JP2003524225A - コンピュータシステムのエラーを処理する方法及び装置 - Google Patents

コンピュータシステムのエラーを処理する方法及び装置

Info

Publication number
JP2003524225A
JP2003524225A JP2001526709A JP2001526709A JP2003524225A JP 2003524225 A JP2003524225 A JP 2003524225A JP 2001526709 A JP2001526709 A JP 2001526709A JP 2001526709 A JP2001526709 A JP 2001526709A JP 2003524225 A JP2003524225 A JP 2003524225A
Authority
JP
Japan
Prior art keywords
error
register
module
packet
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001526709A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003524225A5 (enExample
Inventor
ジョン エス キーン
アジメーア サリー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Graphics Properties Holdings Inc
Original Assignee
Silicon Graphics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Graphics Inc filed Critical Silicon Graphics Inc
Publication of JP2003524225A publication Critical patent/JP2003524225A/ja
Publication of JP2003524225A5 publication Critical patent/JP2003524225A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
JP2001526709A 1999-09-30 2000-09-20 コンピュータシステムのエラーを処理する方法及び装置 Pending JP2003524225A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/409,764 US6457146B1 (en) 1999-09-30 1999-09-30 Method and apparatus for processing errors in a computer system
US09/409,764 1999-09-30
PCT/US2000/025845 WO2001024007A2 (en) 1999-09-30 2000-09-20 Method and apparatus for processing errors in a computer system

Publications (2)

Publication Number Publication Date
JP2003524225A true JP2003524225A (ja) 2003-08-12
JP2003524225A5 JP2003524225A5 (enExample) 2007-11-08

Family

ID=23621860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001526709A Pending JP2003524225A (ja) 1999-09-30 2000-09-20 コンピュータシステムのエラーを処理する方法及び装置

Country Status (4)

Country Link
US (1) US6457146B1 (enExample)
EP (1) EP1221229A2 (enExample)
JP (1) JP2003524225A (enExample)
WO (1) WO2001024007A2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6751698B1 (en) * 1999-09-29 2004-06-15 Silicon Graphics, Inc. Multiprocessor node controller circuit and method
US7539134B1 (en) * 1999-11-16 2009-05-26 Broadcom Corporation High speed flow control methodology
US8024639B2 (en) 2006-06-23 2011-09-20 Schweitzer Engineering Laboratories, Inc. Software and methods to detect and correct data structure
US20080155293A1 (en) * 2006-09-29 2008-06-26 Schweitzer Engineering Laboratories, Inc. Apparatus, systems and methods for reliably detecting faults within a power distribution system
US20080080114A1 (en) * 2006-09-29 2008-04-03 Schweitzer Engineering Laboratories, Inc. Apparatus, systems and methods for reliably detecting faults within a power distribution system
US7900093B2 (en) * 2007-02-13 2011-03-01 Siemens Aktiengesellschaft Electronic data processing system and method for monitoring the functionality thereof
US8441768B2 (en) 2010-09-08 2013-05-14 Schweitzer Engineering Laboratories Inc Systems and methods for independent self-monitoring
US9007731B2 (en) 2012-03-26 2015-04-14 Schweitzer Engineering Laboratories, Inc. Leveraging inherent redundancy in a multifunction IED
CN108632142B (zh) * 2018-03-28 2021-02-12 华为技术有限公司 节点控制器的路由管理方法和装置
US11323362B2 (en) 2020-08-07 2022-05-03 Schweitzer Engineering Laboratories, Inc. Resilience to single event upsets in software defined networks

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05241985A (ja) * 1992-03-03 1993-09-21 Mitsubishi Electric Corp 入出力制御装置
US5414713A (en) * 1990-02-05 1995-05-09 Synthesis Research, Inc. Apparatus for testing digital electronic channels
US5465250A (en) * 1993-06-24 1995-11-07 National Semiconductor Corporation Hybrid loopback for FDDI-II slave stations
JPH08249257A (ja) * 1995-03-15 1996-09-27 Nec Corp シリアルデータ受信装置
JPH08272719A (ja) * 1995-03-30 1996-10-18 Mitsubishi Electric Corp 通信インタフェース回路
JPH08272705A (ja) * 1995-03-31 1996-10-18 Fujitsu Ltd 情報処理方法及び情報処理装置
JPH09504149A (ja) * 1993-10-20 1997-04-22 エルエスアイ・ロジック・コーポレーション 非同期転送モード（ａｔｍ）ネットワーク・デバイス
JPH09506727A (ja) * 1993-12-13 1997-06-30 クレイ・リサーチ・インコーポレイテッド 大規模並列処理システムのためのメッセージ機構
WO1999012102A1 (en) * 1997-09-05 1999-03-11 Sun Microsystems, Inc. A multiprocessing system including cluster optimization mechanisms

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5121342A (en) 1989-08-28 1992-06-09 Network Communications Corporation Apparatus for analyzing communication networks
US6012148A (en) * 1997-01-29 2000-01-04 Unisys Corporation Programmable error detect/mask utilizing bus history stack

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5414713A (en) * 1990-02-05 1995-05-09 Synthesis Research, Inc. Apparatus for testing digital electronic channels
JPH05241985A (ja) * 1992-03-03 1993-09-21 Mitsubishi Electric Corp 入出力制御装置
US5465250A (en) * 1993-06-24 1995-11-07 National Semiconductor Corporation Hybrid loopback for FDDI-II slave stations
JPH09504149A (ja) * 1993-10-20 1997-04-22 エルエスアイ・ロジック・コーポレーション 非同期転送モード（ａｔｍ）ネットワーク・デバイス
JPH09506727A (ja) * 1993-12-13 1997-06-30 クレイ・リサーチ・インコーポレイテッド 大規模並列処理システムのためのメッセージ機構
JPH08249257A (ja) * 1995-03-15 1996-09-27 Nec Corp シリアルデータ受信装置
JPH08272719A (ja) * 1995-03-30 1996-10-18 Mitsubishi Electric Corp 通信インタフェース回路
JPH08272705A (ja) * 1995-03-31 1996-10-18 Fujitsu Ltd 情報処理方法及び情報処理装置
WO1999012102A1 (en) * 1997-09-05 1999-03-11 Sun Microsystems, Inc. A multiprocessing system including cluster optimization mechanisms

Also Published As

Publication number Publication date
WO2001024007A2 (en) 2001-04-05
US6457146B1 (en) 2002-09-24
EP1221229A2 (en) 2002-07-10
WO2001024007A3 (en) 2002-01-10

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