JP2003348848A - Power factor improving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power factor improving circuit which can safely and surely stop an output voltage detecting circuit in the case that its operation goes wrong. <P>SOLUTION: The power factor improving circuit, which gets the output voltage of DC by inputting the full-wave-rectified voltage from an AC power source 1 via a choke coil 67 and turning it on or turning it off by a switching element 6, and rectifying and filtering it, is equipped with an output voltage detecting circuit which gets the first detection voltage for controlling the output voltage into a certain value, nonlatching overvoltage detecting circuit 77 for detecting whether the output voltage has reached a specified overvoltage value larger than the above certain value or not, a latching output voltage detecting circuit 81 which shows that the output voltage has reached the overvoltage reference voltage, a control circuit 6 which turns on or off the switching element 68, based on the first detection voltage and the second detection voltage, and a diode 80 which disables the nonlatching overvoltage detecting circuit 77 in cooperation with that disableness, when the output voltage detecting circuit is disabled. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protection circuit for a power factor correction circuit.

[0002]

2. Description of the Related Art FIG. 4 shows an example of such a conventional power factor correction circuit. In FIG. 4, a sine wave voltage from an AC power supply 1 passes through a filter 2 and is full-wave rectified by a full-wave rectifier circuit 3, and a full-wave rectified waveform passes through a filter 4 and is supplied to a power factor improvement circuit 5. . The power factor improvement circuit 5 includes a choke coil 6
7 is a step-up active filter system including a main winding 67a, a switching element 68, a diode 70, and an output capacitor 71, and has a control circuit 6 as a control system.

Next, the operation of the power factor correction circuit 5 shown in FIG. 4 will be described. First, one end of the critical detection winding 67b of the choke coil 67 is connected to GND, and the other end is connected to the + of the comparator 54 via the resistor 66 and the DET terminal.
The third reference voltage 53 is input to the input terminal, and at the same time, to the negative input terminal of the comparator 54. The comparator 54 compares the two input voltages, and
Outputs a low-level set signal to the flip-flop 62.

A flip-flop 62 is a comparator 54
Is set in response to the set signal from the switch, a high-level drive signal is supplied from the Q output terminal to the gate terminal of the switching element 68 via the AND circuit 64, and the switching element 68 is turned on. Switching element 68
Is turned on, a switching current flows from the AC power supply 1 to GND via the main winding 67a of the choke coil 67, the drain-source of the switching element 68, and the current detecting resistor 69, and energy is stored in the choke coil 67. .

At this time, the switching current flowing through the switching element 68 is
The voltage is converted into a voltage by a current detection resistor 69 provided between GND and input to the + input terminal of the comparator 56,
The current is compared with the current target value Vm output from the multiplier 55 by the comparator 56.

When the switching current reaches the current target value Vm, a high-level reset signal is output from the comparator 56 to the flip-flop 62 via the OR circuit 61. The flip-flop 62 is reset in response to a reset signal from the comparator 56, the high-level drive signal output from the Q output terminal switches to low level, and the switching element 68 is turned off.

When the switching element 68 is turned off, the energy stored in the choke coil 67 and the voltage supplied from the filter 4 are combined, and the output capacitor 71 is charged through the diode 70. As a result, a voltage boosted above the peak value of the full-wave rectified waveform supplied from the filter 4 is output to the output capacitor 71.

When the release of the energy stored in the choke coil 67 ends, the winding voltage of the choke coil 67 is inverted. This winding voltage is detected by the criticality detection winding 67b of the choke coil 67, and the resistance 66 and DE
It is input to the comparator 54 via the T terminal. The comparator 54 calculates the voltage from the DET terminal and the third reference voltage 5
3 and the comparator 54 outputs a low-level set signal to the flip-flop 62. As a result, the flip-flop 62 is set in response to the set signal from the comparator 54, and a high-level drive signal is again input to the gate terminal of the switching element 68, and the switching element 68 is turned on. That is, when the release of the energy of the choke coil 67 ends, the flip-flop 62 is set again, and the switching element 6
8 is turned on.

The output voltage from the output capacitor 71 is divided by a resistor 73, a resistor 74, and a resistor 75 and input to an operational amplifier 57 via a CV terminal.
As a result, the difference signal from the first reference voltage 58 is amplified and the error signal output is supplied to the multiplier 55.

The full-wave rectified waveform from the filter 4 has a resistance 5
1 and 52, and is divided by a multiplier 55 through an AC terminal.
And the multiplier 55 multiplies the full-wave rectified waveform by the error signal. The multiplied output is supplied to the negative input terminal of the comparator 56. The output of the multiplier 55 changes the full-wave rectified waveform (pulse current waveform) according to the output voltage.
It becomes the current target value Vm of the switching current detected via the S terminal.

Thereafter, the output voltage of the output capacitor 71 of the power factor correction circuit 5 is kept constant by repeating such an operation. At the same time, the current flowing through the AC power supply 1 has a sinusoidal current waveform following the voltage of the AC power supply 1.

The power factor improving circuit 5 has a latch type output overvoltage detecting circuit 81 for stopping the power factor improving circuit 5 when the output voltage becomes overvoltage due to a failure or the like. The latch-type output overvoltage detection circuit 81 divides the output voltage by a resistor 83 and a resistor 84, compares the divided voltage with a reference voltage 86 and a comparator 85.
5 outputs a high level to the latch circuit 87, sets the latch circuit 87, sends a stop signal to the OFF terminal of the control circuit 6, and stops the power factor correction circuit 5.

Further, the power factor improving circuit 5 converts the voltage of the resistor 75 of the output voltage detecting circuit 72 including the resistor 73, the resistor 74 and the resistor 75 into an operational amplifier 5 in order to keep the output voltage constant.
7, the feedback control is performed. In order to make the current flowing in the AC power supply 1 sinusoidal, it is necessary to sufficiently slow down the response corresponding to the frequency of the sinusoidal wave.
Therefore, a relatively large phase compensation capacitor 76 is connected between the FB terminal and the CV terminal. As a result, the response can be sufficiently delayed in accordance with the frequency of the sine wave, but the response is slow, so that there is a problem that the output voltage rises in a short period due to a sudden change in input, a sudden change in load, or the like.

In order to solve this problem, the control circuit 6 is provided with an OVP terminal. The OVP terminal receives the voltage at the connection point between the resistance 73 and the resistance 74 of the output voltage detection circuit 72, and The voltage is set to a voltage slightly higher than the voltage of the CV terminal. From the OVP terminal to the second reference voltage 60
When a larger voltage is input, the comparator 59 outputs a high level. The output of the comparator 59 resets the flip-flop 62 via the OR circuit 61,
The switching element 68 is turned off. As a result, the switching element 68 is turned off only during a period in which the output voltage is in an overvoltage state and is rising due to a sudden change in input or a sudden change in load,
The output voltage is prevented from rising.

However, since the power factor improving circuit shown in FIG. 4 has a relatively large phase compensating capacitor 76, the voltage of the FB terminal affects the voltage of the OVP terminal, and the response speed of the OVP terminal is slightly reduced. This has the disadvantage that the output voltage rises transiently.

In order to avoid this disadvantage, the power factor improving circuit shown in FIG.
8, a non-latch type output overvoltage detection circuit 7 including a resistor 79
7 is added, and the voltage at the connection point between the resistor 78 and the resistor 79 is changed to O.
Input to the VP terminal. That is, the configuration is not affected by the phase compensation capacitor 76 at all, and a speed response is possible.

[0017]

However, the power factor improving circuit shown in FIG. 5 has the following problems. For example, when the resistor 73 of the output voltage detection circuit 72 is open (OPEN), in the power factor correction circuit shown in FIG.
Since 9 does not function, the output voltage increases. In the case of such a failure, the latch type output overvoltage detection circuit 81 operates to stop the power factor correction circuit safely.

However, in the power factor improving circuit shown in FIG.
When the resistance 73 becomes OPEN, the resistance 78 and the resistance 79
Is applied to the OVP terminal, and the output voltage is made constant by the set voltage of the OVP terminal. That is, CV
Although the power factor improvement circuit does not function properly due to the stoppage of the voltage application to the terminal, the power factor improvement circuit has a disadvantage that the power factor improvement circuit continues to operate by applying the voltage to the OVP terminal. Also,
Since the output voltage at this time is the set voltage of the OVP terminal, the output voltage is larger than a normal value and has a disadvantage that devices connected to the subsequent stage of the power factor correction circuit are adversely affected.

An object of the present invention is to improve the power factor by which the latch-type output overvoltage detection circuit can be safely and reliably stopped when the operation of the output voltage detection circuit becomes defective. It is to provide a circuit.

[0020]

According to a first aspect of the present invention, a full-wave rectified waveform obtained by rectifying an AC voltage supplied from an AC power supply is input via a choke coil. A power factor improving circuit that is turned on / off by a switching element, rectifies and smoothes to obtain a DC output voltage, and detects the output voltage to obtain a first detection voltage in order to control the output voltage to a constant value. An output voltage detection circuit, a non-latch type output overvoltage detection circuit for obtaining a second detection voltage used to detect whether or not the output voltage has reached a predetermined overvoltage value larger than the fixed value; A latch-type output overvoltage detection circuit that compares an output voltage with an overvoltage reference voltage for detecting an overvoltage state of the output voltage, and latches an output indicating that the output voltage has reached the overvoltage reference voltage; The switching element based on a first detection voltage obtained by the output voltage detection circuit, a second detection voltage obtained by the non-latch type output overvoltage detection circuit, and a latch output from the latch type output overvoltage detection circuit. And an interlocking element that, when the output voltage detection circuit becomes inoperable, makes the non-latch type overvoltage detection circuit inoperative in conjunction with the nonoperation. .

According to a second aspect of the present invention, the interlocking element is a diode connecting the output voltage detection circuit and the non-latch type overvoltage detection circuit.

According to a third aspect of the present invention, in the output voltage detecting circuit, a first resistor and a second resistor are connected in series, and the non-latch type overvoltage detecting circuit includes a third resistor and a second resistor. 4 is connected in series, a cathode of the diode is connected to a connection point between the first resistor and the second resistor, and a connection is established between the third resistor and the fourth resistor. The point is connected to the anode of the diode.

According to a fourth aspect of the present invention, the control circuit amplifies a difference signal between the first detection voltage and the first reference voltage obtained by the output voltage detection circuit and outputs an error signal. Generating means for generating a current target value interlocked with the full-wave rectified waveform from a full-wave rectified waveform obtained by rectifying an AC voltage supplied from the AC power supply and an error signal from the error signal generating means; Target value generation means, first off control means for turning off the switching element when the value of the switching current flowing during the ON period of the switching element reaches the current target value from the current target value generation means,
Second off control means for turning off the switching element when a second detection voltage from the non-latch type output overvoltage detection circuit reaches a second reference voltage; and a latch output from the latch type output overvoltage detection circuit. And a third off-control means for turning off the switching element when is input.

[0024]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a power factor correction circuit according to the present invention. FIG. 1 is a diagram showing a configuration of a power factor correction circuit according to an embodiment of the present invention. The power factor correction circuit according to the embodiment is different from the conventional power factor correction circuit shown in FIG.
It is characterized by being added between V terminals.

In FIG. 1, a filter 2
The sine wave voltage that has passed through the filter 2 is full-wave rectified by the full-wave rectifier circuit 3 and passes through the filter 4, and the full-wave rectified waveform from the filter 4 is applied to the power factor correction circuit 5. Supplied to The filters 2 and 4 remove noise components leaking from the power factor correction circuit 5 to the AC power supply 1 side.
Further, the filters 2 and 4 can be omitted.

Next, the configuration of the power factor improving circuit 5 will be described in detail. The power factor improving circuit 5 includes a main winding 67a of a choke coil 67, a switching element 68, and a diode 7.
0, a step-up type active filter system including an output capacitor 71.

The choke coil 67 is provided with a main winding 67a and a criticality detection winding 67b. Main winding 67a
Is connected to one end of the filter 4 and the resistor 51, and the other end of the main winding 67a is connected to the drain of the switching element 68 and the anode of the diode 70. One end of the criticality detection winding 67b is connected to the + input terminal of the comparator 54 via the resistor 66 and the DET terminal, and the other end of the criticality detection winding 67b is connected to GND. The cathode of the diode 70 is connected to one end of the output capacitor 71, one end of the resistor 73, one end of the resistor 78, and one end of the resistor 83.

The resistor 73, the resistor 74, and the resistor 75 constitute an output voltage detection circuit 72. The output voltage detection circuit 72
In order to control the output voltage of the output capacitor 71 to a constant value, the output voltage is detected, and the voltage of the resistor 75 is output to the CV terminal as a first detection voltage.

The resistor 78 and the resistor 79a constitute a non-latch type output overvoltage detection circuit 77. The non-latch type output overvoltage detection circuit 77 determines whether the output voltage has reached a predetermined overvoltage value larger than a predetermined value. The second used to detect
The voltage of the resistor 79a is output to the OVP terminal as the detection voltage of the above.

The cathode of the diode 80 is connected to the connection point between the resistor 74 and the resistor 75, and the resistor 78 and the resistor 7
The anode of the diode 80 is connected to the connection point with 9a. Note that the resistance of the resistor 79a is set so that the voltage of the resistor 75 is higher than the voltage of the resistor 79a in order to normally turn off the diode 80.

A latch-type output overvoltage detection circuit 81 divides the output voltage by a resistor 83 and a resistor 84, compares the divided voltage with a reference voltage 86 and a comparator 85, and outputs a high level signal from the comparator 85 to the latch circuit 87 when an overvoltage occurs. Is output, the latch circuit 87 is set, and the OF of the control circuit 6 is turned off.
A stop signal is sent to the F terminal to stop the power factor correction circuit 5.

Next, the configuration of the control circuit 6 which is a control system of the power factor improvement circuit 5 will be described. + Of the comparator 54
The input terminal is a DET terminal, a resistor 66, a critical detection winding 6
7b is connected to GND. The third reference voltage 53 is input to a negative input terminal of the comparator 54. The comparator 54 compares both input voltages,
When the voltage generated in the criticality detection winding 67b input to the + input terminal is lower than the third reference voltage 53, a low-level set signal is output to the set terminal of the flip-flop 62.

The set terminal of the flip-flop 62 has
The output terminal of the comparator 54 is connected, the reset terminal is connected to the output terminal of the comparator 56 via the OR circuit 61, and the Q output terminal is connected to the gate terminal of the switching element 68 via the AND circuit 64. . When a low-level set signal is input from the comparator 54, the flip-flop 62 outputs a high-level drive signal to the Q output terminal. When a high-level reset signal is input from the comparator 56 via the OR circuit 61, a low level is output to the Q output terminal.

The voltage between the terminals of the output capacitor 71 is divided by resistors 73, 74 and 75 and inputted to the minus input terminal of the operational amplifier 57, and the first reference voltage 58 is inputted to the plus input terminal. Is connected between the input terminal and the output terminal. The operational amplifier 57 has an amplification gain set by the resistors 73, 74, 75 and the phase compensation capacitor 76, and a divided voltage corresponding to the output voltage of the output capacitor 71 and the first voltage.
The difference signal from the reference voltage 58 is amplified and an error signal is supplied to the multiplier 55.

A voltage obtained by dividing the full-wave rectified waveform from the full-wave rectifier circuit 3 by the resistors 51 and 52 is input to one input terminal of the multiplier 55, and an error from the operational amplifier 57 is input to the other input terminal. The signal is input, and the multiplier 55 multiplies the full-wave rectified waveform by the error signal and supplies the current target value Vm interlocked with the full-wave rectified waveform to the negative input terminal of the comparator 56.

The negative input terminal of the comparator 56 is supplied with the current target value Vm of the switching current from the multiplier 55. The + input terminal of the comparator 56 is connected to a current detecting resistor 69 via the CS terminal. 6
The voltage corresponding to the drain-source current when 8 is in the ON period is input as a current detection value. When the switching current reaches the current target value Vm linked with the full-wave rectification waveform, a high-level reset signal is output from the comparator 56 to the flip-flop 62 via the OR circuit 61.

The second reference voltage 60 is inputted to the minus input terminal of the comparator 59, and the divided voltage of the resistor 78 and the resistor 79a is inputted to the plus input terminal of the comparator 59 via the OVP terminal. When the voltage reaches the second reference voltage 60, a high-level reset signal is output to the flip-flop 62 via the OR circuit 61.

The inverter circuit 63 inverts the stop signal input from the latch circuit 87 via the OFF terminal and sends a low level drive signal to the gate terminal of the switching element 68 via the AND circuit 64, Turn off 68.

Next, the operation of the power factor correction circuit will be described. When the AC power supply 1 is applied, the sine wave voltage supplied from the AC power supply 1 is full-wave rectified by the full-wave rectification circuit 3, and the full-wave rectified waveform is supplied to the power factor correction circuit 5.

(1) Operation at Startup First, the + input terminal of the comparator 54 is grounded via the resistor 66 and the criticality detection winding 67b. The third reference voltage 53 is input. In the comparator 54,
The two input voltages are compared, and the voltage at the + input terminal is lower in potential, so the comparator 54 outputs a low-level set signal to the flip-flop 62.

The flip-flop 62 is connected to the comparator 5
4, a high-level drive signal is output from the Q output terminal, and the switching element 68 is turned on via the AND circuit 64, as shown at a timing t 1 shown in FIG. 2.

When the switching element 68 is turned on, FIG.
As shown at a timing t1 shown in FIG.
Drain voltage Vd drops to near 0V. Then, the main winding 67a, the switching element 68
GN via the drain-source of the current detection resistor 69
A switching current flows to D, and energy is stored in the choke coil 67.

At this time, the switching current flowing through the switching element 68 is converted into a voltage Vs by a current detecting resistor 69 provided between the source of the switching element 68 and GND, as shown in FIG.
The current is input to the input terminal and is compared with a current target value Vm linked with the full-wave rectified waveform output from the multiplier 55 by the converter 56.

(2) Current target value Vm A capacitor 76 of, for example, 0.68 μF for relatively large phase compensation is provided between the CV terminal and the FB terminal. ,
74, an error signal which is divided by a resistor 75, input to a negative input terminal of an operational amplifier 57 via a CV terminal, and amplifies and outputs a difference signal between a divided value of an output voltage and a first reference voltage 58. Is supplied from the operational amplifier 57 to the multiplier 55.

On the other hand, the full-wave rectified waveform from the full-wave rectifier circuit 3 is divided by the resistors 51 and 52 and input to the multiplier 55.

In the multiplier 55, a voltage is generated by multiplying the error signal from the operational amplifier 57 by the full-wave rectified waveform from the full-wave rectifier circuit 3, and the current target value V linked with the full-wave rectified waveform is generated.
The signal m is supplied to the negative input terminal of the comparator 56.

(3) Switching element off control As shown at timing t2 in FIG. 2, the current detection value of the switching current is changed to the current target value Vm linked with the full-wave rectified waveform.
, A high-level reset signal is output from the comparator 56 to the flip-flop 62 via the OR circuit 61. The flip-flop 62 includes a comparator 56
, The high-level drive signal output from the Q output terminal is switched to a low level, and the switching element 68 is turned off.

When the switching element 68 is turned off, the energy stored in the choke coil 67 and the voltage supplied from the filter 4 are combined, and the output capacitor 71 is charged through the diode 70.

As a result, a voltage boosted above the peak value of the full-wave rectified waveform supplied from the filter 4 is output to the output capacitor 71.

(4) ON control of the switching element Next, when the release of the energy stored in the choke coil 67 ends, a ringing voltage is generated in the criticality detection winding 67b, and the voltage of the criticality detection winding 67b is increased. Is inverted. This voltage is supplied to a third reference voltage 53 and a comparator 54.
At timing t3 shown in FIG.
A low-level set signal is output from the comparator 54 to the flip-flop 62.

As a result, the flip-flop 62 is set according to the set signal from the comparator 54.
As shown at timing t3, the high-level drive signal is input to the gate terminal of the switching element 68 again, and the switching element 68 is turned on.

Thereafter, by repeating such an operation,
The output voltage at the output capacitor 71 of the power factor correction circuit 5 is kept constant. At the same time, the current flowing through the AC power supply 1 has a sinusoidal current waveform following the voltage of the AC power supply 1.

(5) When the output voltage detection circuit 72 is operating normally The normal operation of the output voltage detection circuit 72 will now be described. In this case, since the voltage of the resistor 75 is higher than the voltage of the resistor 79a, the diode 80 is turned off.
Therefore, the output voltage detection circuit 72 and the non-latch type overvoltage detection circuit 77 are completely disconnected from each other, so that the OVP terminal side is not affected by the phase compensation capacitor 76 at all.

As a result, since the divided voltage of the resistor 78 and the resistor 79a is input to the + input terminal of the comparator 59 via the OVP terminal, the comparator 59 operates at a high speed, and causes a sudden input change and a sudden load change. Also, as shown in FIG. 3, the output voltage is made constant at the OVP level which is the set voltage of the OVP terminal. For this reason, output overvoltage can be reliably prevented.

(6) When the operation of the output voltage detecting circuit 72 becomes defective Here, as an example of the case where the operation of the output voltage detecting circuit 72 becomes defective, the operation when the resistor 73 becomes OPEN will be described. . When the resistance 73 becomes OPEN, the resistance 7
3. Since no current flows through the path of the resistor 74 and the resistor 75,
The voltage at the CV terminal drops. Thereby, the diode 8
When 0 is turned on, the current flows from the resistor 78 to the resistor 75 via the diode 80, and the current also flows from the resistor 78 to the resistor 79a. Therefore, the resistance of the OVP terminal is
Since the resistance becomes a parallel resistance of the resistance 75 and the resistance 79a and has a small resistance value, the OVP terminal does not function with respect to the OPEN of the resistance 73. That is, since the comparator 59 does not function at the time of overvoltage, the output voltage becomes overvoltage. However, the latch-type output overvoltage detection circuit 81 operates and the power factor improvement circuit 5 can be safely and reliably stopped.

[0056]

As described above, according to the present invention,
If the operation of the output voltage detection circuit becomes defective, the operation of the non-latch type output overvoltage detection circuit is prohibited, and the power factor improvement circuit is safely operated by reliably operating the latch type output overvoltage detection circuit. It can be stopped reliably.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a power factor correction circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of the power factor correction circuit according to the embodiment;

FIG. 3 is a waveform for explaining the operation of the power factor correction circuit.

FIG. 4 is a diagram showing a configuration of an example of a conventional power factor correction circuit.

FIG. 5 is a diagram illustrating a configuration of another example of a conventional power factor correction circuit.

[Explanation of symbols]

Reference Signs List 1 AC power supply 2, 4 Filter 3 Full-wave rectifier circuit 5 Power factor improvement circuit 6 Control circuit 54, 56, 59, 85 Comparator 55 Multiplier 62 Flip-flop 57 Operational amplifier 63 Inverter circuit 61 OR circuit 64 AND circuit 67 Choke coil 68 Switching Element 70 Diode 71 Output capacitors 51, 52, 66, 73 to 75, 78, 79, 79a,
83, 84 Resistance 76 Phase compensation capacitor 80 Diode 72 Output voltage detection circuit 77 Non-latch type output overvoltage detection circuit 81 Latch type output overvoltage detection circuit 87 Latch circuit 69 Current detection resistance

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Seiya Fukumoto             3-6-3 Kitano, Niiza-shi, Saitama             Electric Co., Ltd. F-term (reference) 5H006 AA05 CA02 CB01 DB01 DC05                       FA01 GA04

Claims (4)

[Claims] 1. A power factor for inputting a full-wave rectified waveform obtained by rectifying an AC voltage supplied from an AC power supply via a choke coil, turning on / off by a switching element, rectifying and smoothing to obtain a DC output voltage. An improvement circuit, comprising: an output voltage detection circuit that detects the output voltage to obtain a first detection voltage to control the output voltage to a constant value; and a predetermined overvoltage in which the output voltage is greater than the constant value. A non-latch type output overvoltage detection circuit that obtains a second detection voltage used to detect whether or not the output voltage has reached a value, and an output voltage and an overvoltage reference voltage for detecting an overvoltage state of the output voltage. A latch-type output overvoltage detection circuit that compares and latches an output indicating that the output voltage has reached the overvoltage reference voltage; a first detection voltage obtained by the output voltage detection circuit; A control circuit for controlling on / off of the switching element based on a second detection voltage obtained by the type output overvoltage detection circuit and a latch output from the latch type output overvoltage detection circuit; and the output voltage detection circuit becomes inoperative. A non-latching type overvoltage detection circuit that is deactivated in response to the non-operation. 2. The power factor improving circuit according to claim 1, wherein said interlocking element is a diode connecting said output voltage detecting circuit and said non-latch type overvoltage detecting circuit. 3. The output voltage detection circuit includes a first resistance and a second resistance connected in series, and the non-latch type overvoltage detection circuit includes a third resistance and a fourth resistance. The diode is connected in series, a cathode of the diode is connected to a connection point between the first resistance and the second resistance, and a connection point of the diode is connected to a connection point between the third resistance and the fourth resistance. An anode is connected to the anode.
Power factor improvement circuit described. 4. The control circuit, comprising: a first detection voltage obtained by the output voltage detection circuit;
An error signal generating means for amplifying a difference signal with respect to the reference voltage and outputting an error signal; and a full-wave rectified waveform obtained by rectifying an AC voltage supplied from the AC power supply and an error from the error signal generating means. A current target value generating means for generating a current target value interlocked with the full-wave rectified waveform from the signal, and a value of a switching current flowing during an ON period of the switching element reaches a current target value from the current target value generating means. First off control means for turning off the switching element when the second detection voltage from the non-latch type output overvoltage detection circuit reaches a second reference voltage. 2 off-control means, and third off-control means for turning off the switching element when a latch output is input from the latch-type output overvoltage detection circuit. The power factor improving circuit according to any one of claims 1 to 3, wherein