JP2003345732A - Serial communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the processing load of a CPU in performing a communication and to reduce the burden of the CPU by reducing interruption processing needed in performing a serial communication. <P>SOLUTION: The serial communication device has a transmission buffer 111 and a reception buffer 112 for storing respective second addresses for transmission and reception, selectors (116 and 117) for selecting one among the addresses of the two buffers and a self-address 2, and an address determination control circuit 109 for comparing address data. Since the addresses held in the buffers (111 and 112) can be directly compared with the address of a shift register 108, interruption to the CPU 114 can be reduced, and the processing of the CPU 114 performed in communication is reduced to be able to reduce the burden of the CPU 114. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a serial communication device such as an I2C communication device for performing communication between a master controller and a slave controller.

[0002]

2. Description of the Related Art A conventional serial communication device will be described below using an I2C communication device as an example.

FIG. 8 is a block diagram of a conventional I2C communication device, and FIG. 9 is a diagram showing communication data and an interrupt generation timing in the conventional I2C communication device. In FIG. 8, I2C
The communication device corresponds to a controller that performs a slave transmission / reception operation of a 7-bit address protocol by software for a slave transmission / reception operation of a 10-bit address protocol.

[0004] The configuration of the I2C communication device 800 will be described below. The clock control circuit 803 controls an I2C bus clock signal line (hereinafter, referred to as an I2C bus SCL) 80 in response to an interrupt signal output from the interrupt generation circuit 806.
1 clock signal output control.

The data control circuit 805 outputs the serial data of the shift register 808 to the data signal line of the I2C bus (hereinafter referred to as I2C bus SDA) 802 at the time of transmission, and the serial data input from the I2C bus SDA 802 at the time of reception. Output to the shift register 808. Also,
An acknowledgment is output to the I2C bus SDA802 in response to the output of the address determination control circuit 809. At the time of the reception operation, the presence / absence of acknowledgment transmission can be set by the setting of the CPU 814.

[0006] The bus state detection circuit 804 is an I2C bus S
A communication start condition is detected by monitoring the states of the CL 801 and the I2C bus SDA 802, and a start detection signal is output when the start condition is detected.

When an address match signal from the address determination control circuit 809 or a buffer access request signal from the data transfer control circuit 807 is input, the interrupt generation circuit 806 controls the clock control circuit 803 and the CPU 81
4 is output as an interrupt signal.

A data transfer control circuit 807 controls a transmission operation and a reception operation according to a transmission / reception switching signal from the address determination control circuit 809. If the transmission / reception switching signal is a transmission selection signal, the data transfer control circuit 807 enters the transmission mode, reads out byte data for transmission from the transmission buffer 811 and then transfers it to the shift register 808 to start serial transmission. After serial transmission, it outputs a buffer access request signal to interrupt generation circuit 806. When the transmission / reception switching signal is a reception selection signal,
The data transfer control circuit 807 enters the reception mode, reads out the byte data received from the shift register 808, transfers it to the reception buffer 812, and outputs a buffer access request signal to the interrupt generation circuit 806. However, the output of the buffer access request signal at the time of reception is always before transmission of the acknowledge.

The shift register 808 is a one-byte shift register. When performing a receiving operation, the shift register 808 performs a shifting operation on the serial data input from the data control circuit 805 from the LSB side. Also,
When performing the transmission operation, the shift register 808 shifts the serial data from the MSB side and outputs the serial data to the data control circuit 805.

The transmission buffer 811 is a one-byte data buffer, and stores transmission data. The transmission buffer 811 reads out transmission data from the CPU 814 under the control of the control circuit 807.

The reception buffer 812 is a 1-byte data buffer, and stores received data. The reception buffer 812 writes the data received under the control of the data transfer control circuit 807 to the CPU 814.

The host I / F 813 includes a transmission buffer 81
1 from the CPU 814 and the reception buffer 812
Control of writing to. The CPU 814 is an I2C
A central processing unit that controls the communication device 800 and processes data.

The self address 1 register 810 is a 7-bit register and stores a self address 1 which is a slave address corresponding to the present slave controller among slave addresses for identifying each slave controller.

An address determination control circuit 809 controls the transmission of an acknowledgment by the interrupt generation circuit 806 and the data control circuit 805 and the transmission and reception of the data transfer control circuit 807 according to the data comparison result between the shift register 808 and the self address 1 register 810. Perform control.

The operation performed by the I2C communication device having the above configuration will be described with reference to FIG. When receiving data,
When the bus state detection circuit 804 detects the start condition (S), it sends a control signal to the data transfer control circuit 807, and the slave controller performs an address reception and determination operation. The data of the address 1 is transferred to the shift register 80 via the I2C bus SDA 802 and the data control circuit 805.
8 is stored. Next, when 7 bits of address + communication direction bit = 8 bits are stored in the shift register 808, the value of the self address 1 register 810 in which the self address 1 is written in advance is compared with the value of the shift register 808 by address determination control by software. The circuit 809 performs this operation, and if they match, outputs an acknowledge (A) output request signal to the data control circuit 805. At this time, since the communication direction bit for determining the transmission / reception operation is "0", the data transfer control circuit 807 switches the controller to the reception operation as the next operation (9a). Next, the data of the address 2 is stored in the shift register 808 in the same manner as the address 1, and the data transfer control circuit 807 transfers the stored address 2 to the reception buffer 812. After the transfer is completed, an interrupt request is sent to the interrupt generation circuit 806, and the controller outputs an interrupt. Then, address 2 by software
Is determined and whether the acknowledgment is output or not is set for the slave controller (9b). next,
When the restart sequence is not detected, the controller continues the byte reception operation of the slave reception (9c, 9d) until the restart condition (Sr) or the stop condition (P) is transmitted (9e). When the restart sequence is detected, the operation of comparing the data of the address 1 is performed again, and the process is continued. Here, since the communication direction bit is “1”, the data transfer control circuit 807 switches the slave controller to the transmission operation (9f). Next, until the restart condition (Sr) or the stop condition (S) is transmitted (9i), the slave controller performs the byte data transmission operation (9g, 9h). The data transfer control circuit 807 transfers the data written to the transmission buffer 811 to the shift register 808, and the serial data is transferred to the I2C bus S via the data control circuit 805.
Output to DA802. Every time the acknowledge bit is completed, the data transfer control circuit 807 issues an interrupt request to the interrupt generation circuit 806, and the slave controller outputs an interrupt.

[0016]

SUMMARY OF THE INVENTION Problems to be Solved by the Invention
1 in I2C communication device dedicated to bit address format
When the 0-bit address format is supported by software processing, as shown in FIG.
Requires an interrupt from the I2C communication device. The reason for this is that when comparing address 2, it is necessary to read the data at address 2 from the reception buffer by software and to compare it with the data at its own address held by software, and an interrupt for that processing is issued. Because it becomes indispensable. Since an interrupt from the peripheral device to the CPU occurs, there is a problem that the number of processes that can be performed by the CPU is reduced.

In order to solve the above problems, the serial communication device of the present invention reduces the number of interrupts required for communication, thereby reducing the amount of processing performed by the CPU during communication and reducing the load on the CPU. It is intended to be light.

[0018]

According to a first aspect of the present invention, there is provided a serial communication apparatus for serially transmitting communication data and transmitting / receiving the communication data to / from an external device. A shift register, a data control circuit for transferring received data of the communication data sequentially communicated to the shift register, a first data buffer for holding the received data shifted by the shift register, When the second received data is input to the data control circuit after the shift register shifts the first received data, the first received data is transferred to the first data buffer, and the second received data is transferred to the first data buffer. A data transfer control circuit for transferring the data to the shift register; a register for holding arbitrarily set comparison data; The held in the data buffer 1
A first selector circuit for selecting any of the received data and the comparison data, and a data comparison circuit for comparing the data selected by the first selector circuit with the second received data. Features.

According to a second aspect of the present invention, there is provided a serial communication device comprising:
What is claimed is: 1. A serial communication device, which is an I2C communication device that performs communication via a C bus, comprising: a shift register for shifting the communication data; and data control for transferring received data of the communication data sequentially communicated to the shift register. A circuit, a first data buffer for holding an address of the reception data shifted by the shift register, and a second reception data input to the data control circuit after the shift register shifts the first reception data. And a data transfer control circuit for transferring an address of the first received data to the first data buffer and transferring the second received data to the shift register, and an arbitrarily configurable comparison address. A register and an address of the first reception data held in the first data buffer or the comparison address. And a data comparison circuit for comparing the address selected by the selector circuit with the address of the second received data, wherein the address of the second received data and the selector Data reception is performed when the addresses selected by the circuit match.

According to a third aspect of the present invention, there is provided a serial communication device, comprising:
What is claimed is: 1. A serial communication device, which is an I2C communication device performing communication via a C bus, comprising: a shift register for shifting said communication data; A data control circuit for receiving and outputting the received data from the shift register, a first data buffer for storing the address of the received data shifted by the shift register, and a second data buffer for storing the address of the transmitted data received from the shift register. And a second buffer for transferring the address of the first communication data to the first data buffer when the second communication data is input to the data control circuit after the shift register shifts the first communication data. And the second
A data transfer control circuit for transferring communication data to the shift register; an address data transfer circuit for controlling transfer of address data between the first data buffer and the second data buffer; A register for holding data, an address of communication data held in the first data buffer, an address of communication data held in the second data buffer, or a comparison address held in the register; A selector circuit for selecting one of the addresses; and a data comparison circuit for comparing the address selected by the selector circuit with the address of the second communication data, wherein the address of the second communication data and the selector circuit are selected. Are transmitted and received when the selected addresses match.

According to a fourth aspect of the present invention, there is provided the serial communication device, wherein the I2
What is claimed is: 1. A serial communication device, which is an I2C communication device performing communication via a C bus, comprising: a shift register for shifting said communication data; A data control circuit for receiving and outputting the communication data from the shift register, a data buffer for holding the address of the communication data shifted by the shift register, and a second communication after the shift register shifts the first communication data. When data is input to the data control circuit, the first
A data transfer control circuit for transferring an address of the communication data to the data buffer and transferring the second communication data to the shift register;
An address holding flag setting circuit that sets a flag when an address of communication data is held, a register that holds arbitrarily set comparison data, and an address held in the data buffer or held in the register A selector circuit for selecting any of the selected comparison addresses, and a data comparison circuit for comparing the address selected by the selector circuit with the address of the second communication data, wherein the flag is not set The transmission / reception is performed by matching the comparison address with the address of the first communication data, and when the flag is set, the address of the second communication data matches the address selected by the selector circuit. It is characterized by transmitting and receiving data.

According to a fifth aspect of the present invention, there is provided the serial communication device, wherein the I2
What is claimed is: 1. A serial communication device, which is an I2C communication device performing communication via a C bus, comprising: a shift register for shifting said communication data; A data control circuit for receiving and outputting the received data from the shift register, a first data buffer for storing the address of the received data shifted by the shift register, and a second data buffer for storing the address of the transmitted data received from the shift register. And a second buffer for transferring the address of the first communication data to the first data buffer when the second communication data is input to the data control circuit after the shift register shifts the first communication data. And the second
A data transfer control circuit that transfers the communication data to the shift register; an address data transfer circuit that controls the transfer of address data between the first data buffer and the second data buffer; The first
An address holding flag setting circuit that sets a flag when the address of the second communication data is held in the data buffer of the first buffer, a register that holds arbitrarily set comparison data, A selector circuit for selecting any one of an address of the held communication data, an address of the communication data held in the second data buffer, and a comparison address held in the register; and the selector circuit Has a data comparison circuit that compares the selected address with the address of the second communication data, and performs data transmission and reception when the address of the second communication data matches the address selected by the selector circuit. It is characterized by the following.

According to a sixth aspect of the present invention, there is provided a serial communication device, comprising:
What is claimed is: 1. A serial communication device, which is an I2C communication device performing communication via a C bus, comprising: a shift register for shifting said communication data; A data control circuit for receiving and outputting the received data from the shift register, a first data buffer for storing the address of the received data shifted by the shift register, and a second data buffer for storing the address of the transmitted data received from the shift register. And a second buffer for transferring the address of the first communication data to the first data buffer when the second communication data is input to the data control circuit after the shift register shifts the first communication data. And the second
A data transfer control circuit for transferring the communication data to the shift register; an address data transfer circuit for controlling the transfer of address data between the first data buffer and the second data buffer; An operation determination circuit that determines whether the device is in a serial reception operation state;
When the external arithmetic unit performs communication, it is determined by the operation determination circuit that the operation is in the serial reception operation state, and the flag is set when the address of the second communication data is held in the first data buffer. An address holding flag setting circuit to be set; a register for holding arbitrarily set comparison data; and an address of communication data held in the first data buffer or communication data held in the second data buffer Either the address of the address or the address for comparison held in the register
A selector circuit for selecting one of the two addresses, and a data comparing circuit for comparing the address selected by the selector circuit with the address of the second communication data, wherein the address of the second communication data and the selector circuit are selected. The transmission and reception of data is performed when the addresses match.

With the above configuration, by reducing the number of interrupts required during communication, the processing performed by the CPU during communication can be reduced and the load on the CPU can be reduced.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a serial communication device according to the present invention will be described below using an I2C communication device as an example. (Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described with reference to FIGS.

Here, the I2C operating in the slave transmission / reception in the 10-bit address mode without performing the master operation is described.
The communication device will be described. FIG. 1 is a block diagram of an I2C communication device according to Embodiment 1 of the present invention. FIG. 2 is a timing chart of communication data and interruption occurrence in the I2C communication device according to the first embodiment of the present invention, and FIG. 3 is an operation flow diagram of the I2C communication device in the first embodiment of the present invention.

Hereinafter, the configuration of the I2C communication device 100 and the function of each circuit will be described. The clock control circuit 103 sets the Low to the I2C bus SCL101 in response to the signal 106a.
The operation of the entire I2C bus can be stopped for an arbitrary period of time by outputting to the.

When transmitting, the data control circuit 105 transmits the serial data of the shift register 108 to the I2C bus SDA1.
02, and upon reception, the serial data of the I2C bus SDA102 is output to the shift register 108. Also,
When the acknowledgment sending signal 109a is input, the data control circuit 105 sends an acknowledgment to the I2C bus SDA1.
02 is output.

The bus state detection circuit 104 is an I2C bus SC
The start condition is detected by monitoring the states of the L101 and the I2C bus SDA102, and when the start condition is detected, a start detection signal 104a is output. In addition, when an acknowledgment is not detected during transmission and when a start condition or a stop condition is detected during reception, the present circuit outputs a communication end signal 104b.

When the address match signal 109b or the buffer access request signal 107a is input to the interrupt generation circuit 106, the interrupt generation circuit 106 outputs an output of the signal 106a and an interrupt signal 106b.

The data transfer control circuit 107 controls switching between a transmission operation and a reception operation or a non-operation state by a transmission / reception switching signal 109d. When the transmission / reception switching signal 109d is a transmission selection signal, the circuit enters a transmission mode, reads out byte data for transmission from the transmission buffer 111, and then transfers it to the shift register 108 to start serial transmission. Further, this circuit operates after the serial transmission of the byte data is completed.
Is output. When the transmission / reception switching signal 109d is a reception selection signal, the circuit enters the reception mode, reads out the byte data received from the shift register 108, transfers it to the reception buffer 112, and outputs the buffer access request signal 107a and the reception buffer write signal 107b. I do. When the transmission / reception switching signal 109d is neither the transmission selection signal nor the reception selection signal, the circuit does not access the transmission buffer 111 and the reception buffer 112, and
It does not output the buffer access request signal 107a. When the communication end signal 104b is output, the circuit ends the transmission / reception operation and outputs the initialization signal 107c.

The shift register 108 is a one-byte shift register. When performing a reception operation, the shift register 108 outputs the serial data L from the data control circuit 105.
The shift operation is performed while being input from the SB side. When performing a transmission operation, the shift register 108 performs a shift operation while outputting serial data from the MSB side to the data control circuit 105.

The transmission buffer 111 is a one-byte data buffer, and stores transmission data and its own address 2. The transmission buffer 111 is read and written by the host I / F 113, and the data transfer control circuit 10
7, reading is performed. Also, transmission buffer 1
The data in 11 is always output to the selector 117.

The reception buffer 112 is a one-byte data buffer, and stores received data and its own address 2. Reading and writing are performed on the reception buffer 112 by the host I / F 113, and writing is performed by the data transfer control circuit 107. The data in the reception buffer 112 is always output to the selector 117.

The self address 2 transfer circuit 115 transfers the data in the reception buffer 112 to the transmission buffer 111 when the reception buffer write signal 107b or the reception buffer write signal 113b is input, and uses the selector switching signal 115a to select the selector 117. Send buffer 11
Switch to 1. When the transmission buffer write signal 113a is input, the self address 2 transfer circuit 115 transfers the data in the transmission buffer 111 to the reception buffer 112, and uses the selector switching signal 115a to select the selector 1
17 is switched to the reception buffer 112. When the initialization signal 107c is input during the reception operation, the self address 2
The transfer circuit 115 transfers the data in the transmission buffer 111 to the reception buffer 112, and the selector switching signal 115
The selector 117 is switched to the transmission buffer 111 using a. If the initialization signal 107c is input during the transmission operation, the self address 2 transfer circuit 115 transfers the data in the reception buffer 112 to the transmission buffer 111, and switches the selector 117 using the selector switching signal 115a. Switch to.

The host I / F 113 includes a transmission buffer 111
And reading and writing of the receiving buffer 112.
Also, when writing to the transmission buffer 111, the transmission buffer writing signal 113a is output, and when writing to the reception buffer 112, the reception buffer writing signal 113b is output.

The CPU 114 is a central processing unit for controlling the I2C communication device 100. The self address 1 register 110 is a 7-bit address register and stores the self address 1. The address value is set by the CPU 114. 7-bit address data is stored in the selector 1
16 is always output.

The address determination control circuit 109 controls the transmission / reception switching signal 109d and the selector switching signal 109c and sends the acknowledge transmission signal 109 in accordance with the data comparison result between the shift register 108 and the selector 116.
a and the address coincidence signal 109b are output.

Hereinafter, the operation of the address determination control circuit 109 will be described with reference to FIG. In the initial state, the address determination control circuit 109 does not operate the data transfer control circuit 105 and sets the selector 116 to its own address 1 register 1
It has been switched to the 10 side.

The data format (2a) for the address 1 determination is composed of a start condition (S), an address 1 (7 bits), a transfer direction bit "0" value, and an acknowledge bit in this order. When the start condition (S) is detected and the start detection signal 104a is input, the circuit determines the address 1. After receiving the address 1 and the transfer direction bit, the LS of the value of the self address 1 register 110
The 8-bit value obtained by adding the value “0” to the B side is compared with the 8-bit value obtained by adding the transfer direction bit to the address 1 in the shift register. Selector 116 to selector 117
Switch to the side. If the addresses 1 do not match, this circuit performs the same operation as in the initial state.

The data format (2b) in the determination of the address 2 is composed of the address 2 (8 bits) and the acknowledge bit in this order. After the address 1 matches, the address 2 is determined. This circuit compares the 8-bit value of the selector 117 with the 8-bit address 2 in the shift register after receiving 1-byte address data, and outputs an acknowledgment transmission signal 109a to make the selector 116 self Switch to the address 1 register 110 side. If the addresses 2 do not match, this circuit performs the same operation as in the initial state.

Data format for slave transmission (2
f) includes a restart condition (Sr), an address 1 (7 bits), a transfer direction bit “1” value, and an acknowledge bit.

Immediately after the address 2 matches (2b), the restart condition (Sr) is detected and the start detection signal 104
When "a" is input, the circuit performs the third address determination (2f) for performing the transmission operation. This circuit combines the value of the self address 1 register 110, the 8-bit value obtained by adding "1" to the LSB, the address 1 in the shift register, and the transfer direction bit after receiving the address 1 and the transfer direction bit. The value is compared with the bit value, and if they match, an acknowledgment transmission signal 109a is output. Also,
The data transfer control circuit 107 is switched to the transmission mode, and outputs the address match signal 109b. Selector 1
Switching of 16 leaves the self address 1 register 110 selected. Thereafter, the I2C communication device 100 performs a transmission operation. If the address comparison here does not match,
This circuit performs the same operation as the initial state.

When the received byte data (2c) is received after the address 2 matches (2b), the circuit switches the data transfer control circuit 107 to the reception mode. Thereafter, the I2C communication device 100 performs a receiving operation.

During the transmission / reception operation of the I2C communication apparatus 100, the restart condition (Sr) and the stop condition (P) (2
When e, 2i) is received, the circuit performs the above-described operation in the initial state.

Further, referring to FIG.
The operation flow of 0 will be described. Before starting communication, the self address 1 is set in the self address 1 register 110, and the self address 2 is set in the transmission buffer 111 and the reception buffer 112.
(S300). In the initial state, the selector 116 selects the self address 1 register 110 side, and the selector 117
Is selected.

The detection is continued until the start condition (S) appears on the I2C bus (S301). When the start condition (S) is detected, the address 1 is judged next. Next, the data of the address 1 is received, the data is compared with the self address 1 register, and the transfer direction is determined (S30).
2). If they match, an acknowledge is sent and selector 1
16 is switched to the selector 117 side, and then the address 2 is determined (S303). If they do not match, the process returns to the standby state for start condition detection (S301).

Next, the data at the address 2 is received and compared with the output of the selector 117 (S304). If they match, an acknowledgment is sent out, the selector 116 is switched to the self address 1 register 110 side, and then it is determined whether or not a restart condition exists (S306). The process returns to the standby state for detecting the start condition that does not match (S301) (S305).

Next, it is determined whether or not the restart condition (Sr) exists, and a transmission operation or a reception operation is selected (S307). If the restart condition (Sr) is detected, an address determination for entering the transmission mode is performed (S308), and if not detected, a reception operation (S311) is performed.

Hereinafter, the flow of the transmission operation will be described. First, the data of the address 1 is received, the data is compared with the self address 1 register, and the transfer direction is determined (S30).
8). If they match, the I2C communication device 100 enters the transmission mode, sends an acknowledge, and generates an interrupt (S3).
09). If they do not match, it is assumed that it is a protocol violation of the I2C bus, and a communication error process is performed. As for the control of the communication error, control is performed such as generating an interrupt and stopping the operation.

When the CPU 114 writes transmission data to the transmission buffer 111, the transmission buffer 1
The data at the address 2 in 11 is transferred to the reception buffer 112, and the selector 117 switches to the reception buffer 112 side (S310). Thereafter, the transmission data is set in the transmission buffer 111 (S317).

Next, the transmission data in the transmission buffer 111 is transferred to the shift register 108 and serial transmission is performed. When the serial transmission of the byte data is completed, the next transmission data set request interrupt is generated (S31).
8). Thereafter, data transmission is continued while an acknowledgment for each byte transmission is detected, and if not detected, the transmission operation ends (S319).

When the transmission operation is completed, the reception buffer 112
Is transferred to the transmission buffer 111, and the selector 117 switches to the transmission buffer 111 side (S320).

Finally, when the start condition is detected (S321), the address 1 is determined (S302), and when the stop condition is detected (S322), the communication is terminated (S323). Next, the flow of the receiving operation will be described.

After the serial reception of bytes, the received data in the shift register 108 is transferred to the reception buffer 112, and an interrupt is generated after sending an acknowledge (S311).
The CPU 114 reads out the reception data in the reception buffer 112 (S312).

Thereafter, when the restart condition (Sr) or the stop condition (P) is not detected, the data reception is continued (S313, S314). When the restart condition is detected (S313), the data at address 2 in the transmission buffer 111 is transferred to the reception buffer 112, the selector 117 is switched to the transmission buffer 111 side (S324), and the address 1 is determined (S302). Processing shifts.

When the stop condition is detected (S314), the data at address 2 in the transmission buffer 111 is transferred to the reception buffer 112, the selector 117 is switched to the transmission buffer 111 side (S315), and the communication is terminated (S316). ).

According to the above configuration, the self address 2 is held in the transmission buffer or the reception buffer, so that the address held in the buffer can be directly compared with the register of the shift register in the second address comparison. There is no need to perform the processing used, and C
Interrupts to the PU can be reduced.

Embodiment 2 Hereinafter, an I2C communication apparatus according to Embodiment 2 will be described with reference to FIGS.

Although the transmission buffer and the reception buffer are separately mounted in the I2C communication device according to the first embodiment, the transmission buffer and the reception buffer are shared by the I2C communication device according to the second embodiment of the present invention. It is characterized by being implemented.

Here, I2C operating in slave transmission / reception in 10-bit address mode without performing the master operation
The communication device will be described. FIG. 4 is a block diagram of an I2C communication device according to Embodiment 2 of the present invention. FIG. 5 is a communication data and interrupt generation timing diagram in the I2C communication device according to the second embodiment of the present invention, and FIG. 6 is an operation flow diagram of the I2C communication device in the second embodiment of the present invention.

The configuration of the I2C communication device 400 and the function of each circuit will be described below. However, description of the same parts as in the first embodiment will be omitted. The data transfer control circuit 107 controls switching between a transmission operation and a reception operation or a non-operation state by a transmission / reception switching signal 109d. When the transmission / reception switching signal 109d is a transmission selection signal, the data transfer control circuit 107 enters the transmission mode, reads out byte data for transmission from the transmission / reception buffer 411, and then transfers it to the shift register 108 to start serial transmission. When the transmission / reception switching signal 109d is a reception selection signal, the data transfer control circuit 107 enters the reception mode, reads out the byte data received from the shift register 108, transfers the data to the transmission / reception buffer 411, and outputs the buffer access request signal 107a. When the transmission / reception switching signal 109d is neither the transmission selection signal nor the reception selection signal, the circuit does not access the transmission / reception buffer 411 and the buffer access request signal 107a
Also does not output Further, the circuit includes a communication end signal 104
When b is output, the transmission / reception operation ends.

The transmission / reception buffer 411 is a 1-byte data buffer, and stores transmission data, received data, and its own address 2. The transmission / reception buffer 411 is read and written by the host I / F 113 and the data transfer control circuit 107. The transmission / reception buffer 41
The data in 1 is always output to the selector 116. Also,
When writing is performed by the data transfer control circuit 107 and the host I / F 113, a transmission / reception buffer write signal 411a is output.

The host I / F 113 has a transmission / reception buffer 41
1 is read and written. When the CPU 114 accesses the transmission / reception buffer 411, the address 1 for accessing when setting the address 1 or the self address 2 for accessing as the transmission / reception buffer is input. The host I / F 113 accesses the transmission / reception buffer 411 both at the time of transmission and at the time of reception, but the address 1 or the address 2 is output to the address recorder 418.

Address decoder 418 is used to set transmission data and read reception data.
When the U 114 accesses the transmission / reception buffer 411, the address 1 is input from the host I / F 113. When the CPU 114 accesses the transmission / reception buffer 411 to set the self address 2, the address 2 is input from the host I / F 113. Address decoder 418
Outputs "0" when an address 1 is input, and outputs "1" when an address 2 is input.

The self address 2 set flag 419 is a circuit for storing whether or not the self address 2 is set in the transmission / reception buffer 411. The transmission / reception buffer write signal 411a is output and the address decoder 41
When the output of 8 is "1", the self address 2 set flag 419 is set. The transmission / reception buffer write signal 411a is output and the address decoder 4
When the output of No. 18 is "0", the self address 2 set flag 419 is cleared. The flag value of the self address 2 set flag 419 is output as a self address 2 flag signal 419a.

The difference between the address determination control circuit 109 and the first embodiment is that the operation at the time of determining the address 1 differs depending on the value of the self address 2 flag 419. The operation at the time of determining the address 1 will be described with reference to FIG.

When the determination (5a) of address 1 is performed,
If the self address 2 flag 419 is set, the address match signal 109b is not output, and if the self address 2 flag 419 is cleared, the address match signal 109b is not output.
b is output to generate an interrupt.

Further, referring to FIG. 6, the I2C communication device 40
The operation flow of 0 will be described. Before starting communication, the self address 1 is set in the self address 1 register 110 and the self address 2 is set in the transmission / reception buffer 411 (S600), and at the same time, the self address 2 set flag 419 is set (S601). In the initial state, the selector 116 selects the self address 1 register 110 side.

The detection is continued until the start condition appears on the I2C bus. If the start condition is detected, the address 1 is determined next (S602). First, the data at address 1 is received, the data is compared with the self address 1 register, and the transfer direction is determined (S603). If they match, an acknowledgment is transmitted, and the selector 116 is switched to the transmission / reception buffer 411 (S604).
The set flag 419 is determined (S605). If they do not match, the process returns to the standby state for start condition detection (S602) (S609).

Next, the self address 2 set flag 419
Is set, no interrupt is generated. If the self address 2 set flag 419 is cleared, the self address 2 is set by software (S606).

Next, the data at the address 2 is received and compared with the output of the transmission / reception buffer 411 (S60).
7). If they do not match, the selector 116 is switched to the self address 1 register 110 side to detect the start condition (S
The process returns to the standby state of 602) (S609). If they match, an acknowledgment is sent out, the selector 116 is switched to the self address 1 register 110 side (S608), and the presence or absence of a restart condition is determined, and a transmission operation or a reception operation is selected (S610). If a restart condition is detected, an address determination for entering the transmission mode (S611) is performed. If no restart condition is detected, a reception operation (S6) is performed.
Perform 14).

Hereinafter, the flow of the transmission operation will be described. First, the data of the address 1 is received, the data is compared with the self address 1 register, and the transfer direction is determined (S61).
1) If they match, the I2C communication device 400 enters the transmission mode, sends an acknowledgment, and generates an interrupt (S6).
12). If they do not match, it is assumed that it is a protocol violation of the I2C bus, and a communication error process is performed. As for the control of the communication error, control is performed such as generating an interrupt and stopping the operation.

When the CPU 114 writes transmission data to the transmission / reception buffer 411, the self address 2 set flag 419 is cleared (S613), and the transmission data is set in the transmission / reception buffer 411 (S62).
0).

Next, the transmission data in the transmission / reception buffer 411 is transferred to the shift register 108 and serial transmission is performed. When the serial transmission of the byte data is completed, the next transmission data set request interrupt is generated (S62).
1). Thereafter, data transmission is continued while an acknowledgment is detected for each byte transmission (S622). When the start condition (S) is detected (S623), the address 1 is determined (S603), and the stop condition (P) is detected. Then (S
624) The communication is terminated (S625).

Next, the flow of the receiving operation will be described. After serial reception of bytes, the received data in the shift register 108 is transferred to the transmission / reception buffer 411, the self-address two-set flag 419 is cleared (S614), and an interrupt is generated after an acknowledgment is sent (S615).
By 114, the received data in the transmission / reception buffer 411 is read (S616).

Thereafter, when the restart condition (Sr) or the stop condition (P) is not detected, the data reception is continued (S617, S618). When the restart condition (Sr) is detected, the address 1 is determined (SS60).
The process proceeds to 3) (S617), and if a stop condition is detected, communication is terminated (S619) (S618).

As described above, according to the second embodiment of the present invention, when comparing a 10-bit address with an I2C communication device sharing a transmission buffer and a reception buffer as a transmission / reception buffer, a second address comparison is performed. In this case, since the address held in the buffer and the register of the shift register can be directly compared, it is not necessary to perform processing using a program, and it is possible to reduce interrupts to the CPU.

(Embodiment 3) An I2C communication apparatus according to Embodiment 3 will be described below with reference to FIG. In the I2C communication device according to the second embodiment, the self-address two-set flag is controlled using an address decoder. However, in the I2C communication device according to the third embodiment of the present invention, an output from an address determination control circuit is used without using an address decoder. The self-address two-set flag is controlled using the transmission / reception switching signal.

Here, I2C operating in slave transmission and reception in a 10-bit address mode without performing a master operation is described.
The communication device will be described. FIG. 7 is a block diagram of an I2C communication device according to Embodiment 3 of the present invention.

The configuration of the I2C communication device 700 and the function of each circuit will be described below. However, description of the same parts as in the second embodiment will be omitted. The self address 2 set flag 719 is a circuit for storing whether the self address 2 is set in the transmission / reception buffer 411.
A flag is set when the transmission / reception buffer write signal 411a is output and the transmission / reception switching signal 109d is not a transmission selection. Transmit / receive buffer write signal 411
a is output, and the flag of this circuit is cleared when the transmission / reception switching signal 109d is a transmission / reception selection. The flag value of this circuit is output as the self address 2 flag signal 419a. The operation flow of the I2C communication device 700 is the same as that of the second embodiment, and a description thereof will be omitted.

According to the configuration described above, in the second embodiment, separate access addresses are required for accessing the transmission / reception buffer and for setting the self address 2 flag. However, according to the third embodiment of the present invention, one type of access address is required. The address of the transmission / reception buffer and the setting of the self address 2 flag can be performed by the address. That is, compared to the second embodiment, the third embodiment of the present invention requires less address space by one register address, and can reduce interrupts to the CPU with a more efficient configuration.

[0083]

As described above, according to the I2C communication apparatus in the serial communication apparatus of the present invention, two buffers for storing the second addresses for transmission and reception, and one of the addresses of the two buffers and the self address 2 By having a selector for selecting one of the two and a circuit for comparing the address data, in the second address comparison, the address held in the buffer and the register of the shift register can be directly compared. It is not necessary to perform the processing, and the interruption to the CPU can be reduced.
The burden on U can be reduced.

Further, the transmission buffer and the reception buffer are set to 1
Even if the transmission and reception buffers are shared, the address held in the buffer and the register of the shift register can be directly compared in the second address comparison, so that there is no need to perform processing using a program,
Interrupts to the CPU can be reduced, and the processing performed by the CPU during communication can be reduced, thereby reducing the load on the CPU.

Further, by setting the self address 2 set flag, it is possible to access the transmission / reception buffer and set the self address 2 flag with one kind of access address, thereby suppressing the consumed address space.
It is possible to reduce interrupts to the CPU with a more efficient configuration, and reduce the number of CPU processes performed during communication to reduce the CPU
Can be lightened.

[Brief description of the drawings]

FIG. 1 is a block diagram of an I2C communication device according to a first embodiment of the present invention.

FIG. 2 is a communication data and interrupt generation timing diagram in the I2C communication device according to the first embodiment of the present invention.

FIG. 3 is an operation flowchart of the I2C communication device according to the first embodiment of the present invention.

FIG. 4 is a block diagram of an I2C communication device according to a second embodiment of the present invention.

FIG. 5 is a communication data and interrupt generation timing diagram in the I2C communication device according to the second embodiment of the present invention.

FIG. 6 is an operation flowchart of the I2C communication device according to the second embodiment of the present invention.

FIG. 7 is a block diagram of an I2C communication device according to a third embodiment of the present invention.

FIG. 8 is a block diagram of a conventional I2C communication device.

FIG. 9 is a communication data and interrupt generation timing diagram in a conventional I2C communication device.

[Explanation of symbols]

100 I2C communication device 101 I2C bus SCL 102 I2C bus SDA 103 Clock control circuit 104 Bus state detection circuit 104a Start detection signal 104b Communication end signal 105 Data control circuit 106 Interrupt generation circuit 106a signal 106b Interrupt signal 107 Data transfer control circuit 107a Buffer access request signal 107b Receive buffer write signal 107c Initialization signal 108 shift register 109 Address judgment control circuit 109a Address determination control circuit 109b Address match signal 109c Selector switching signal 109d transmission / reception switching signal 110 Self address 1 register 111 transmission buffer 112 receive buffer 113 Host I / F 113a Transmission buffer write signal 113b Receive buffer write signal 114 CPU 115 Self-address 2 transfer circuit 115a Selector switching signal 116 Selector 117 Selector 400 I2C communication device 411 send / receive buffer 411a Transmit / receive buffer write signal 418 Address decoder 419 Self address 2 set flag 419a Self address 2 set flag signal 700 I2C communication device 719 Self address 2 set flag 800 I2C communication device 801 I2C bus SCL 802 I2C bus SDA 803 Clock control circuit 804 bus state detection circuit 805 Data control circuit 806 interrupt generation circuit 807 Data transfer control circuit 808 shift register 809 Address determination control circuit 810 Self address 1 register 811 Transmission buffer 812 Receive buffer 813 Host I / F 814 CPU

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Kenichi Kawaguchi             Matsushita Electric, 1006 Kadoma, Kazuma, Osaka             Sangyo Co., Ltd. (72) Inventor Miki Urano             Matsushita Electric, 1006 Kadoma, Kazuma, Osaka             Sangyo Co., Ltd. F-term (reference) 5B014 HB02                 5B077 BA02 DD07 NN02

Claims (6)

[Claims] 1. A serial communication device for serially transmitting communication data and transmitting / receiving the communication data to / from an external device, comprising: a shift register for shifting the communication data; and receiving data of the communication data sequentially communicated to the shift register. A data control circuit for transferring; a first data buffer for holding the received data shifted by the shift register; and a second received data to the data control circuit after the shift register shifts the first received data. A data transfer control circuit for transferring the first received data to the first data buffer when input, and transferring the second received data to the shift register; and holding arbitrarily configurable comparison data. A register, either of the first received data or the comparison data held in the first data buffer; A first selector circuit for selecting either the serial communication device; and a data comparison circuit for comparing said first selector circuit selects the data second received data. 2. A serial communication device, which is an I2C communication device that performs communication via an I2C bus, comprising: a shift register that shifts the communication data; and a shift register that receives received data among the communication data sequentially communicated. A first data buffer for holding an address of the received data shifted by the shift register; and a second received data after the shift register shifts the first received data. A data transfer control circuit for transferring an address of the first received data to the first data buffer and transferring the second received data to the shift register when input to the control circuit; A register for holding an address for use, and an address of first received data held in the first data buffer. Other has a selector circuit for selecting one of the addresses for the comparison, the data comparison circuit for comparing the address of said second received data and addresses the selector circuit selects,
A serial communication device, wherein data is received when the address of the second received data matches the address selected by the selector circuit. 3. A serial communication device, which is an I2C communication device that performs communication via an I2C bus, comprising: a shift register that shifts the communication data; and a shift register that receives received data among the communication data sequentially communicated. A data control circuit for receiving the transmission data from the shift register and outputting the received data; a first data buffer for holding an address of the reception data shifted by the shift register; and an address of the transmission data received from the shift register. And a second data buffer for holding the first communication data when the second communication data is input to the data control circuit after the shift register shifts the first communication data. To transfer the second communication data to the shift register. A transfer control circuit; an address data transfer circuit for controlling transfer of address data between the first data buffer and the second data buffer; a register for holding arbitrarily configurable comparison data; A selector circuit for selecting any one of an address of communication data held in a data buffer, an address of communication data held in the second data buffer, and an address for comparison held in the register; A data comparison circuit that compares the address selected by the selector circuit with the address of the second communication data,
A serial communication device for transmitting and receiving data when the address of the second communication data matches the address selected by the selector circuit. 4. A serial communication device, which is an I2C communication device that performs communication via an I2C bus, comprising: a shift register for shifting the communication data; and a shift register for receiving data among the communication data sequentially communicated. A data control circuit for receiving the transmission data from the shift register and outputting the transmission data; a data buffer for holding the address of the communication data shifted by the shift register; and a shift register for shifting the first communication data. A data transfer control circuit that transfers an address of the first communication data to the data buffer when the second communication data is input to the data control circuit later, and transfers the second communication data to the shift register; When the address of the second communication data is held in the data buffer, An address holding flag setting circuit for setting a register, a register for holding arbitrarily set comparison data, and selecting one of an address held in the data buffer or a comparison address held in the register And a data comparison circuit that compares the address selected by the selector circuit with the address of the second communication data,
When the flag is not set, transmission / reception is performed by matching the comparison address with the address of the first communication data, and when the flag is set, the second communication is performed.
A serial communication device for transmitting and receiving data by matching the address of the communication data with the address selected by the selector circuit. 5. A serial communication device, which is an I2C communication device that performs communication via an I2C bus, comprising: a shift register that shifts the communication data; and a shift register that receives received data among the communication data sequentially communicated. A data control circuit for receiving the transmission data from the shift register and outputting the received data, a first data buffer for holding an address of the reception data shifted by the shift register, and an address of the transmission data received from the shift register. And a second data buffer for holding the first communication data when the second communication data is input to the data control circuit after the shift register shifts the first communication data. To transfer the second communication data to the shift register. A transfer control circuit; an address data transfer circuit for controlling transfer of address data between the first data buffer and the second data buffer; and an external arithmetic unit communicating with the first data buffer to store the second data in the first data buffer. An address holding flag setting circuit for setting a flag when an address of communication data is held; a register for holding arbitrarily set comparison data; an address of communication data held in the first data buffer; A selector circuit for selecting any one of an address of communication data held in the second data buffer or a comparison address held in the register; and an address selected by the selector circuit and the second address. A data comparison circuit for comparing addresses of communication data of
A serial communication device for transmitting and receiving data when the address of the second communication data matches the address selected by the selector circuit. 6. A serial communication device, which is an I2C communication device that performs communication via an I2C bus, comprising: a shift register that shifts the communication data; and a shift register that receives received data among the communication data sequentially communicated. A data control circuit for receiving the transmission data from the shift register and outputting the received data, a first data buffer for holding an address of the reception data shifted by the shift register, and an address of the transmission data received from the shift register. And a second data buffer for holding the first communication data when the second communication data is input to the data control circuit after the shift register shifts the first communication data. To transfer the second communication data to the shift register. A transfer control circuit; an address data transfer circuit for controlling the transfer of address data between the first data buffer and the second data buffer; and an operation for determining whether the device is in a serial transmission operation state or a serial reception operation state. When the discrimination circuit communicates with the external arithmetic device, the operation discrimination circuit discriminates that the operation is in the serial reception operation state, and the address of the second communication data is held in the first data buffer. An address holding flag setting circuit for setting a flag when there is a register; a register for holding arbitrarily settable comparison data; an address of communication data held in the first data buffer or holding in the second data buffer One of the address of the transmitted communication data or the address for comparison held in the register. The has a selector circuit for selecting, and a data comparator circuit for comparing said selector circuit address of the selected address to the second communication data,
A serial communication device for transmitting and receiving data when the address of the second communication data matches the address selected by the selector circuit.