JPH06164595A - Serial bus controller - Google Patents

Abstract

PURPOSE:To reduce data quantity on a serial bus and control period of time for a slave circuit group, and further, to lower occupancy rate on the serial bus so that the burden on a bus master circuit can be lightened by imparting command data at the some time for plural slave circuits to which the same address is assigned. CONSTITUTION:At two slave circuits 121, 122 to which the same address 1 is assigned in a serial bus controller, the data of the same address 1 is discriminated, and the command data to make a pair with it is fetched, and the data is decoded by data decoder sequencers 141, 142, and is outputted as a bit data string on a time base. After that, processing logic circuits 131, 132 are controlled on the basis of the data string so as to execute necessary control. Here, the processing of the circuits 131, 132 corresponding to the circuits 121, 122 is different from each other but operation aimed by the command data can be realized. Besides, at the circuit 123 to which the address 2 of the other side is assigned, the command data to make a pair with it is fetched, and a logic circuit 133 is controlled by the output of the sequencer 143.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial bus control device for controlling a controlled circuit group through a serial bus built in, for example, an audio / video (AV) device, and more particularly to a plurality of serial bus coupled devices. To commonly control the slaves.

[0002]

2. Description of the Related Art In recent television receivers,
For example, there is a serial bus control device for controlling the tuning and displaying the tuning number on the screen. Figure 4
1 illustrates a conventional serial bus controller used in a television receiver.

In the serial bus 10 for the data transfer line, for example, one bus master circuit 41 (usually a microcomputer is used) and a plurality of slave circuits 421, 42 to which addresses different from each other are assigned.
2, 423 are connected, and processing logic circuits 431, 432, 433 are connected to the plurality of slave circuits 421, 422, 423, respectively.

Here, the slave circuit 421 of address 1
And the processing logic circuit 431 uses P for channel selection.
The slave circuit 422 of the address 2 is provided in the integrated circuit for controlling the LL (phase locked loop) (tuning control).
The processing logic circuit 432 is provided in the integrated circuit for screen display control. Next, the channel selection control operation by the serial bus control device will be described.

The bus master circuit 41 transmits the data of the address 1 and the tuning control bit data corresponding to the channel number designated from the outside to the serial bus 10 as a pair, and further transmits the data of the address 2 and the channel number. The corresponding screen display control bit data is transmitted to the serial bus 10 as a pair.

The slave circuit 421 of the address 1 discriminates the data of the address 1 addressed to itself from the serial bus 10 and sends the tuning control bit data paired with the data directly to the processing logic circuit 431. This processing logic circuit 4
A processing unit 31 processes the PLL for channel selection so as to perform tuning control corresponding to the designated channel number.

The slave circuit 422 of the address 2 discriminates the data of the address 2 addressed to itself from the serial bus 10 and sends the screen display control bit data paired with the data directly to the processing logic circuit 432. The processing logic circuit 432 controls to display the designated channel number on the screen of the television receiver.

As described above, in the conventional serial bus control device, when performing one job, the bus master circuit 41 first decomposes the data into slave circuit-specific data, and the slave circuits are assigned different addresses. 42
By individually transmitting the individual address data and the individual bit data to 1, 422, 423, the slave circuits 421, 422, 423 are individually controlled. Then, in each slave circuit 421, 422, 423, each corresponding data is decoded, and in each corresponding processing logic circuit 431, 432, 433, different processing for each slave circuit is performed.

However, in such a conventional serial bus control device, since the address data and bit data corresponding to the number of slave circuits are transmitted on the serial bus 10,
When the number of slave circuits increases, the control time for the slave circuit group increases and the serial bus 10
The occupancy rate becomes higher, and the load on the bus master circuit 41 becomes heavier.

[0010]

As described above, in the conventional serial bus control device, the control time for the slave circuit group increases, the occupation rate on the serial bus increases, and the load on the bus master circuit becomes heavy. was there.

The present invention has been made to solve the above problems, and it is possible to reduce the control time for the slave circuit group, reduce the occupation rate on the serial bus, and reduce the load on the bus master circuit. An object is to provide a serial bus control device.

[0012]

The serial bus control device of the present invention serializes a data transfer line serial bus and data including the same address data and operation control command data coupled to the serial bus. A bus master circuit having a function of transmitting to the bus and a bus interface function which are respectively coupled to the serial bus, determine data of an address addressed to itself on the serial bus, and take in a pair of data are provided. A slave circuit group including a plurality of slave circuits to which addresses are assigned, and a plurality of slave circuits provided corresponding to the plurality of slave circuits and decoding the command data fetched by the corresponding slave circuits to output a control signal. A data decoder and a plurality of data decoders are provided corresponding to the data decoder. Characterized by comprising a plurality of processing logic circuit that performs different processing from each other on the basis of a control signal output of the data decoder.

[0013]

Since command data is simultaneously given to a plurality of slave circuits to which the same address is assigned, the amount of data on the serial bus decreases, the control time for the slave circuit group decreases, and the serial bus on the serial bus decreases. The occupancy rate becomes low, and the load on the bus master circuit becomes light.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a serial bus control device according to a first embodiment of the present invention.

The serial bus control device is connected to the serial bus 10 for a data transfer line, and is connected to the serial bus 10 and has, for example, 3 addresses to which addresses are assigned.
Each slave circuit 121, 122, 123 and a bus master circuit 11 connected to the serial bus 10 are provided.

In the present embodiment, among the slave circuit groups, a plurality of specific slave circuits (two slave circuits 121 and 122 in this example) related to processing are grouped into one group and are the same. An address (for example, address 1) is assigned. The number of this group can be set arbitrarily. For the remaining slave circuits (in this example, one slave circuit 123) unrelated to the processing of the two slave circuits, the address 2 independent of the address 1 is used.
Has been assigned.

The bus master circuit 11 is, for example, a microcomputer, and is used to control address data for designating an arbitrary slave circuit and operation of the slave circuit designated by the address data. It has a function of transmitting command data to the serial bus 10. In this case, the same address data and command data are transmitted to the plurality of slave circuits 121 and 122 to which the same address is assigned.

The slave circuits 121, 122, 123
Has a bus interface function of discriminating data of an address addressed to itself on the serial bus 10 and fetching command data paired with the address data, and correspondingly, via data decoders / sequencers 141, 142, 143. Processing logic circuits 131, 132, 133 are connected.

The data decoder / sequencer 141,
142 and 143 are slave circuits 121 and 1 respectively corresponding
22 and 123 has a function of decoding the command data taken in and converting it into a control signal necessary for controlling the operation to be performed in the processing system to which the command data belongs.

Specifically, the decoder function for decoding command data and outputting a control signal (bit data) and the control signal when it is necessary to perform processing in consideration of time (order on the time axis, etc.) It has a sequencer function of outputting (bit data) at a required timing (in other words, converting the bit data as a bit data string on the time axis).

Each processing logic 131, 132, 133
Is the corresponding data decoder / sequencer 141, 1
Required processing is performed based on the bit data output from 42 and 143 or the bit data string on the time axis. In addition,
The above-mentioned slave circuit, data decoder / sequencer, and processing logic circuit are provided, for example, in the same integrated circuit for each pair.

In the serial bus control device of the above embodiment, the two slave circuits 121 and 122 to which the same address 1 is assigned discriminates the data of the same address 1 and fetches the command data paired with this. , This command data is sent to the data decoder / sequencer 14
The data is decoded by 1 and 142 and output as a bit data string on the time axis, and the processing logic circuits 131 and 132 are controlled based on this bit data string to perform required processing.

In this case, the above two slave circuits 12
Two processing logic circuits 131 corresponding to 1, 122;
Although the processing of 132 is different from each other, the intended operation of the command data is realized by the processing of these two processing logic circuits 121 and 122.

On the other hand, the slave circuit 123 to which the address 2 is assigned discriminates the data of the address 2 and fetches the command data paired with the data. Then, this command data is decoded by the data decoder / sequencer 143 and output as a bit data string on the time axis,
Based on this bit data string, the processing logic circuit 133
Control and perform the required processing.

As described above, the serial bus control device of this embodiment is different from the conventional serial bus control device in the meaning of the address data and control data transmitted from the bus master circuit 11 to the serial bus 10 to the slave circuit. ing.

That is, in the conventional serial bus control device,
The address data is unique to the slave circuit, the control data is bit data, and the meaning of the control data is different for each slave circuit.

On the other hand, in the serial bus control device of the present embodiment, a plurality of specific slave circuits related to the process are grouped as one group in the slave circuit group and the same address is assigned. Also, control data for a plurality of slave circuits having the same address is treated as command data, and a plurality of slave circuits are made to perform a common work. In this case, the plurality of slave circuits have different actual processing operations even if they have the same address.

Therefore, according to the serial bus control device of the above embodiment, command data is simultaneously given to a plurality of specific slave circuits related to processing, and to the remaining slave circuits not related to processing. Are individually provided with address data and command data. As a result, the amount of data on the serial bus decreases, the control time for the slave circuit group decreases, the occupation rate on the serial bus decreases, and the load on the bus master circuit decreases.

Next, as an example of a specific operation of the serial bus control device of the above embodiment, a case where the serial bus control device is used in a television receiver and channel selection control is performed will be described.

In this case, the slave circuit 121 and the processing logic circuit 131 are provided in an integrated circuit for controlling a PLL (phase locked loop) for channel selection (channel selection control), and the slave circuit 122 and the processing logic circuit 132. Are provided in the integrated circuit for screen display control.

The bus master circuit 11 transmits command data corresponding to a channel number designated from the outside to the serial bus 10 after the data of the address 1. In this case, for example, "01" of the command data is channel number 1
Is defined as "10" of the command data, "10" of the command data is selected as the channel number 2, and so on, and the command data "01" is transmitted.

The slave circuit 121 of the address 1 discriminates the data of the address 1 addressed to itself from the serial bus 10 and sends the command data ("01") paired with the data to the corresponding data decoder / sequencer 141. The data decoder / sequencer 141 converts the command data (“01”) into a bit data string and sends it to the processing logic circuit 131 for channel selection control. As a result, the processing logic circuit 132 processes the PLL for channel selection so as to perform the tuning control corresponding to the specified channel number 1.

The slave circuit 122 having the same address 1 as the slave circuit 121 discriminates the data of the address 1 addressed to itself from the serial bus 10 and outputs the command data ("01") which forms a pair with the data. Send to the decoder / sequencer 142. The data decoder / sequencer 142 converts the command data (“01”) into a bit data string and sends it to the processing logic circuit 132 for screen display control. As a result, the processing logic circuit 1
The control unit 32 controls to display the designated channel number 1 on the screen of the television receiver for a fixed time.

That is, by transmitting one command data, the channel selection processing and the screen display control processing can be simultaneously processed by the two processing logic circuits 131 and 132.

Next, as another example of the specific operation of the serial bus control device of the above embodiment, a video tape recorder (VTR) is used by using a remote control device (remote control device) while watching information on a television screen. ) A case of performing setting control such as timer reserved recording in) will be described.

In this case, it is considered that the bus master circuit 11 is provided in the remote controller and has a function of transmitting address data and, for example, time setting command data, time setting data and screen display position specifying data. Further, transmission using infrared rays from the remote control device is considered as transmission on the serial bus 10. Then, two slave circuits 121 having the same address,
It is considered that 122 is provided in the system microcomputer incorporated in the VTR and the screen display control integrated circuit.

The time setting command data and the time setting data transmitted from the remote control device are taken into the system microcomputer and decoded, and the time setting data is stored in the memory of the system microcomputer. At the same time, each of the data is taken into the screen display control integrated circuit, decoded, and displayed at a predetermined position on the television screen for a set time.

When such a control is performed by the conventional serial bus control device, after the system microcomputer takes in the time setting data transmitted from the remote control device, the remote control device sends it to the screen display control integrated circuit. Since it is necessary to transmit the time setting data and the screen display position specifying data for each character, there is a problem that the load on the system microcomputer becomes heavy and the amount of data on the serial bus becomes large.

On the other hand, according to the serial bus control device of the above embodiment, by transmitting one command data, it becomes possible to simultaneously perform the storage process of the time setting data and the screen display control process. Moreover, since the serial bus only requires a line for transmitting infrared rays from the remote control device, the load on the system microcomputer is extremely light.

The data decoder / sequencer 141, 142, 143 omits the sequencer function when the corresponding processing logic circuits 131, 132, 133 do not need to perform the processing in consideration of time, and the decoder is omitted. A configuration having only functions may be used.

In order to designate the slave circuit 123 to which the address 2 is assigned as the bus master circuit 11 and control its operation, address data and bit data are transmitted to the serial bus 10 as in the conventional case. When the function is provided, the slave circuit 123 to which the address 2 is assigned discriminates the data of the address 2 and sends the bit data paired with the data directly to the corresponding processing logic circuit 133. Should be changed. In this case, the data decoder / sequencer 1 is provided between the slave circuit 123 and the processing logic circuit 133.
It is not necessary to interpose 43. Further, each slave circuit does not necessarily have to correspond to an integrated circuit on a one-to-one basis, and one integrated circuit may include a plurality of slave circuits. Further, the bus master circuit 11 and the slave circuit and the serial bus 10 are not limited to electrical connection, but may be informationally coupled including optical coupling in the above example.
Further, the present invention is not limited to the above-described embodiment, but can be applied to a case where there are a plurality of bus master circuits or a case where there are a plurality of serial buses. FIG. 2 shows a serial bus control device according to the second embodiment of the present invention.

This serial bus control device is different from the serial bus control device described above with reference to FIG. 1 in that two bus master circuits 111 and 112 are connected to the serial bus 10, and the others are the same. Is. Figure 3
7 shows a serial bus control device according to a third embodiment of the present invention.

This serial bus control device uses two serial buses as compared with the serial bus control device described above with reference to FIG.
One bus master circuit 11 is commonly connected to 102, two slave circuits 121 and 122 having the same address are connected to one serial bus 101, and one bus master circuit 11 having another address is connected to the other serial bus 102. The difference is that one slave circuit 123 is connected, and the others are the same.

[0044]

As described above, according to the present invention, the control time for the slave circuit group can be reduced, the occupation rate on the serial bus can be reduced, and the load on the bus master circuit can be reduced. Can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a serial bus control device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a serial bus control device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a serial bus control device according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional serial bus control device.

[Explanation of symbols]

10, 101, 102 ... Serial bus, 11, 111,
112 ... Bus master circuit, 121, 122, 123 ... Slave circuit, 131, 132, 133 ... Processing logic circuit, 141, 142, 143 ... Data decoder.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location G06F 13/38 350 9072-5B

Claims (2)

[Claims] 1. A serial bus for a data transfer line, a bus master circuit coupled to the serial bus, having a function of transmitting data including data of the same address and command data for operation control to the serial bus, and the serial bus. Each has a bus interface function that is coupled to the bus, determines the data of the address addressed to itself on the serial bus, and takes in the paired data.
A slave circuit group including a plurality of slave circuits to which the same address is assigned, and the slave circuit group provided corresponding to the plurality of slave circuits and decoding the command data fetched by the corresponding slave circuits and outputting a control signal. A serial bus comprising a plurality of data decoders and a plurality of processing logic circuits provided corresponding to the plurality of data decoders and performing different processings based on control signal outputs of the corresponding data decoders. Control device. 2. The serial bus control device according to claim 1, wherein the serial bus control device is provided in correspondence between the plurality of data decoders and the plurality of processing logic circuits, and the control signal output of the corresponding data decoder is on the time axis. A serial bus control device further comprising a data sequencer for controlling timing.