JP2639248B2 - Communication interface device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication interface device for transmitting and receiving data, and more particularly to a communication interface device for storing a communication procedure sent from a master CPU and executing data transmission and reception in accordance with the procedure.

[0002]

2. Description of the Related Art Conventionally, an interface called a modem intervenes between a device and a communication line to send data generated by the device to the communication line or vice versa.
Such an interface is required to realize transmission conditions that match the characteristics of the communication line in order to transmit data most efficiently.

In order to configure an interface, for example, a microprocessor and a peripheral IC for communication are often used in combination. The communication peripheral IC temporarily stores the data sent from the microprocessor, and sends out a signal on an external communication line according to a procedure predetermined by the communication peripheral IC. As such a peripheral IC for communication,
For example, Intel's 8251 or Zilog's Z
80-SI0.

[0004]

In order to use a peripheral IC for communication that communicates with an external device in combination with a microprocessor, it is necessary to follow a specification predetermined for the IC. For example, it is necessary to design an interface device according to the number of communication ports, communication speed, pin assignment of ports, handshake conditions, and the like. As described above, as long as the conventional peripheral IC for communication is used, a great restriction is imposed on the design of the interface. Considering the restrictions from the above specifications, one or two sets of communication ports are usually prepared for the conventional communication peripheral IC, and it is necessary to add the communication peripheral IC for a system requiring more communication ports. Occurs. In order to switch the communication speed, it is necessary to provide a dip switch externally, or to provide a dedicated control line for setting from the microprocessor side. Regarding port pin assignment, when the communication peripheral IC uses RS232C as a communication protocol, control lines for communication, for example, RS, CS, DR,
Signals such as ER are determined in advance, and it is impossible to change the content of control, the number of control lines, or the arrangement of pins. Further, the handshake condition is also predetermined in the peripheral IC for communication and cannot be changed and used. Therefore, communication cannot be performed using the new protocol.

As described above, conventional communication peripheral ICs need to be designed in accordance with various specifications, and depending on the design contents, the result is that a communication interface must be configured while leaving unused control lines and functions. Become.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a highly versatile communication interface device that follows a communication procedure transferred from a master CPU.

[0007]

The present invention provides a master CPU.
And transmits the data to an external communication line according to a predetermined communication procedure, and receives data on the external communication line and transmits the serial data to the master CPU according to a predetermined communication procedure. In the communication interface device, a communication program storage means for storing a communication program for executing the communication procedure, and a transfer for storing a transfer program for transferring the communication program stored in the master CPU to the communication interface device. Program storage means, transfer program transfer means for transferring the transfer program from the master CPU to the transfer program storage means in response to reception of a start signal from the master CPU, and transfer program storage means for the transfer program After the transfer to And a communication program transfer means for transferring the communication program stored in the master CPU to a communication program storage means by executing the transfer program in the communication interface device. Master CP confirms that data can be sent to communication line
When U is detected, the data is transmitted to the external communication line under a condition based on transmission information included in the serial data transmitted from the master CPU, and serial data from the external communication line to the master CPU is transmitted. Is a communication interface device composed of a one-chip semiconductor integrated circuit that transmits the reception condition of data received from the external communication line to the serial data when the transmission condition is possible.

[0008]

The communication interface device is interposed between the master CPU and an external communication line, and performs data communication between them. Serial data is sent from the master CPU to the communication interface device, and the data is sent to an external communication line according to a predetermined communication procedure. The data transmitted via the external communication line is transmitted to the master CPU according to a predetermined communication procedure.
The communication interface device is a communication program storage means,
Transfer program storage means, transfer program storage means, and communication program transfer means, wherein the transfer program transfer means responds to the reception of the start signal from the master CPU;
The transfer program is transferred from the master CPU to the communication interface device. The transfer program is a program for transferring the communication program from the master CPU to the communication interface device, and is stored in the transfer program storage unit. When the transfer program is stored in the transfer program storage means, the transfer program is executed, and the communication program transfer means stores the communication program from the master CPU in the communication program storage means.

When sending data to the external communication line, the master CPU confirms that the communication interface device can send data to the external communication line,
Output serial data to the communication interface device. The communication interface device transmits the data to the external communication line according to the transmission information included in the serial data by executing the communication program. Also, the master CPU
When receiving data on an external communication line, the communication interface adds reception conditions to serial data when outputting the received data to the master CPU.

[0010]

FIG. 1 is a block diagram of a communication interface and its periphery for explaining an embodiment of the present invention. The microprocessor 1 is connected via a bus 2 including a ROM (read only memory) 3 and a RAM (random access memory) 4 to constitute a master CPU. The master CPU may be a one-chip integrated circuit, or may be configured by a plurality of integrated circuits. ROM
Reference numeral 3 denotes a read-only memory;
In addition to a program and data for operating the program, a transfer program and a communication program to be transferred to the communication interface 5 are stored.

The communication interface 5 is a device for transmitting and receiving data between the master CPU and an external communication line. Various communication lines and control lines are connected between the microprocessor 1 and the communication interface 5. The control line 6 is a control line for sending a start signal for starting the initial setting of the communication interface 5.

The serial communication lines 7 and 8 are connected via selector switches S1 and S2. When the selector switches S1 and S2 are connected to the contact 1, serial data from the microprocessor 1 communicates. Transferred to interface 5. Selector switch S1, S2
Is connected to the contact 2, the serial data from the microprocessor 1 is transmitted to another device (not shown) via the communication line 9, and the communication interface 5 also communicates with the external device via the communication lines 8 and 10. can do. The contacts of the selector switches S1 and S2 are switched by a switching signal provided via a switching control line 11.

The serial communication lines 12 and 13 transmit serial data to the microprocessor 1 and the communication interface 5.
The signal line 12 is used to transfer data from the microprocessor 1 to the communication interface 5, and the signal line 13 is used to transfer data from the microprocessor 1 to the communication interface 5. 5 is used for data transfer. The signal lines 12 and 13 may be used as bidirectional signal lines.

As is well known, transmission and reception of the serial signal lines 7, 8, 12, and 13 are provided with a transmission data register and a reception data register on the transmission side and the reception side, respectively. In order to send the data to the serial signal line, first, parallel transmission data is transferred to the transmission data register. The data in the transmission data register is sequentially output to the serial signal line from the most significant bit or the least significant bit. The serial data output in this way is taken into the receiving register on the receiving side. When all bits are taken into the reception register, the received parallel data is output to the data bus. The data format on the serial signal line may be standard NRZ including start bit and stop bit,
Also, any other data format may be used.

An external communication line 14 for exchanging data between the communication interface 5 and an external device (not shown) is provided with a serial signal line and a parallel signal line. The external signal line 15 is a unidirectional communication line through which serial data is transmitted from the communication interface 5 to an external device. The external communication lines 16 and 17 are bidirectional serial signal lines, and can transmit and receive between the communication interface 5 and the external device by one signal line. Further, the external communication lines 18 and 19 can transmit and receive parallel data, and a data bus generally used in the communication interface 5 is output to the outside via a buffer.

As described above, the serial data output from the microprocessor 1 is received by the communication interface 5 via the serial signal line 12, and the transmission conditions (the transmission baud rate, the transmission baud rate, and the like) based on the transmission information included in the serial data. Output to an external device in accordance with the external communication line to be output). Conversely, data transmitted from the external device is received by the communication interface 5,
The signal is sent to the microprocessor 1 via the serial signal line 13.

FIG. 2 is a block diagram for explaining the operation of the communication interface 5 in more detail. The operation of the communication interface 5 is controlled by the control unit 50. The control unit 50 is constituted by a microprocessor, and its operation is controlled by a communication program and a transfer program stored in a communication program memory 51 and a transfer program memory 52. Control unit 5
0, the communication program memory 51 and the transfer program memory 52 transfer data via the internal bus 53.

The serial signal line 8 is connected to a reception register 54, and serial data sent from the microprocessor 1 is stored in the reception register 54. The data received by the reception register is converted into parallel data and output to the internal bus 53. The transmission / reception register 55 stores serial data transmitted from the microprocessor 1 through the serial signal line 12, converts the data into parallel, and outputs the parallel data to the internal bus. The data transferred from the internal bus 53 to the transmission / reception register 55 is sent to the microprocessor 1 via the serial communication line 13 after being converted into serial data.

The internal bus 5 and the external communication line 14 are connected to the port 5
6 to 60, and data from or to the master CPU is transmitted through these ports.

The mode control section 61 performs an operation for performing an initial setting of the communication interface 5. The control line 6 is connected to the mode control unit 61,
The output of the control unit 61 is connected to a bootstrap program memory 62. The bootstrap program memory 62 is a ROM (read only memory)
And stores a bootstrap program. When receiving the start signal on the control line 6, the mode control unit 56 outputs a bootstrap signal to the bootstrap program memory 62, and the bootstrap is started. The bootstrap program causes the transfer program stored in the master CPU to be transferred to the transfer program storage memory 52 composed of a RAM (random access memory) via the serial signal line 8. When the transfer program is stored in the transfer program storage memory 52, the bootstrap operation is completed.

When the bootstrap operation is completed, the transfer program starts executing. By executing the transfer program, the communication program stored in the ROM 2 of the master CPU is transferred to the communication program storage memory 51 via the serial signal line 8 like the transfer program. A plurality of communication programs may be prepared so that selection is possible according to communication conditions. When the communication program is stored in the communication program storage memory 51, the communication program starts executing, and communication between the master CPU and the external device becomes possible. When the communication program is stored in the communication program storage memory 51, the transfer program stored in the transfer program storage memory 52 may disappear.

The operation of transferring the above-described communication program to the communication program storage memory 51 will be described in more detail. In FIG. 3, when the mode control 61 receives a start signal from the microprocessor 1, the communication interface 5 starts a bootstrap operation (initial setting operation) (blocks 101 to 104).
First, a communication line for transferring a transfer program from the microprocessor 1 to the communication interface 5 is set to the serial signal line 8 (block 102). The transfer program is transferred from the microprocessor 1 through the serial signal line 8 and stored in the transfer program storage memory 52 (block 103). When the transfer of the transfer program is completed, the communication line on the serial communication line 8 is cut off (block 104).

When the transfer program is stored in the transfer program storage memory 52, execution of the transfer program starts (block 105). By executing the transfer program,
The microprocessor 1 starts transferring the communication program stored in the ROM 2 (block 106). The communication interface 5 sequentially stores the transferred communication programs in the communication program storage memory 51 (block 1).
07). When all of the communication programs are stored in the communication program storage memory 51, execution of the communication program is started (block 108). By starting execution of the communication program, normal communication processing is started (block 10).
9).

The processing in the microprocessor 1 and the communication interface 5 when data is transmitted from the master CPU to an external device will be described. Figure 4 shows the master CP
It is a flowchart for demonstrating each processing content at the time of transmitting data from the U side to the communication interface 5 side. First, when a request to transmit data to an external device occurs on the master CPU side (block 201), the microprocessor 1 checks whether transmission to the external device is possible.
A request is made to return the status of the communication interface 5 (block 202). The communication interface 5 communicates the result of the transmission enable state according to the request of the microprocessor 1 (block 203).

Upon receiving the result from the communication interface 5 and recognizing that the communication interface 5 is in a transmission disabled state (block 204), the microprocessor 1 enters a mode for receiving data from the communication interface 5 (block 204). 205).

Upon recognizing that the communication interface 5 is ready for transmission to an external device (block 206),
The microprocessor 1 sends a transmission request and sends transmission data to the communication interface 5 (block 2).
07).

When receiving the transmission request from the microprocessor 1, the communication interface 5 recognizes that the transmission request has occurred on the master CPU side, and temporarily stores the data transmitted together with the transmission request in the RAM in the communication interface 5. Store (block 208). The data stored in the RAM is output while handshaking the control line from the port specified by the transmission information (block 209).

Next, a process for transmitting data from the external device to the master CPU will be described. FIG. 5 is a flowchart for explaining each processing content when data transmitted from the external device to the communication interface is transmitted to the master CPU side. Normally, since the communication interface 5 is set to the reception state, the data transmitted from the external device is hand-shaked on the control line according to a predetermined communication procedure, received, and stored in the RAM (block 301).

When the microprocessor 1 is ready to receive data from an external device (block 30)
2) The microprocessor 1 is a communication interface 5
The reception status of is checked (block 303). The communication interface 5 judges the inquiry from the microprocessor 1, checks the accumulation status of the data in the RAM, and transmits it to the microprocessor 1 (block 304).

According to the accumulation state of the data transmitted from the communication interface 5, if there is data stored in the RAM (block 305), the microprocessor 1 requests the data stored in the RAM to be transmitted to the communication interface 5 (block 305). Block 306). The communication interface 5 transmits the data stored in the RAM in response to the request of the microprocessor 1 to the microprocessor 1 in accordance with the communication procedure stored in the communication program storage memory 51 (block 307). When the microprocessor 1 receives all of the data transmitted from the communication interface 5 (block 308), it completes receiving the data transmitted from the external device (block 309).

If there is no stored data from the data storage status in the RAM (block 309), the microprocessor 1 checks whether or not there is data to be transmitted to the communication interface 5 (block 310). The transmission control is performed according to the following (block 311). If there is no transmission data (block 312), the microprocessor 1 checks again whether the communication interface 5 is accumulating the reception data (block 303).

As described above, according to the present embodiment, the communication program of the communication interface 5 is transmitted from the microprocessor 1 and changed, so that the communication such as the bit rate of the serial port, the selection of the control line, the handshake method, etc. The procedure can be changed freely.

Further, since the microprocessor 1 and the communication interface 5 are connected by a serial signal line, there is no need for an address decoder for specifying a data transmission destination, so that the circuit can be simplified and the space can be saved. be able to.

Further, since the communication interface can be configured using a general-purpose microprocessor, the cost can be reduced.

[0035]

As described above, according to the present invention, the communication program is transmitted from the master CPU to the communication interface device, and the communication procedure can be changed by changing the contents of the program. Thus, it is possible to provide a communication interface having a very high degree of freedom.

Further, since the transmitted communication program is stored in the electrically erasable read-only memory in the communication interface device, the program is stored even if the power supply is stopped.

[Brief description of the drawings]

FIG. 1 is a block diagram of a communication interface and its periphery for explaining an embodiment of the present invention.

FIG. 2 is a block diagram for explaining the operation of the communication interface 5 in further detail.

FIG. 3 shows a communication program storage memory 5 for storing a communication program.
6 is a flowchart for explaining an operation of transferring the information to the first device;

FIG. 4 is a flowchart for explaining each processing content when data is transmitted from the master CPU to the communication interface 5;

FIG. 5 is a flowchart for explaining each processing content when data transmitted from the external device to the communication interface is transmitted to the master CPU side.

[Description of Signs] 1 microprocessor 2 bus 3 ROM 4 RAM 5 communication interface 6 control line 7, 8, 12, 13 serial communication line 14 external communication line 51 communication program storage memory 52 transfer program storage memory 54 reception register 55 transmission / reception register 62 Bootstrap program memory

Continuation of the front page (56) References JP-A-1-144839 (JP, A) JP-A-61-30842 (JP, A) JP-A-54-98142 (JP, A) JP-A-1-93236 (JP) JP-A-3-182933 (JP, A) JP-A-3-111956 (JP, A) JP-A-2-112043 (JP, A) JP-A-58-22430 (JP, A)

Claims (4)

(57) [Claims] 1. A method for receiving serial data transmitted from a master CPU and transmitting the data to an external communication line in accordance with a predetermined communication procedure, and receiving data on the external communication line and performing serial communication in accordance with a predetermined communication procedure. A communication interface device for sending data to a master CPU, a communication program storage means for storing a communication program for executing the communication procedure, and a transfer for transferring the communication program stored in the master CPU to the communication interface device Transfer program storage means for storing a program; transfer program transfer means for transferring the transfer program from the master CPU to the transfer program storage means in response to receiving a start signal from the master CPU; The transfer program of the program By executing the transfer program after the transfer to the RAM storage means is completed,
And a communication program transfer unit for transferring the communication program stored in the master CPU to a communication program storage unit. By executing the communication program, transmission of data from the communication interface device to the external communication line is performed. When the master CPU detects that it is possible, the data is transmitted to the external communication line according to a condition based on transmission information included in the serial data transmitted from the master CPU, and the master is transmitted from the external communication line to the master. A one-chip semiconductor integrated circuit, wherein when serial data can be sent to a CPU, a reception condition of data received from the external communication line is added to the serial data and sent to the master CPU. Communication interface device consisting of circuits. 2. The communication interface device according to claim 1, wherein said communication program storage means comprises an electrically erasable read-only memory. 3. The communication program according to claim 1, wherein the communication program is the master CPU.
The communication interface device according to claim 1, wherein a plurality of communication interface devices are stored. 4. Receiving serial data transmitted from a master CPU and transmitting the data to an external communication line according to a predetermined communication procedure, and receiving data on the external communication line and performing serial communication according to a predetermined communication procedure. A communication interface device for sending data to a master CPU, a communication program storage means comprising an electrically erasable read-only memory for storing a communication program for executing the communication procedure, and the communication program stored in the master CPU Transfer program storage means comprising a random access memory for storing a transfer program for transferring the transfer program to the communication interface device; and a bootstrap program for transferring the transfer program stored in the master CPU to the communication interface device. A bootstrap program storage means comprising a read-only memory for storing, and the bootstrap program being executed in response to receiving a start signal from the master CPU,
Transfer program transfer means for transferring the transfer program from U to the transfer program storage means, and execution of the transfer program after transfer of the transfer program to the transfer program storage means is completed.
And a communication program transfer unit for transferring the communication program stored in the master CPU to a communication program storage unit. By executing the communication program, transmission of data from the communication interface device to the external communication line is performed. When the master CPU detects that it is possible, the data is transmitted to the external communication line according to a condition based on transmission information included in the serial data transmitted from the master CPU, and the master is transmitted from the external communication line to the master. A one-chip semiconductor integrated circuit, wherein when serial data can be sent to a CPU, a reception condition of data received from the external communication line is added to the serial data and sent to the master CPU. Communication interface device consisting of circuits.