WO2006090473A1 - Data transmission control method and data transmission control apparatus - Google Patents
Data transmission control method and data transmission control apparatus Download PDFInfo
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- WO2006090473A1 WO2006090473A1 PCT/JP2005/003204 JP2005003204W WO2006090473A1 WO 2006090473 A1 WO2006090473 A1 WO 2006090473A1 JP 2005003204 W JP2005003204 W JP 2005003204W WO 2006090473 A1 WO2006090473 A1 WO 2006090473A1
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- data transmission
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/40—Network security protocols
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/28—Timers or timing mechanisms used in protocols
Definitions
- the present invention relates to a data transmission technique, and more particularly to a data transmission method for high-speed data transmission when data is transmitted between devices while receiving a response to confirm the arrival of data with a communication partner device.
- the present invention relates to a data transmission control method and a data transmission control device.
- Fig. 5 shows a concept of connection between devices for data transmission, and conceptually shows an example of connection between devices using the I2C interface.
- the I2C interface uses a master signal 500 and a plurality of slave devices 100, 200 using two types of signal lines: clock signal line SCL (Serial Clock Line) 700 and data signal line SDA (Serial Data Line) 800. , Can transmit data between 900.
- Figure 5 shows the case where there are three slave devices.
- a slave device is assigned a 7-bit slave address, and any number of slave devices within the range represented by the slave address can be connected.
- the clock signal line SCL700 is a signal power line for outputting the clock signal.
- the master device is connected to the clock signal line SCL700. Pause output. This state is called “clock stretch”.
- the data signal line SDA800 is a signal line for sending and receiving data between the master device and the slave device.
- the clock signal line SCL700 and the data signal line SDA800 are supplied via the pull-up resistors (Rp) 760 and 860, respectively. Connected to (VDD) 600!
- FIG. 6 is a conceptual diagram of signal line connection between devices for data transmission, and conceptually shows an example of signal line connection between a master device and a slave device using an I2C interface.
- the connection between slave device 100 and master device 500 shown in the connection concept between devices in FIG. 5 is shown as an example.
- Both the clock signal line SCL700 and the data signal line SDA800 are configured to be capable of bidirectional communication with open drain drive, and the slave device 100 includes open drain circuits 170 and 180 and corresponding reception buffers 171 and 181.
- a data storage unit 110 for storing a data string 111 to be transmitted / received is provided.
- the master device 500 includes open drain circuits 570 and 580 and reception buffers 571 and 581 corresponding to the clock signal line SCL700 and the data signal line SDA800.
- the description of the data storage unit of the master device 500 is omitted.
- FIG. 7 shows a data transmission sequence (1), which is a sequence example when data is transmitted from the master device to the slave device through the I2C interface.
- the data transmission timing viewed from the master device 500 side is shown along the time axis 850, and the data transmission timing viewed from the slave device 100 side force is shown along the time axis 810.
- Master device 500 first generates start condition S, which is a condition for starting data transmission (sequence MS01), and then the slave device address (slave address: 7 bits) and data as the first byte data. Indicates the transmission direction of
- R / W (Read / Write) bit (1 bit) (sequence MS02, MS03).
- the value of the R / W bit is set to the bit value “0” meaning “Write”.
- the slave device 100 collates the slave address assigned to the own device with the slave address information transmitted from the master device card. If they match, the acknowledge signal A, which is confirmation response information, is returned to the master device. (Sequence MS04). In the I2C interface, acknowledge signal means to set the data signal line SDA to "Low".
- master device 500 transmits a memory address indicating the address of the data storage area in data storage unit 110 of slave device 100 (sequence MS05), and after receiving an acknowledge (sequence MS06), master device 500 Data storage capacity in device 500 Data 1 that is the first data is transmitted (sequence MS07). Then, if the response to that is returned (sequence MS08), the data is sequentially transmitted in the same manner as V, then the last data n is transmitted (sequence MS09), and the acknowledgment A for that is sent. After receiving (sequence MS10), a stop condition P is generated (sequence MS11), and the data transmission sequence is terminated.
- the above transmission sequence immediately before transmitting a data string (data 1 1 data n), it is a sequence that transmits the memory address of the data storage area of the slave device 100 that stores the data string. It is specially specified for the I2C interface!
- FIG. 8 shows a data transmission sequence (2), which is a sequence example when data is transmitted from the slave device to the master device through the I2C interface.
- a case where a data string (data 1 1 data n) is transmitted from the slave device 100 to the master device 500 shown in the connection concept between the devices in FIG. 5 will be shown as a representative example.
- the data transmission timing as viewed from the master device 500 side is shown along the time axis 850, and the data transmission timing as viewed from the slave device 100 side is shown along the time axis 810.
- the master device 500 first generates a start condition S, which is a condition for starting data transmission (sequence SM01), then slave device address information (slave address: 7 bits) and information to be transmitted next (memory) R / W (Read / Write) bit (1 bit) indicating the transmission direction of (address) is transmitted (sequence SM02, SM03).
- start condition S is a condition for starting data transmission
- slave device address information slave address: 7 bits
- information to be transmitted next memory
- R / W Read / Write
- the transmission direction of the “memory address” information is transmission, that is, “Write” as seen from the master device, so the bit value “0” meaning “Write” is set.
- Slave device 100 collates the slave address assigned to its own device with the slave address information sent to the master device, and if they match, acknowledge A, which is acknowledgment information, is returned to the master device (sequence SM04).
- acknowledge A which is acknowledgment information
- the master device 500 transmits “memory address” information, which is the address of the data storage area in the data storage unit 110 of the slave device 100 (sequence MS05), and receives the acknowledge A corresponding thereto (sequence SM06).
- the master device 500 again generates a start condition S (sequence SM07), and the slave device 100 to the master device 500 as the transmission direction of slave address information (7 bits) of the same slave device 100 and the next data.
- acknowledgment A which is acknowledgment information (sequence SM10)
- the slave device 100 having received the R / W bit of “ ⁇ ”, which means the slave address information and the data transmission to the master device in the sequence SM08, SM09, is stored in the data storage unit 110.
- Data area force indicated by “memory address” specified in sequence SM05 above Reads data 1 as the first data and transmits it to master device 500 (sequence SM11). Acknowledge A which is confirmation response information of master device strength is returned. Waits for it (sequence SM12). Thereafter, the data is sequentially read from the data storage unit 110 and transmitted to the master device 500 in the same procedure. After the data n which is the last data is transmitted (sequence SM13, SM14), the master device 500 transmits the transmission end information. Returns a non-notification NA, then generates a stop condition (sequence SM15) and terminates the data transmission sequence.
- FIG 9 shows the signal timing (1) during data transmission.
- the clock signal SCL701 and the data signal SDA801 are generated during the generation of the start condition, the transmission of the data bit, and the generation of the stop condition by the I2C interface. Show time relationship.
- the start condition C01 is a state in which the data signal SDA 801 changes from “High” to “Low” while the clock signal SCL701 is in the “High” state, which means the start of data transmission.
- t indicates the setup time of start condition C01 and start
- the state of the data signal SDA 801 must be constant while the clock signal SCL701 is "High”, and the data signal SDA801 is between “High” and “Low”. The state can be changed only when the clock signal SCL701 is "Low”, and the data signal SD A801 is sampled at the rising edge of the clock signal SCL701.
- the setup time t of the data signal SDA801 and the hold of the data signal SDA801 is the setup time t of the data signal SDA801 and the hold of the data signal SDA801
- the stop condition C02 is the data signal SDA while the clock signal SCL701 is "High".
- the state in which 801 changes from “Low” to “High” means the end of data transmission.
- the minimum value of the interval t between C02 and the next start condition C03 is specified.
- Figure 10 shows the signal timing (2) during data transmission.
- the data signal SDA 801 is sampled at the rising edge of the clock signal SCL701. For this reason, for example, when data is transmitted to the slave device master device, it takes time to read data from the data storage unit of the slave device, and the determination time t of the data signal SDA801 increases,
- the output of the data signal SDA801 may be delayed.
- the confirmation time t of the signal SDA801 can be extended.
- the data signal SDA801 has a fixed time t and a clock stretch allowable time t.
- FIG. 11 is a signal timing overview of the prior art data transmission control.
- the first byte is transmitted from the master device 500 to the slave device 900 configured in the prior art via the I2C interface.
- the signal timing relationship until the slave device 900 starts to transmit data 1 as the first transmission data to the master device 500 is conceptually shown.
- slave device 900 is generated by master device 500 After the start condition S is detected (timing T901), the 7-bit slave address information sent from the master device 500 and the R / W bit sent in (!
- FIG. 12 shows a configuration of a data transmission control device of the prior art.
- the slave device 900 shown in the connection concept of FIG. 5 is shown as being configured by the prior art.
- Information transmitted from the master device 500 via the data signal line SDA800 under the control of the clock signal line SCL700 is input to the reception register 901 via the buffer 981.
- the reception data analysis unit 902 reads the data stored in the reception register 901 and analyzes the contents. For example, it may be information indicating a data transmission request from the master device.
- the data read transmission unit 903 is activated, the first data is read from the data string 911 stored in the data storage unit 910, an acknowledgment is transmitted, and the first data read after the clock stretch is released. Send.
- the data read transmission unit 903 reads data in a predetermined order from the data sequence 911 stored in the data storage unit 910 and reads the data.
- the data is transferred to the received data analysis unit 902.
- the conventional data transmission control is configured to read data from the data storage unit 910 in the clock stretch state and then output the read data to the data signal line SDA800.
- the data transmission timing was affected by the data read time from the data storage unit 910 and fluctuated in the direction of delay.
- Fig. 13 is an operation flow (1) of the data transmission control of the prior art.
- the slave device 900 (configured as a transmission control device of the prior art) after the reception of 1-byte information of the data transmission request information from the master device. Demonstrate the data transmission control processing procedure.
- the slave device 900 configured in the prior art receives the first byte of data from the master device 500 (step S901), the slave device 900 first sets the clock stretch and holds the clock signal line SCL900 at "Low".
- step S902 the slave address and R / W bit contents included in the first byte received are analyzed, and if the slave address matches its own device address and the R / W bit has a value of 1 ” Then, it is determined that it means a data transmission request from the slave device to the master device (step S903), and the leading force of the area storing the transmission data string in the data storage unit 910 is read out.
- step S904 after transmitting the confirmation response information (attenuation) for the first byte information received in step S901 to the master device 500 (step S905)
- the lock stretch is released (step S906), and the data read in step S904 is transmitted to the master device 500 (step S907).
- step S908 it waits for the receipt of acknowledgment (information) or transmission end information (non-acknowledge) from master device 500 (step S908), and determines whether the received information is acknowledged or non-acknowledged (step S909). In case of non-acknowledge (YES), the processing is terminated, and in case of acknowledge (NO), the following processing is performed.
- acknowledgment information
- transmission end information non-acknowledge
- step S910 After setting the clock stretch (step S910), send data in the data storage unit 910 The data to be transmitted next is read (step S911), the clock stretch is canceled (step S912), the read data is transmitted (step S913), and the process returns to step S908.
- the method for determining the start area address of the data string 911 stored in the data storage unit 910 is described in this operation flow, but the data shown in FIG. In the sequence SM05 shown in the transmission sequence (2), the master device 500 notifies the slave device 900 in advance.
- FIG. 14 is an operation flow (2) of the data transmission control of the prior art, and the master device when the master device configured as the data transmission control device of the prior art autonomously transmits data to the slave device The processing procedure of the data transmission control on the side is shown.
- the master device configured in the prior art reads the data string force data stored in its own data storage unit (S921) and transmits the data to the slave device (step S922). Wait for a reply of acknowledgment information (Attanoridge) (step S923).
- the acknowledgment information is received from the slave device, it is determined whether or not the data transmitted immediately before is the final data of the data string (S924). If it is not the final data (NO), return to step S921 to read the next data. If it is final data (YES), the process is terminated.
- the data transmission control method of the prior art when data is transmitted from the own device by autonomous timing, the data is first read from the data storage unit, and then the read data is transmitted.
- Non-Patent Document 1 The details of the data transmission technology using the I2C interface described above are disclosed in Non-Patent Document 1.
- Non-Patent Document 1 12C Bus Specification, Version 2.1, January 2000, published by Philips Japan. Disclosure of the invention
- Slave devices that conform to the conventional I2C interface specifications adjust the timing of data transmission using clock stretching as described above. For example, when a slave device transmits a data string in response to a data transmission request from a master device, it takes time to read the data from the data storage unit, so that data is transmitted by a clock stretch during the read time. It was paused. This clock stretch state occurs every time one byte of data is read, and when transmitting a large amount of data string, it was a factor that deteriorated the data transmission performance of the entire system.
- clock stretch allowable time t (for example, within 5 s) are very short.
- the present invention relates to a method for controlling data transmission while reading data in a predetermined order and storing data in a data storage unit and receiving a confirmation response for data arrival as much as the communication partner device.
- the data to be transmitted is previously read from the data storage unit and stored in the transmission register, and the data stored in the transmission register is transmitted when the data transmission timing is detected.
- the data to be transmitted next is already stored in the transmission register when the data transmission timing is detected, and the data is transmitted in a processing time sufficient to switch the transmission switch from the transmission register to the data signal line. And delay of data transmission timing can be minimized.
- the data transmission timing is determined when data transmission request information is received from a communication partner device, when an autonomous data transmission request is generated from the device, and the communication partner device. It is also possible to configure so that it is a deviation when receiving acknowledgment information of data arrival from.
- the data transmission timing delay can be suppressed in a manner that covers all possible cases for data transmission conditions, and high-speed data transmission of the entire apparatus can be achieved.
- the present invention can be further configured to perform data transmission and data arrival confirmation response in accordance with the communication protocol of the I2C serial interface.
- high-speed data transmission can be achieved while generally supporting connection between various devices in a form compliant with the communication protocol of the I2C serial interface.
- the data to be transmitted next is read in advance and stored in the transmission register before the transmission timing is detected. At this time, the data stored in the transmission register can be immediately output to the data signal line, and high-speed data transmission can be achieved.
- FIG. 1 shows the configuration of the data transmission control device of the present invention.
- the slave device 100 shown in the connection concept of FIG. 5 is configured as the data transmission control device of the present invention.
- the data reading unit 103 is stored in the data storage unit 110!, And the data is read from the data string 111 and stored in the transmission register 104.
- information transmitted from the master device 500 via the data signal line SDA800 is input to the reception register 101 via the buffer 181, and the reception data analysis unit 102 receives the data stored in the reception register 101.
- the reception data analysis unit 102 After reading and setting the clock stretch, analyze the contents, and if it is the data transmission request information from the master device, return the confirmation response information (analog) and then cancel the clock stretch.
- Clock stretch is set and released by driving the open drain circuit 170 of the clock signal line SCL700.
- the transmission switch 105 is turned ON, and the data stored in the transmission register is output to the open drain circuit 180 and transmitted as a serial signal to the data signal line SDA800.
- the data reading unit 103 is activated and the data storage unit 110 is activated. Start reading the next data from.
- the reception data analysis unit 102 waits for receipt of confirmation response information (atanridge) from the master device in parallel with the next data read processing of the data read unit 103 activated above, and when the confirmation response information is received.
- the transmission switch 105 is turned ON and the data stored in the transmission register is transmitted to the master device.
- the next data read process is performed in advance, so normally the data to be transmitted next is already stored in the transmission register 104, and only the process of turning ON the transmission switch 105 is performed.
- Send immediately at cash register The data stored in the master is transmitted to the master device.
- the clock stretch may actually be set. However, since this time is negligible compared to the time for reading data from the memory, the essence of the present invention. Has no effect.
- the received data analysis unit 102 waits for a next data read completion notification from the data read unit 103 that does not operate in parallel with the next data read processing of the data read unit 103, and recognizes the read completion notification. It may be configured to wait for reception of confirmation response information (atanridge) from the master device at the time. Even in this case, since the reception timing of the acknowledgment information (attenuation) is usually later than the data read completion timing of the data storage unit, the data transmission timing can be similarly accelerated.
- the above processing procedure is repeated until the transmission end information (non acknowledge) indicating the end of data transmission from the master device is received, and the data transmission sequence is terminated.
- the data is not transmitted after the data is read from the data storage unit 110 as in the prior art, but is transmitted in parallel while waiting for reception of the response confirmation information from the communication partner device. Since the data is read from the data storage unit 110 and prepared, the data transmission timing is accelerated by the data reading time, and the data transmission speed can be increased.
- FIG. 2 is an operation flow (1) of data transmission control according to the present invention, and shows a processing procedure of data transmission control of the slave device 100 when data transmission request information is received from the master device 500.
- the slave device 100 configured by the transmission control device of the present invention is a data storage unit first. Data to be transmitted first from 110 is read in advance and stored in the transmission register 104 (step S 101).
- step S102 when the first byte is received from the master device 500 (step S102), the clock stretch is set and the clock signal line SCL700 is held "Low” (step S103), and then the received first byte is received. Analyzes the stored slave address information and the contents of the R / W bit, and the slave address is the same as the address assigned to the local device! /, And the R / W bit value is, 1 " If it is determined that the request is also a data transmission request to the master device (step S104), after sending acknowledgment information (a knowledge) to the master device 500 (step S105), the clock stretch is canceled (step S106).
- the transmission switch 105 is switched to the ON (connected) state and the data in the transmission register is transmitted to the master device (step 107), where the first area of the transmission data string 111 in the data storage unit 110 is allocated. For less, this operation flow is described as ⁇ , but are previously notified from the master device 500 to the slave device 100 in the sequence SM05 shown by the data transmission sequence of FIG. 8 (2).
- step S108 After reading the next data in the data string 11 in the data storage unit 110 and storing it in the transmission register 104 (step S108), the confirmation response information from the master device 500 (the “analog”) or the transmission end information (the non-acknowledge). Wait for reception (step S109), determine whether the received information is non-acknowledged or acknowledged (step S110), if it is non-acknowledged (YES) terminate processing, if not acknowledged (NO), send The data stored in the register 104 is transmitted by switching the transmission switch 105 (step SI11), and the process returns to step S108.
- clock stretch may be set during the process of determining whether the received data is the acknowledgment response information (attenuation), but this can be ignored compared to the data read time from the memory. Therefore, the essence of the present invention is not affected.
- the delay in data transmission timing can be minimized, and high-speed data transmission can be achieved.
- FIG. 3 is an operation flow (2) of the data transmission control of the present invention.
- the master device 500 configured by the data transmission control device of the present invention autonomously sends data to the slave device 100.
- the processing procedure of data transmission control in the case of transmission is shown.
- the master device 500 reads the transmission data of its own data storage unit and stores the data in the transmission register (step S121). After the data stored in the transmission register is transmitted by switching the transmission switch (step S122), the data storage unit also reads out the data to be transmitted next and stores it in the transmission register (step S123). Waiting for the receipt of confirmation response information from the slave device 100 for the data transmitted to the device 100, and receiving the confirmation response information (step S124), it is determined whether the data transmitted immediately before is the final data power ( In step S125), if it is not final data (NO), the process returns to step S122, and if final, (YES) processing is terminated.
- the data stored in the transmission register is processed by simply switching the transmission switch, and the data reading process of the data storage unit that requires time is performed on the data transmitted immediately before. Since it is performed during the time period required for the return of acknowledgment information from the communication partner device, the data to be transmitted next is usually already stored in the transmission register when the acknowledgment information is received. The next data can be transmitted with a minimum processing time.
- Fig. 4 shows the signal timing outline of the data transmission control according to the present invention.
- the slave device 100 configured as the data transmission control device according to the present invention receives the data transmission request from the master device 500 through the I2C interface.
- FIG. 2 conceptually shows the signal timing relationship until data 1 which is the transmission data of 1 starts to be transmitted to the master device 500.
- the slave device 100 After detecting the start condition S generated by the master device 500 (timing T101), the slave device 100 receives the 7-bit slave address information transmitted from the master device 500 (timing T102) and subsequently transmits it.
- the clock stretch is set and the slave address information and R / W bit information contained in the first byte received are analyzed, and the slave address matches the address of its own device.
- the slave device 100 Since the value of the R / W bit is “T”, it is determined that the request is a data transmission request to the slave device 100 (timing T103). After that, the slave device 100 transmits acknowledgment information (attenuation) A to cancel clock stretching (timing T104), and then starts transmitting data stored in the transmission register 104 (timing ⁇ 105).
- the above tie is used. The time required to read data from the data storage unit 110, which was necessary in the prior art, between the T103 and T104 is no longer required, and the «I duration time in the clock stretch state is minimized, allowing high-speed data transmission. It can be carried out.
- the case where the I2C interface is used as a communication interface between apparatuses has been described as a representative example.
- the present invention can be similarly applied to cases where other communication interfaces are used.
- the present invention can be applied to both a master device and a slave device in the configuration of the embodiment, and can be similarly applied to any device that performs data communication while performing a data arrival confirmation response. .
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Abstract
[PROBLEMS] In a conventional technique of transmitting data with an acknowledgement of arrival of the data being received, a reading of the data from a data storing part (memory) and a transmission of the read data were performed in a sequential processing order. For example, in a data transmission based on I2C interface specification, during a time-consuming reading of data from the memory, the clock signal was held to temporarily halt the data transmission, thereby establishing a timing adjustment. This temporal halt would occur every one-byte of transmission, causing a reduction in the data transfer rate. [MEANS FOR SOLVING PROBLEMS] A standby time or the like during reception of an acknowledgement is utilized to read data from the data storing part and then store the data into a transmission register in advance. Upon detection of a transmission timing, the data stored in the transmission register is transmitted, thereby raising the speed of the data transmission process.
Description
明 細 書 Specification
データ送信制御方法、及びデータ送信制御装置 Data transmission control method and data transmission control device
技術分野 Technical field
[0001] 本発明は、データの送信技術に係り、特に、通信相手装置とデータ到達の確認応 答を取りながら装置間でデータの伝送を行う際のデータ送信を高速ィ匕するためのデ ータ送信制御方法及びデータ送信制御装置に関する。 TECHNICAL FIELD [0001] The present invention relates to a data transmission technique, and more particularly to a data transmission method for high-speed data transmission when data is transmitted between devices while receiving a response to confirm the arrival of data with a communication partner device. The present invention relates to a data transmission control method and a data transmission control device.
背景技術 Background art
[0002] 装置間でのデータ伝送方法としては様々な方法がある力 シリアルインターフエ一 スによりデータを伝送する方法としてはフィリップス社により提唱された I2Cインターフ エースが知られている。 [0002] There are various methods for transmitting data between devices. As a method for transmitting data through a serial interface, the I2C interface proposed by Philips is known.
[0003] 図 5はデータ伝送のための装置間の接続概念で、上記の I2Cインターフェースによ る装置間の接続の例を概念的に示したものである。 [0003] Fig. 5 shows a concept of connection between devices for data transmission, and conceptually shows an example of connection between devices using the I2C interface.
I2Cインターフェースでは、クロック信号線 SCL(Serial Clock Line)700、および、デ ータ信号線 SDA(Serial Data Line)800の 2種類の信号線を用いて、マスター装置 500 と複数のスレーブ装置 100、 200、 900との間でデータの伝送を行うことができる。図 5 ではスレーブ装置が 3台の場合を示している力 スレーブ装置には 7ビットのスレーブ アドレスが割り当てられ、そのスレーブアドレスであらわされる範囲の任意台数のスレ ーブ装置が接続可能である。 The I2C interface uses a master signal 500 and a plurality of slave devices 100, 200 using two types of signal lines: clock signal line SCL (Serial Clock Line) 700 and data signal line SDA (Serial Data Line) 800. , Can transmit data between 900. Figure 5 shows the case where there are three slave devices. A slave device is assigned a 7-bit slave address, and any number of slave devices within the range represented by the slave address can be connected.
[0004] クロック信号線 SCL700はマスター装置力 クロック信号を出力するための信号線で ある力 スレーブ装置にてクロック信号線 SCLを" Low"状態にしている場合はマスタ 一装置はクロック信号線 SCL700の出力を一時停止する。この状態を"クロックストレツ チ"という。データ信号線 SDA800はマスター装置とスレーブ装置の間でデータを送 受信するための信号線であり、クロック信号線 SCL700およびデータ信号線 SDA800 はそれぞれプルアップ抵抗 (Rp)760、 860を介して電源電圧 (VDD)600に接続されて!ヽ る。 [0004] The clock signal line SCL700 is a signal power line for outputting the clock signal. When the clock signal line SCL is set to "Low" in the slave device, the master device is connected to the clock signal line SCL700. Pause output. This state is called “clock stretch”. The data signal line SDA800 is a signal line for sending and receiving data between the master device and the slave device. The clock signal line SCL700 and the data signal line SDA800 are supplied via the pull-up resistors (Rp) 760 and 860, respectively. Connected to (VDD) 600!
[0005] 図 6はデータ伝送のための装置間の信号線接続概念で、 I2Cインターフェースによ るマスター装置とスレーブ装置との間の信号線接続の例を概念的に示したものであ
る。ここでは、上記図 5の装置間の接続概念で示したスレーブ装置 100とマスタ装置 500と間の接続を例として示している。 [0005] FIG. 6 is a conceptual diagram of signal line connection between devices for data transmission, and conceptually shows an example of signal line connection between a master device and a slave device using an I2C interface. The Here, the connection between slave device 100 and master device 500 shown in the connection concept between devices in FIG. 5 is shown as an example.
クロック信号線 SCL700およびデータ信号線 SDA800は共にオープンドレイン駆動 の双方向通信が可能な構成となっており、スレーブ装置 100はオープンドレイン回路 170、 180及び対応する受信バッファ 171、 181を備え、また、送受信するデータ列 111 を記憶するデータ記憶部 110を備えている。 Both the clock signal line SCL700 and the data signal line SDA800 are configured to be capable of bidirectional communication with open drain drive, and the slave device 100 includes open drain circuits 170 and 180 and corresponding reception buffers 171 and 181. A data storage unit 110 for storing a data string 111 to be transmitted / received is provided.
マスター装置 500も同様に、クロック信号線 SCL700、データ信号線 SDA800に対応 するオープンドレイン回路 570、 580及び受信バッファ 571、 581を備えている。ここでは 、マスター装置 500のデータ記憶部の記述は省略して 、る。 Similarly, the master device 500 includes open drain circuits 570 and 580 and reception buffers 571 and 581 corresponding to the clock signal line SCL700 and the data signal line SDA800. Here, the description of the data storage unit of the master device 500 is omitted.
[0006] 図 7はデータ伝送シーケンス(1)で、 I2Cインターフェースによりマスター装置からス レーブ装置へデータ伝送する際のシーケンス例である。上記図 5の装置間の接続概 念で示したマスター装置 500からスレーブ装置 100へデータ列(データ 1一データ n)を 送信する場合を代表例として示して ヽる。 FIG. 7 shows a data transmission sequence (1), which is a sequence example when data is transmitted from the master device to the slave device through the I2C interface. A case where a data string (data 1 1 data n) is transmitted from the master device 500 to the slave device 100 shown in the connection concept between the devices in FIG. 5 is shown as a representative example.
[0007] マスター装置 500側からみたデータ伝送タイミングを時間軸 850に沿って、またスレ ーブ装置 100側力もみたデータ伝送タイミングを時間軸 810に沿って示している。 マスター装置 500は、まずデータ伝送を開始するための条件であるスタート条件 Sを 生成した後(シーケンス MS01)、最初のバイトデータとして送信先となるスレーブ装置 のアドレス(スレーブアドレス: 7ビット)およびデータの伝送方向を示す [0007] The data transmission timing viewed from the master device 500 side is shown along the time axis 850, and the data transmission timing viewed from the slave device 100 side force is shown along the time axis 810. Master device 500 first generates start condition S, which is a condition for starting data transmission (sequence MS01), and then the slave device address (slave address: 7 bits) and data as the first byte data. Indicates the transmission direction of
R/W(Read/Write)ビット (1ビット)を送信する (シーケンス MS02、 MS03)。図 7の例では 、データの伝送方向はマスター装置からみて送信つまり" Write"となるので、 R/Wビッ トの値は" Write"を意味するビット値" 0"に設定されている。スレーブ装置 100は自装 置に割り当てられたスレーブアドレスと、マスター装置カゝら送信されてきたスレーブァ ドレス情報を照合し、一致した場合は確認応答情報であるァクノリッジ信号 Aをマスタ 一装置へ返信する(シーケンス MS04)。 I2Cインターフェースでは、ァクノリッジ信号と はデータ信号線 SDAを" Low"にすることを意味する。 Transmit R / W (Read / Write) bit (1 bit) (sequence MS02, MS03). In the example of FIG. 7, since the data transmission direction is transmission, that is, “Write” as seen from the master device, the value of the R / W bit is set to the bit value “0” meaning “Write”. The slave device 100 collates the slave address assigned to the own device with the slave address information transmitted from the master device card. If they match, the acknowledge signal A, which is confirmation response information, is returned to the master device. (Sequence MS04). In the I2C interface, acknowledge signal means to set the data signal line SDA to "Low".
[0008] 次にマスター装置 500はスレーブ装置 100のデータ記憶部 110内のデータ格納領域 のアドレスを意味するメモリアドレスを送信し (シーケンス MS05)、それに対するァクノ リッジを受信後(シーケンス MS06)、マスタ装置 500内のデータ記憶部力 読み出した
最初のデータであるデータ 1を送信する(シーケンス MS07)。そして、それに対するァ タノリッジが返送されたならば (シーケンス MS08)、同様にして順次データを送信して V、き、最後のデータであるデータ nを送信して(シーケンス MS09)それに対するァクノ リッジ Aを受信した(シーケンス MS10)後に、ストップ条件 Pを生成して(シーケンス MS11)、データ伝送シーケンスを終結する。上記の伝送シーケンスの例では、データ 列(データ 1一データ n)を送信する直前に、そのデータ列を格納するスレーブ装置 100のデータ格納領域のメモリアドレスを送信するシーケンスとなっている力 これに つ!ヽては I2Cインターフェースでは特に規定されて!、な!/、。 [0008] Next, master device 500 transmits a memory address indicating the address of the data storage area in data storage unit 110 of slave device 100 (sequence MS05), and after receiving an acknowledge (sequence MS06), master device 500 Data storage capacity in device 500 Data 1 that is the first data is transmitted (sequence MS07). Then, if the response to that is returned (sequence MS08), the data is sequentially transmitted in the same manner as V, then the last data n is transmitted (sequence MS09), and the acknowledgment A for that is sent. After receiving (sequence MS10), a stop condition P is generated (sequence MS11), and the data transmission sequence is terminated. In the example of the above transmission sequence, immediately before transmitting a data string (data 1 1 data n), it is a sequence that transmits the memory address of the data storage area of the slave device 100 that stores the data string. It is specially specified for the I2C interface!
[0009] 図 8はデータ伝送シーケンス (2)で、 I2Cインターフェースによりスレーブ装置からマ スター装置へデータ伝送する際のシーケンス例である。前記図 5の装置間の接続概 念で示したスレーブ装置 100からマスター装置 500へデータ列(データ 1一データ n)を 送信する場合を代表例として示して ヽる。 FIG. 8 shows a data transmission sequence (2), which is a sequence example when data is transmitted from the slave device to the master device through the I2C interface. A case where a data string (data 1 1 data n) is transmitted from the slave device 100 to the master device 500 shown in the connection concept between the devices in FIG. 5 will be shown as a representative example.
[0010] マスター装置 500側からみたデータ伝送タイミングを時間軸 850に沿って、またスレ ーブ装置 100側力もみたデータ伝送タイミングを時間軸 810に沿って示している。 マスター装置 500は、まずデータ伝送を開始するための条件であるスタート条件 Sを 生成した後(シーケンス SM01)、スレーブ装置のアドレス情報(スレーブアドレス: 7ビ ット)および次に送信する情報 (メモリアドレス)の伝送方向を示す R/W(Read/Write)ビ ット (1ビット)を送信する (シーケンス SM02、 SM03)。図 8の例では、「メモリアドレス」情 報の伝送方向はマスター装置からみて送信つまり" Write"となるので、 "Write"を意味 するビット値" 0"にしておく。スレーブ装置 100は自装置に割り当てられたスレーブアド レスと、マスター装置力も送信されてきたスレーブアドレス情報を照合し、一致した場 合は確認応答情報であるァクノリッジ Aをマスター装置へ返信する(シーケンス SM04) 。次にマスター装置 500はスレーブ装置 100のデータ記憶部 110内のデータ格納領域 のアドレスである「メモリアドレス」情報を送信し(シーケンス MS05)、それに対するァク ノリッジ Aを受信する(シーケンス SM06)。 [0010] The data transmission timing as viewed from the master device 500 side is shown along the time axis 850, and the data transmission timing as viewed from the slave device 100 side is shown along the time axis 810. The master device 500 first generates a start condition S, which is a condition for starting data transmission (sequence SM01), then slave device address information (slave address: 7 bits) and information to be transmitted next (memory) R / W (Read / Write) bit (1 bit) indicating the transmission direction of (address) is transmitted (sequence SM02, SM03). In the example of FIG. 8, the transmission direction of the “memory address” information is transmission, that is, “Write” as seen from the master device, so the bit value “0” meaning “Write” is set. Slave device 100 collates the slave address assigned to its own device with the slave address information sent to the master device, and if they match, acknowledge A, which is acknowledgment information, is returned to the master device (sequence SM04). ) Next, the master device 500 transmits “memory address” information, which is the address of the data storage area in the data storage unit 110 of the slave device 100 (sequence MS05), and receives the acknowledge A corresponding thereto (sequence SM06).
[0011] 引き続いてマスタ装置 500は再びスタート条件 Sを生成し (シーケンス SM07)、同じス レーブ装置 100のスレーブアドレス情報(7ビット)及び次のデータの伝送方向としてス レーブ装置 100からマスター装置 500への方向を意味する R/Wビット情報 ("1")を送信
し (シーケンス SM08、 SM09)、それに対する確認応答情報であるァクノリッジ Aを受信 した後(シーケンス SM10)、スレーブ装置 100からデータが送信されてくるのを待ち合 わせる。 [0011] Subsequently, the master device 500 again generates a start condition S (sequence SM07), and the slave device 100 to the master device 500 as the transmission direction of slave address information (7 bits) of the same slave device 100 and the next data. Send R / W bit information ("1") indicating the direction to (Sequence SM08, SM09) After receiving acknowledgment A, which is acknowledgment information (sequence SM10), it waits for data to be transmitted from slave device 100.
[0012] 一方、上記のシーケンス SM08、 SM09でスレーブアドレス情報およびスレーブ装置 力 マスター装置へのデータ伝送を意味する値 "Γの R/Wビットを受信したスレーブ 装置 100は、データ記憶部 110内の上記シーケンス SM05で指定された「メモリアドレス 」が示すデータ領域力 最初のデータであるデータ 1を読み出してマスター装置 500 へ送信し (シーケンス SM11)、マスタ装置力もの確認応答情報であるァクノリッジ Aが 返信されるのを待ち合わせる(シーケンス SM12)。以後順次データ記憶部 110からデ ータを読み出して同様の手順でマスター装置 500へ送信し、最後のデータであるデ ータ nを送信後(シーケンス SM13、 SM14)、マスター装置 500が送信終了情報であるノ ンァタノリッジ NAを返信し、その後ストップ条件を生成して(シーケンス SM15)データ 伝送シーケンスを終結する。 On the other hand, the slave device 100 having received the R / W bit of “Γ”, which means the slave address information and the data transmission to the master device in the sequence SM08, SM09, is stored in the data storage unit 110. Data area force indicated by “memory address” specified in sequence SM05 above Reads data 1 as the first data and transmits it to master device 500 (sequence SM11). Acknowledge A which is confirmation response information of master device strength is returned. Waits for it (sequence SM12). Thereafter, the data is sequentially read from the data storage unit 110 and transmitted to the master device 500 in the same procedure. After the data n which is the last data is transmitted (sequence SM13, SM14), the master device 500 transmits the transmission end information. Returns a non-notification NA, then generates a stop condition (sequence SM15) and terminates the data transmission sequence.
[0013] 上記のシーケンス SM08、 SM09でマスター装置からスレーブ装置へ送信されるデー タ、つまり、スレーブアドレス情報(7ビット)と値, T,の R/Wビットは、スレーブ装置から マスター装置へのデータ送信要求を意味しているため、以降の記述ではこのデータ のことを「データ送信要求」とも表記する。 [0013] The data transmitted from the master device to the slave device in the above-described sequences SM08 and SM09, that is, the slave address information (7 bits), the value, and the R / W bit of T, are transmitted from the slave device to the master device. Since this means a data transmission request, this data is also referred to as a “data transmission request” in the following description.
また、上記の図 8のデータ伝送シーケンス(2)に示されている「メモリアドレス」につ V、ては、 I2Cインターフェースでは特に規定されて!、な!/、。 In addition, the “memory address” shown in the data transmission sequence (2) in FIG. 8 above is specified in particular for the I2C interface!
[0014] 図 9はデータ伝送時の信号タイミング(1)で、 I2Cインターフェースによるスタート条 件の生成、データビットの伝送、及びストップ条件の生成の際のクロック信号 SCL701 とデータ信号 SDA801との間の時間関係を示して 、る。 [0014] Figure 9 shows the signal timing (1) during data transmission. The clock signal SCL701 and the data signal SDA801 are generated during the generation of the start condition, the transmission of the data bit, and the generation of the stop condition by the I2C interface. Show time relationship.
スタート条件 C01とはクロック信号 SCL701が" High"状態の間にデータ信号 SDA 801が" High"から" Low"に変化した状態のことで、データ伝送の開始を意味する。 I2C インターフェースではスタート条件 C01のセットアップ時間を示す t およびスタート The start condition C01 is a state in which the data signal SDA 801 changes from “High” to “Low” while the clock signal SCL701 is in the “High” state, which means the start of data transmission. In the I2C interface, t indicates the setup time of start condition C01 and start
SU.STA SU.STA
条件 C01のホールド時間を示す t のそれぞれ最小値が規定されて!ヽる。 Each minimum value of t indicating the hold time of condition C01 is specified! Speak.
HD.STA HD.STA
[0015] データビットの伝送の際は、クロック信号 SCL701が" High"の間はデータ信号 SDA 801の状態は一定でなければならず、データ信号 SDA801が" High"ど' Low"の間で
状態を変更できるのはクロック信号 SCL701が" Low"のときに限られ、データ信号 SD A801はクロック信号 SCL701の立ち上がりでサンプルされる。 I2Cインターフェースで は、データ信号 SDA801のセットアップ時間 t 、データ信号 SDA801のホールド [0015] During data bit transmission, the state of the data signal SDA 801 must be constant while the clock signal SCL701 is "High", and the data signal SDA801 is between "High" and "Low". The state can be changed only when the clock signal SCL701 is "Low", and the data signal SD A801 is sampled at the rising edge of the clock signal SCL701. In the I2C interface, the setup time t of the data signal SDA801 and the hold of the data signal SDA801
SU.DAT SU.DAT
時間 t 、クロック信号 SCL701の Low信号パルス幅 t 、およびクロック信号 SCL Time t, low signal pulse width t of clock signal SCL701, and clock signal SCL
HD.DAT LOW HD.DAT LOW
701の High信号パルス幅 t のそれぞれの最小値が規定されて ヽる。 The minimum value of each 701 High signal pulse width t is specified.
HIGH HIGH
[0016] ストップ条件 C02とはクロック信号 SCL701が" High"状態の間にデータ信号 SDA [0016] The stop condition C02 is the data signal SDA while the clock signal SCL701 is "High".
801が" Low"から" High"に変化した状態のことで、データ伝送の終結を意味する。 I2C インターフェースでは、ストップ条件 C02のセットアップ時間 t 、およびストップ条件 The state in which 801 changes from “Low” to “High” means the end of data transmission. In the I2C interface, the setup time t of the stop condition C02 and the stop condition
SU.STO SU.STO
C02と次のスタート条件 C03との間隔 t のそれぞれの最小値が規定されている。 The minimum value of the interval t between C02 and the next start condition C03 is specified.
BUF BUF
[0017] 図 10はデータ伝送時の信号タイミング(2)で、 I2Cインターフェースにおけるデータ 信号 SDA801の確定時間 t とクロックストレッチ許容時間 t の時間関係について [0017] Figure 10 shows the signal timing (2) during data transmission. The time relationship between the fixed time t of the data signal SDA801 and the allowable clock stretch time t in the I2C interface.
AA Strech AA Strech
示している。 Show.
前記図 9のデータ伝送時の信号タイミング(1)で示したように、データ信号 SDA 801はクロック信号 SCL701の立ち上がりでサンプルされる。このため、例えば、スレー ブ装置力 マスター装置にデータを送信する際に、スレーブ装置のデータ記憶部か らのデータ読み出しに時間を要し、データ信号 SDA801の確定時間 t が大きくなり、 As shown in the signal timing (1) during data transmission in FIG. 9, the data signal SDA 801 is sampled at the rising edge of the clock signal SCL701. For this reason, for example, when data is transmitted to the slave device master device, it takes time to read data from the data storage unit of the slave device, and the determination time t of the data signal SDA801 increases,
AA AA
その結果データ信号 SDA801の出力が遅延する場合がある。このようなときは、クロッ クストレッチ、つまり、スレーブ装置側でクロック信号 SCL801を" Low"状態に保持して おくことによりデータ信号 SDA801のサンプリングが行われないようにすることができ、 これによりデータ信号 SDA801の確定時間 t を引き延ばすことができる。図 10のデ As a result, the output of the data signal SDA801 may be delayed. In such a case, it is possible to prevent the data signal SDA801 from being sampled by clock stretching, that is, by holding the clock signal SCL801 in the “Low” state on the slave device side. The confirmation time t of the signal SDA801 can be extended. Figure 10
AA AA
ータ伝送時の信号タイミング(2)はこのような状況を示している。 I2Cインターフェース ではデータ信号 SDA801の確定時間 t 、およびクロックストレッチ許容時間 t につ Signal timing (2) during data transmission indicates such a situation. In the I2C interface, the data signal SDA801 has a fixed time t and a clock stretch allowable time t.
AA Strech AA Strech
Vヽてはその上限値は規定されて 、な!、。 The upper limit is specified for V!
[0018] 図 11は従来技術のデータ送信制御の信号タイミング概要で、 I2Cインターフェース にお!/、て、マスター装置 500から従来技術で構成されるスレーブ装置 900へ最初の 1 バイトを送信し、それに対してスレーブ装置 900が最初の送信データであるデータ 1を マスター装置 500へ送信開始するまでの信号タイミング関係を概念的に示している。 従来技術で構成されて 、るスレーブ装置 900は、マスター装置 500により生成された
スタート条件 Sを検出後 (タイミング T901)、マスター装置 500から送信されてくる 7ビット のスレーブアドレス情報と(タイミング Τ902)引き続!/、て送信されてくる R/Wビットを受 信した時点(1バイト受信)でクロックストレッチを設定し、受信した 1バイトに含まれるス レーブアドレス情報と R/Wビット情報を解析し、スレーブアドレスが自装置のアドレスと 一致しかつ R/Wビットの値力 "l"であることから、マスター装置 500からのスレーブ装 置 900に対するデータ送信要求であると判定する(タイミング T903)。そして、データ 記憶部 910から最初の送信データであるデータ 1を読み出した後に (タイミング T904)、 ァクノリッジ Αを送信してクロックストレッチを解除し (タイミング Τ905)、読み出したデー タ 1の送信を開始する (タイミング Τ906)。この例では、スレーブ装置 900の内部メモリで あるデータ記憶部 910からのデータ読み出しに時間を要し (タイミング Τ904)、データ 信号 SDA801の確定時間 t およびクロックストレッチ時間 t が大きな値となってい [0018] FIG. 11 is a signal timing overview of the prior art data transmission control. The first byte is transmitted from the master device 500 to the slave device 900 configured in the prior art via the I2C interface. On the other hand, the signal timing relationship until the slave device 900 starts to transmit data 1 as the first transmission data to the master device 500 is conceptually shown. Composed of prior art, slave device 900 is generated by master device 500 After the start condition S is detected (timing T901), the 7-bit slave address information sent from the master device 500 and the R / W bit sent in (! (1 byte reception) sets the clock stretch, analyzes the slave address information and R / W bit information contained in the received 1 byte, and the slave address matches the address of its own device and the value of the R / W bit Since it is “l”, it is determined that the request is a data transmission request from the master device 500 to the slave device 900 (timing T903). Then, after reading data 1 which is the first transmission data from the data storage unit 910 (timing T904), transmit acknowledge Α to release clock stretch (timing Τ 905) and start transmission of the read data 1 (Timing Τ906). In this example, it takes time to read data from the data storage unit 910, which is the internal memory of the slave device 900 (timing Τ904), and the confirmation time t and the clock stretch time t of the data signal SDA801 are large values.
AA Strech AA Strech
る場合を示している。 Shows the case.
図 12は従来技術のデータ送信制御装置の構成で、上記図 5の接続概念で示した スレーブ装置 900を従来技術で構成されて ヽるものとして示して 、る。 FIG. 12 shows a configuration of a data transmission control device of the prior art. The slave device 900 shown in the connection concept of FIG. 5 is shown as being configured by the prior art.
マスタ装置 500よりクロック信号線 SCL700の制御の基にデータ信号線 SDA800を 介して送信されてくる情報はバッファ 981を経由して受信レジスタ 901に入力される。 受信データ解析部 902はクロックストレッチを設定した後、受信レジスタ 901に格納され ているデータを読み込んでその内容を解析し、例えば、それがマスター装置からのデ ータ送信要求を意味する情報であれば、データ読み出し送信部 903を起動してデー タ記憶部 910に格納されているデータ列 911から最初のデータを読み出して確認応答 (ァタノリッジ)を送信し、クロックストレッチ解除後にその読み出した最初のデータを送 信する。 Information transmitted from the master device 500 via the data signal line SDA800 under the control of the clock signal line SCL700 is input to the reception register 901 via the buffer 981. After setting the clock stretch, the reception data analysis unit 902 reads the data stored in the reception register 901 and analyzes the contents. For example, it may be information indicating a data transmission request from the master device. For example, the data read transmission unit 903 is activated, the first data is read from the data string 911 stored in the data storage unit 910, an acknowledgment is transmitted, and the first data read after the clock stretch is released. Send.
以降、マスタ装置 500からの確認応答情報の受信を待ち合わせ、確認応答情報受 信後にクロックストレッチを設定した状態でデータ列 911から次に送信すべきデータを 読み出し、クロックストレッチを解除してその読み出したデータを送信する、処理をマ スター装置 500から送信終了情報 (ノンァクノリッジ)が返信されるまで繰り返す。ここで 、クロックストレッチの設定および解除はオープンドレイン回路 970を駆動することによ り行われ、データおよび確認応答情報の送信はオープンドレイン回路 980を駆動する
ことにより行われる。 After that, it waits for the receipt of the confirmation response information from the master device 500, reads the data to be transmitted next from the data string 911 with the clock stretch set after receiving the confirmation response information, releases the clock stretch and reads it The process of transmitting data is repeated until the transmission end information (non acknowledge) is returned from the master device 500. Here, setting and releasing of clock stretching is performed by driving the open drain circuit 970, and transmission of data and acknowledgment information drives the open drain circuit 980. Is done.
[0020] 一方、データ読み出し送信部 903は、受信データ解析部 902から起動された時のみ 、データ記憶部 910に格納されているデータ列 911から所定の順序でデータを読み出 し、その読み出したデータを受信データ解析部 902に引き渡す。 On the other hand, only when activated by the received data analysis unit 902, the data read transmission unit 903 reads data in a predetermined order from the data sequence 911 stored in the data storage unit 910 and reads the data. The data is transferred to the received data analysis unit 902.
このように、従来技術のデータ送信制御では、クロックストレッチの状態でデータ記 憶部 910からデータ読み出した後にその読み出したデータをデータ信号線 SDA800 へ出力する構成になっており、データ信号線 SDA800へのデータ送出タイミングがデ ータ記憶部 910からのデータ読み出し時間に影響され、その分だけ遅延する方向に 変動していた。 As described above, the conventional data transmission control is configured to read data from the data storage unit 910 in the clock stretch state and then output the read data to the data signal line SDA800. The data transmission timing was affected by the data read time from the data storage unit 910 and fluctuated in the direction of delay.
[0021] 図 13は従来技術のデータ送信制御の動作フロー(1)で、マスター装置よりデータ 送信要求情報の 1バイト情報を受信した時点以降のスレーブ装置 900 (従来技術の送 信制御装置として構成されて!、る)のデータ送信制御の処理手順を示して ヽる。 従来技術で構成されているスレーブ装置 900は、マスター装置 500から最初の 1バイ ト目のデータを受信すると (ステップ S901)、まずクロックストレッチを設定してクロック 信号線 SCL900を" Low"に保持した後 (ステップ S902)、この受信した最初のバイトに 含まれるスレーブアドレスと R/Wビットの内容を解析し、スレーブアドレスが自装置アド レスと一致し R/Wビットの値力 1 "の場合は、スレーブ装置からマスター装置方向へ のデータ送信要求を意味していると判定する (ステップ S903)。そして、データ記憶部 910内の送信データ列が格納されている領域の先頭力 最初のデータを読み出した 後 (ステップ S904)、上記ステップ S901で受信した第 1バイト目の情報に対する確認応 答情報 (ァタノリッジ)をマスター装置 500へ送信した後に (ステップ S905)クロックストレ ツチを解除し (ステップ S906)、上記ステップ S904で読み出したデータをマスター装置 500へ送信する(ステップ S907)。 [0021] Fig. 13 is an operation flow (1) of the data transmission control of the prior art. The slave device 900 (configured as a transmission control device of the prior art) after the reception of 1-byte information of the data transmission request information from the master device. Demonstrate the data transmission control processing procedure. When the slave device 900 configured in the prior art receives the first byte of data from the master device 500 (step S901), the slave device 900 first sets the clock stretch and holds the clock signal line SCL900 at "Low". After (step S902), the slave address and R / W bit contents included in the first byte received are analyzed, and if the slave address matches its own device address and the R / W bit has a value of 1 ” Then, it is determined that it means a data transmission request from the slave device to the master device (step S903), and the leading force of the area storing the transmission data string in the data storage unit 910 is read out. After (step S904), after transmitting the confirmation response information (attenuation) for the first byte information received in step S901 to the master device 500 (step S905) The lock stretch is released (step S906), and the data read in step S904 is transmitted to the master device 500 (step S907).
[0022] 次に、マスター装置 500から確認応答情報 (ァタノリッジ)または送信終了情報 (ノン ァクノリッジ)が受信されるのを待ち合わせ (ステップ S908)、受信情報がァクノリッジか ノンァクノリッジかを判定し (ステップ S909)、ノンァクノリッジの場合 (YES)は処理を終 了し、ァクノリッジの場合 (NO)は次の処理を行う。 [0022] Next, it waits for the receipt of acknowledgment (information) or transmission end information (non-acknowledge) from master device 500 (step S908), and determines whether the received information is acknowledged or non-acknowledged (step S909). In case of non-acknowledge (YES), the processing is terminated, and in case of acknowledge (NO), the following processing is performed.
クロックストレッチを設定した後に (ステップ S910)、データ記憶部 910内の送信デー
タ列 91はり次に送信するデータを読み出して (ステップ S911)クロックストレッチを解除 した後(ステップ S912)読み出したデータを送信し (ステップ S913)、ステップ S908に戻 る。 After setting the clock stretch (step S910), send data in the data storage unit 910 The data to be transmitted next is read (step S911), the clock stretch is canceled (step S912), the read data is transmitted (step S913), and the process returns to step S908.
ここで、上記のデータ記憶部 910内に格納されているデータ列 911の先頭領域アド レスの決定方法にっ ヽては本動作フローには記載されて ヽな 、が、前記図 8のデー タ伝送シーケンス(2)で示したシーケンス SM05において、マスター装置 500からスレ ーブ装置 900に予め通知される。 Here, the method for determining the start area address of the data string 911 stored in the data storage unit 910 is described in this operation flow, but the data shown in FIG. In the sequence SM05 shown in the transmission sequence (2), the master device 500 notifies the slave device 900 in advance.
[0023] 図 14は従来技術のデータ送信制御の動作フロー(2)で、従来技術のデータ送信 制御装置として構成されたマスター装置が自律的にスレーブ装置に対してデータを 送信する場合のマスター装置側のデータ送信制御の処理手順を示している。 FIG. 14 is an operation flow (2) of the data transmission control of the prior art, and the master device when the master device configured as the data transmission control device of the prior art autonomously transmits data to the slave device The processing procedure of the data transmission control on the side is shown.
従来技術で構成されているマスター装置は、自装置のデータ記憶部内に記憶され ているデータ列力 データを読み取った後(S921)そのデータをスレーブ装置へ送信 し (ステップ S922)、スレーブ装置からの確認応答情報 (ァタノリッジ)の返信を待ち合 わせる (ステップ S923)。スレーブ装置から確認応答情報を受信したら、直前に送信し たデータがデータ列の最終データか否かを判定し (S924)、最終データでなければ( NO)ステップ S921に戻って次のデータ読み出しを行い、最終データの場合は (YES) 処理を終了する。このように、従来技術のデータ送信制御方法では、自律的なタイミ ングで自装置からデータを送信する場合は、まずデータ記憶部よりデータを読み出し た後にその読み出したデータを送信し、その送信したデータに対する確認応答情報 が通信相手装置力も返送されるのを待ち合わせる。そして、この処理手順を繰り返す ことによりデータ列を送信するため、データ記憶部からのデータ読み出し処理時間の 変動によりデータ送信タイミングが変動することになり、データ列全体の送信完了時 間もかなり変動することになる。 The master device configured in the prior art reads the data string force data stored in its own data storage unit (S921) and transmits the data to the slave device (step S922). Wait for a reply of acknowledgment information (Attanoridge) (step S923). When the acknowledgment information is received from the slave device, it is determined whether or not the data transmitted immediately before is the final data of the data string (S924). If it is not the final data (NO), return to step S921 to read the next data. If it is final data (YES), the process is terminated. As described above, in the data transmission control method of the prior art, when data is transmitted from the own device by autonomous timing, the data is first read from the data storage unit, and then the read data is transmitted. Wait for the acknowledgment information for the data to be sent back to the other device. Since the data sequence is transmitted by repeating this processing procedure, the data transmission timing varies due to variations in the data read processing time from the data storage unit, and the transmission completion time of the entire data sequence also varies considerably. It will be.
[0024] 以上に述べた I2Cインターフェースによるデータ伝送技術については、非特許文献 1にその詳細が開示されて 、る。 The details of the data transmission technology using the I2C interface described above are disclosed in Non-Patent Document 1.
非特許文献 1 : 12Cバス仕様書、バージョン 2.1、 2000年 1月、 日本フィリップス社発行。 発明の開示 Non-Patent Document 1: 12C Bus Specification, Version 2.1, January 2000, published by Philips Japan. Disclosure of the invention
[0025] (発明が解決しょうとする課題)
従来の I2Cインターフェース仕様に準拠したスレーブ装置は、前記のようにクロック ストレッチを利用してデータ送信のタイミング調整を行っていた。例えば、マスター装 置からのデータ送信要求に対してスレーブ装置がデータ列を送信する際は、データ 記憶部からデータを読み出すのに時間を要するため読み出し時間の間はクロックスト レツチによりデータの伝送を一時停止させていた。このクロックストレッチ状態は 1バイ トのデータを読み出す毎に発生し、大量のデータ列の伝送の際はシステム全体のデ ータ伝送性能を低下させる要因になっていた。 [Problems to be solved by the invention] Slave devices that conform to the conventional I2C interface specifications adjust the timing of data transmission using clock stretching as described above. For example, when a slave device transmits a data string in response to a data transmission request from a master device, it takes time to read the data from the data storage unit, so that data is transmitted by a clock stretch during the read time. It was paused. This clock stretch state occurs every time one byte of data is read, and when transmitting a large amount of data string, it was a factor that deteriorated the data transmission performance of the entire system.
また、前記のような従来の I2Cインターフェースをベースにしたデータ送信制御では 、例えば、光モジュールの設計に使用されている SFP(Small Form-factor Pluggable) 仕様に適合させようとする場合などは、データ信号 SDAの確定時間 t (例えば 4.5 In the data transmission control based on the conventional I2C interface as described above, for example, when trying to conform to the SFP (Small Form-factor Pluggable) specification used in the design of the optical module, Confirmation time t of signal SDA (e.g. 4.5
AA AA
s以内)やクロックストレッチ許容時間 t (例えば 5 s以内)が非常に短い為、マスタ s) and clock stretch allowable time t (for example, within 5 s) are very short.
Strech Strech
一装置力 データを受信したらスレーブ装置は直ちにマスター装置へデータを送信 しなければならず、従来のデータ送信制御方法では対応が困難な場合がある。 本発明は、装置間でデータ到達の確認応答を取りながらデータの送受信を行う際 のデータ伝送を高速化するデータ送信制御方法及びデータ送信制御装置を提供す ることを目的とする。 One device strength When data is received, the slave device must immediately transmit data to the master device, which may be difficult to handle with the conventional data transmission control method. It is an object of the present invention to provide a data transmission control method and a data transmission control device for speeding up data transmission when data is transmitted and received while receiving acknowledgment of data arrival between devices.
(課題を解決するための手段) (Means for solving problems)
[0026] 本発明は、データ記憶部に格納されているデータ列力 所定の順序でデータを読 み出し、通信相手装置力ものデータ到達の確認応答を取りながらデータの送信を制 御する方法において、予め前記データ記憶部から送信するデータを読み出して送信 レジスタへ格納し、データ送信タイミング検出時に前記送信レジスタに格納されて ヽ るデータを送信する、ように構成した。 [0026] The present invention relates to a method for controlling data transmission while reading data in a predetermined order and storing data in a data storage unit and receiving a confirmation response for data arrival as much as the communication partner device. The data to be transmitted is previously read from the data storage unit and stored in the transmission register, and the data stored in the transmission register is transmitted when the data transmission timing is detected.
これにより、データの送信タイミング検出時点にはすでに送信レジスタに次に送信 すべきデータが格納されており、送信レジスタカゝらデータ信号線へ送信スィッチを切 り替えるだけの処理時間でデータを送出することができ、データ送信タイミングの遅 延を最小限に抑えることができる。 As a result, the data to be transmitted next is already stored in the transmission register when the data transmission timing is detected, and the data is transmitted in a processing time sufficient to switch the transmission switch from the transmission register to the data signal line. And delay of data transmission timing can be minimized.
[0027] また本発明は、前記データ送信タイミングは通信相手装置からのデータ送信要求 情報受信時、 自装置からの自律的なデータ送信要求発生時、および通信相手装置
からのデータ到達の確認応答情報受信時の 、ずれかである、ように構成することもで きる。 [0027] Further, according to the present invention, the data transmission timing is determined when data transmission request information is received from a communication partner device, when an autonomous data transmission request is generated from the device, and the communication partner device. It is also possible to configure so that it is a deviation when receiving acknowledgment information of data arrival from.
これにより、データを送信する条件として考えられる全ての場合を網羅した形でデ ータ送信のタイミング遅延を抑制でき、装置全体のデータ送信の高速ィ匕を図ることが できる。 As a result, the data transmission timing delay can be suppressed in a manner that covers all possible cases for data transmission conditions, and high-speed data transmission of the entire apparatus can be achieved.
[0028] 本発明はさらに、 I2Cシリアルインターフェースの通信プロトコルに準拠してデータ 送信およびデータ到達の確認応答を行う、ように構成することができる。 [0028] The present invention can be further configured to perform data transmission and data arrival confirmation response in accordance with the communication protocol of the I2C serial interface.
これによれば、 I2Cシリアルインターフェースの通信プロトコルに準拠した形で、様々 の装置間の接続に汎用的に対応しながらデータ送信の高速ィ匕を図ることができる。 According to this, high-speed data transmission can be achieved while generally supporting connection between various devices in a form compliant with the communication protocol of the I2C serial interface.
[0029] (発明の効果) [0029] (Effect of the invention)
装置間でデータの確認応答を取りながらデータを伝送する際に、次に送信すべき データを送信タイミング検出前に予めデータ記憶部力 読み出して送信レジスタに格 納しておくことにより、送信タイミング検出時点では送信レジスタに格納されているデ ータを直ちにデータ信号線へ出力することができ、データ伝送の高速ィ匕を図ることが できる。 When transmitting data while receiving a data confirmation response between devices, the data to be transmitted next is read in advance and stored in the transmission register before the transmission timing is detected. At this time, the data stored in the transmission register can be immediately output to the data signal line, and high-speed data transmission can be achieved.
図面の簡単な説明 Brief Description of Drawings
[0030] [図 1]本発明のデータ送信制御装置の構成 [0030] [Fig. 1] Configuration of data transmission control device of the present invention
[図 2]本発明のデータ送信制御の動作フロー(1) [Fig. 2] Operation flow of data transmission control of the present invention (1)
[図 3]本発明のデータ送信制御の動作フロー(2) [Fig. 3] Operation flow of data transmission control of the present invention (2)
[図 4]本発明のデータ送信制御の信号タイミング概要 [Fig. 4] Outline of signal timing for data transmission control of the present invention
[図 5]データ伝送のための装置間の接続概念 [Fig.5] Connection concept between devices for data transmission
[図 6]データ伝送のための装置間の信号接続概念 [Figure 6] Concept of signal connection between devices for data transmission
[図 7]データ送受信シーケンス(1) [Figure 7] Data transmission / reception sequence (1)
[図 8]データ送受信シーケンス (2) [Figure 8] Data transmission / reception sequence (2)
[図 9]データ伝送時の信号タイミング(1) [Figure 9] Signal timing during data transmission (1)
[図 10]データ伝送情報の信号タイミング (2) [Figure 10] Signal timing of data transmission information (2)
[図 11]従来技術のデータ送信制御の信号タイミング概要 [Figure 11] Overview of signal timing for data transmission control in the prior art
[図 12]従来技術のデータ送信制御装置の構成
[図 13]従来技術のデータ送信制御の動作フロー(1) [Fig.12] Configuration of prior art data transmission control device [Fig.13] Operation flow of conventional data transmission control (1)
[図 14]従来技術のデータ送信制御の動作フロー(2) [Fig.14] Operation flow of data transmission control in the prior art (2)
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
(実施例) (Example)
図 1は本発明のデータ送信制御装置の構成で、ここでは前記図 5の接続概念で示 したスレーブ装置 100が本発明のデータ送信制御装置として構成されている場合の 例を示している。 FIG. 1 shows the configuration of the data transmission control device of the present invention. Here, an example is shown in which the slave device 100 shown in the connection concept of FIG. 5 is configured as the data transmission control device of the present invention.
本発明のデータ送信制御装置では、まずデータ読み出し部 103はデータ記憶部 110内に格納されて!、るデータ列 111からデータを読み出して送信レジスタ 104に格納 し、その旨を受信データ解析部 102に通知する。 In the data transmission control apparatus according to the present invention, first, the data reading unit 103 is stored in the data storage unit 110!, And the data is read from the data string 111 and stored in the transmission register 104. Notify
一方、マスター装置 500よりデータ信号線 SDA800を介して送信されてくる情報はバ ッファ 181を経由して受信レジスタ 101に入力され、受信データ解析部 102は受信レジ スタ 101に格納されているデータを読み込んでクロックストレッチを設定した後その内 容を解析し、それがマスター装置からのデータ送信要求情報の場合は確認応答情 報(ァタノリッジ)を返信した後クロックストレッチを解除する。クロックストレッチの設定 および解除はクロック信号線 SCL700のオープンドレイン回路 170を駆動することによ り行う。 On the other hand, information transmitted from the master device 500 via the data signal line SDA800 is input to the reception register 101 via the buffer 181, and the reception data analysis unit 102 receives the data stored in the reception register 101. After reading and setting the clock stretch, analyze the contents, and if it is the data transmission request information from the master device, return the confirmation response information (analog) and then cancel the clock stretch. Clock stretch is set and released by driving the open drain circuit 170 of the clock signal line SCL700.
その後送信スィッチ 105を ONにし、送信レジスタに格納されているデータをオーブ ンドレイン回路 180に出力してデータ信号線 SDA800にシリアル信号として送信する と同時に、データ読み出し部 103を起動してデータ記憶部 110からの次のデータの読 み出し処理を開始する。 Thereafter, the transmission switch 105 is turned ON, and the data stored in the transmission register is output to the open drain circuit 180 and transmitted as a serial signal to the data signal line SDA800. At the same time, the data reading unit 103 is activated and the data storage unit 110 is activated. Start reading the next data from.
一方、受信データ解析部 102は上記で起動したデータ読み出し部 103の次のデータ 読み出し処理と並行してマスター装置からの確認応答情報 (ァタノリッジ)の受信を待 ち合わせ、確認応答情報を受信した時点でデータ読み出し部 103からの次のデータ 読み出し完了の通知がきていれば送信スィッチ 105を ONにして送信レジスタに格納 されているデータをマスター装置へ送信する。この時点では、次のデータ読み出し処 理は先行して実施されているため、通常は送信レジスタ 104には既に次に送信すベ きデータが格納されており、送信スィッチ 105を ONにする処理のみで直ちに送信レジ
スタに格納されているデータがマスター装置へ送信される。ここで、確認応答情報を 受信した力否かの判定処理の間は実際はクロックストレッチを設定する場合があるが 、メモリからのデータ読み出し時間に比べると無視できる時間であるため、本発明の 本質には影響しない。 On the other hand, the reception data analysis unit 102 waits for receipt of confirmation response information (atanridge) from the master device in parallel with the next data read processing of the data read unit 103 activated above, and when the confirmation response information is received. When the next data reading completion notification is received from the data reading unit 103, the transmission switch 105 is turned ON and the data stored in the transmission register is transmitted to the master device. At this point in time, the next data read process is performed in advance, so normally the data to be transmitted next is already stored in the transmission register 104, and only the process of turning ON the transmission switch 105 is performed. Send immediately at cash register The data stored in the master is transmitted to the master device. Here, during the process of determining whether or not the response information has been received, the clock stretch may actually be set. However, since this time is negligible compared to the time for reading data from the memory, the essence of the present invention. Has no effect.
[0032] また、受信データ解析部 102はデータ読み出し部 103の次のデータ読み出し処理と 並行動作するのではなぐデータ読み出し部 103からの次のデータの読み出し完了 通知を待ち合わせ、読み出し完了通知を認知した時点でマスター装置からの確認応 答情報 (ァタノリッジ)の受信を待ち合わせるように構成してもよい。この場合でも、通 常は確認応答情報 (ァタノリッジ)の受信タイミングの方がデータ記憶部力ものデータ 読み出し完了タイミングより遅くなるため、同様にデータの送信タイミングを速めること ができる。 [0032] In addition, the received data analysis unit 102 waits for a next data read completion notification from the data read unit 103 that does not operate in parallel with the next data read processing of the data read unit 103, and recognizes the read completion notification. It may be configured to wait for reception of confirmation response information (atanridge) from the master device at the time. Even in this case, since the reception timing of the acknowledgment information (attenuation) is usually later than the data read completion timing of the data storage unit, the data transmission timing can be similarly accelerated.
上記の処理手順を、マスター装置からのデータ送信の終了を示す送信終了情報( ノンァクノリッジ)を受信するまで繰り返して、データ送信シーケンスを終結する。 このようにして、従来技術のようにデータ記憶部 110からデータを読み出した後にそ のデータを送信するのではなぐ通信相手装置からの応答確認情報の受信待ちの間 に並行して次に送信するデータをデータ記憶部 110から読み出して準備しておくため に、データ読み出し時間の分だけデータ送信タイミングが速くなり、データ送信の高 速ィ匕を図ることができる。 The above processing procedure is repeated until the transmission end information (non acknowledge) indicating the end of data transmission from the master device is received, and the data transmission sequence is terminated. In this way, the data is not transmitted after the data is read from the data storage unit 110 as in the prior art, but is transmitted in parallel while waiting for reception of the response confirmation information from the communication partner device. Since the data is read from the data storage unit 110 and prepared, the data transmission timing is accelerated by the data reading time, and the data transmission speed can be increased.
上記の実施例は、スレーブ装置側に本発明のデータ送信制御の構成を組み込ん だ場合で説明した力 これをマスター装置に組み込んでマスター装置からスレーブ 装置へデータ送信した場合も同様に構成することができ、データの送信相手であるス レーブ装置からの確認応答情報の受信待ちの間に次の送信データを送信レジスタ に格納しておくことにより、データ記憶部からのデータ読み出し時間分の処理スピー ドを向上させることができる。 The above-described embodiments are the same as those described in the case where the data transmission control configuration of the present invention is incorporated on the slave device side, and this configuration can be configured in the same manner when the data is transmitted from the master device to the slave device. The next transmission data is stored in the transmission register while waiting for receipt of acknowledgment information from the slave device that is the data transmission partner, so that the processing speed for the data read time from the data storage unit Can be improved.
[0033] 図 2は本発明のデータ送信制御の動作フロー(1)で、マスター装置 500からデータ 送信要求情報を受信した際のスレーブ装置 100のデータ送信制御の処理手順を示し ている。 FIG. 2 is an operation flow (1) of data transmission control according to the present invention, and shows a processing procedure of data transmission control of the slave device 100 when data transmission request information is received from the master device 500.
本発明の送信制御装置で構成されて!ヽるスレーブ装置 100は、まずデータ記憶部
110から最初に送信すべきデータを予め読み出して送信レジスタ 104に格納しておく( ステップ S 101)。 The slave device 100 configured by the transmission control device of the present invention is a data storage unit first. Data to be transmitted first from 110 is read in advance and stored in the transmission register 104 (step S 101).
次に、マスター装置 500から最初の 1バイトを受信した時点で (ステップ S102)クロック ストレッチを設定してクロック信号線 SCL700を" Low"に保持した後 (ステップ S103)、受 信した 1バイト目に格納されているスレーブアドレス情報と R/Wビットの内容を解析し、 スレーブアドレスが自装置に割り当てられて!/、るアドレスと一致し、 R/Wビットの値が,, 1 "でスレーブ装置力もマスター装置へのデータ送信要求であると判定した場合は (ス テツプ S104)、確認応答情報 (ァタノリッジ)をマスター装置 500へ送信した後 (ステップ S105)、クロックストレッチを解除し (ステップ S106)、送信スィッチ 105を ON (接続)状態 に切り替えて送信レジスタのデータをマスター装置へ送信する(ステップ 107)。ここで 、データ記憶部 110内の送信データ列 111の先頭領域アドレスについては、本動作フ ローには記述されて ヽな 、が、前記図 8のデータ伝送シーケンス (2)で示したシーケ ンス SM05においてマスター装置 500からスレーブ装置 100に予め通知される。 Next, when the first byte is received from the master device 500 (step S102), the clock stretch is set and the clock signal line SCL700 is held "Low" (step S103), and then the received first byte is received. Analyzes the stored slave address information and the contents of the R / W bit, and the slave address is the same as the address assigned to the local device! /, And the R / W bit value is, 1 " If it is determined that the request is also a data transmission request to the master device (step S104), after sending acknowledgment information (a knowledge) to the master device 500 (step S105), the clock stretch is canceled (step S106). The transmission switch 105 is switched to the ON (connected) state and the data in the transmission register is transmitted to the master device (step 107), where the first area of the transmission data string 111 in the data storage unit 110 is allocated. For less, this operation flow is described as ヽ, but are previously notified from the master device 500 to the slave device 100 in the sequence SM05 shown by the data transmission sequence of FIG. 8 (2).
次にデータ記憶部 110内のデータ列 11はり次のデータを読み出して送信レジスタ 104に格納した後 (ステップ S108)、マスター装置 500からの確認応答情報 (ァタノリツ ジ)または送信終了情報 (ノンァクノリッジ)の受信を待ち合わせ (ステップ S109)、受 信した情報がノンァクノリッジかァクノリッジかを判定し (ステップ S110)、ノンァクノリツ ジの場合は (YES)処理を終了し、そうでなくァクノリッジの場合は (NO)、送信レジスタ 104に格納されているデータを送信スィッチ 105を切り替えて送信し (ステップ SI 11)、 上記のステップ S108へ戻る。上記のステップ S110の処理では、受信したデータが確 認応答情報 (ァタノリッジ)力否かを判定する処理の間クロックストレッチを設定する場 合があるが、メモリからのデータ読み出し時間に比較すると無視できるため、本発明 の本質には影響しない。 Next, after reading the next data in the data string 11 in the data storage unit 110 and storing it in the transmission register 104 (step S108), the confirmation response information from the master device 500 (the “analog”) or the transmission end information (the non-acknowledge). Wait for reception (step S109), determine whether the received information is non-acknowledged or acknowledged (step S110), if it is non-acknowledged (YES) terminate processing, if not acknowledged (NO), send The data stored in the register 104 is transmitted by switching the transmission switch 105 (step SI11), and the process returns to step S108. In the process of step S110 above, clock stretch may be set during the process of determining whether the received data is the acknowledgment response information (attenuation), but this can be ignored compared to the data read time from the memory. Therefore, the essence of the present invention is not affected.
このように、時間を要するメモリからのデータ読み出し処理の間ではクロックストレツ チが設定されな 、ためデータ送信タイミングの遅延が最小限に抑えられ、データ送 信の高速ィ匕を図ることができる。 As described above, since the clock stretch is not set during the process of reading data from the time-consuming memory, the delay in data transmission timing can be minimized, and high-speed data transmission can be achieved.
図 3は本発明のデータ送信制御の動作フロー(2)で、本発明のデータ送信制御装 置により構成されたマスター装置 500が自律的にスレーブ装置 100に対してデータを
送信する場合のデータ送信制御の処理手順を示している。 FIG. 3 is an operation flow (2) of the data transmission control of the present invention. The master device 500 configured by the data transmission control device of the present invention autonomously sends data to the slave device 100. The processing procedure of data transmission control in the case of transmission is shown.
マスター装置 500は、自装置のデータ記憶部力 送信データを読み出した後その データを送信レジスタへ格納する(ステップ S121)。そして、送信レジスタに格納され ているデータを送信スィッチを切り替えて送信した後 (ステップ S122)、データ記憶部 力も次に送信すべきデータを読み出して送信レジスタへ格納し (ステップ S123)、直前 にスレーブ装置 100へ送信したデータに対するスレーブ装置 100からの確認応答情 報 (ァタノリッジ)の受信を待ち合わせ、確認応答情報を受信したら (ステップ S124)直 前に送信したデータが最終データ力否かを判定し (ステップ S125)、最終データでな い場合は (NO)上記のステップ S122に戻り、最終の場合は (YES)処理を終了する。こ のようにして、送信レジスタに格納されて ヽるデータを送信スィッチを切り替えるだけ の処理で行い、時間を要するデータ記憶部力 のデータ読み出し処理を、直前に送 信したデータにた!ヽする通信相手装置からの確認応答情報 (ァタノリッジ)の返送に 要する時間帯の間に行うため、確認応答情報を受信した時点では通常は既に送信 レジスタに次に送信すべきデータが格納された状態になっており、最小限の処理時 間で次のデータを送信することができる。 The master device 500 reads the transmission data of its own data storage unit and stores the data in the transmission register (step S121). After the data stored in the transmission register is transmitted by switching the transmission switch (step S122), the data storage unit also reads out the data to be transmitted next and stores it in the transmission register (step S123). Waiting for the receipt of confirmation response information from the slave device 100 for the data transmitted to the device 100, and receiving the confirmation response information (step S124), it is determined whether the data transmitted immediately before is the final data power ( In step S125), if it is not final data (NO), the process returns to step S122, and if final, (YES) processing is terminated. In this way, the data stored in the transmission register is processed by simply switching the transmission switch, and the data reading process of the data storage unit that requires time is performed on the data transmitted immediately before. Since it is performed during the time period required for the return of acknowledgment information from the communication partner device, the data to be transmitted next is usually already stored in the transmission register when the acknowledgment information is received. The next data can be transmitted with a minimum processing time.
図 4は本発明のデータ送信制御の信号タイミング概要で、 I2Cインターフェースによ り、本発明のデータ送信制御装置として構成されているスレーブ装置 100がマスター 装置 500からデータ送信要求を受信時点から、最初の送信データであるデータ 1をマ スター装置 500へ送信開始するまでの信号タイミング関係を概念的に示している。 スレーブ装置 100は、マスター装置 500により生成されたスタート条件 Sを検出後 (タイ ミング T101)、マスター装置 500から送信されてくる 7ビットのスレーブアドレス情報を受 信し (タイミング T102)、引き続いて送信されてくる R/Wビットを受信した時点でクロック ストレッチを設定して、受信した最初の 1バイトに含まれるスレーブアドレス情報と R/W ビット情報を解析し、スレーブアドレスが自装置のアドレスと一致しかつ R/Wビットの 値力 'T'であることから、スレーブ装置 100に対するデータ送信要求であると判定する (タイミング T103)。その後スレーブ装置 100は確認応答情報 (ァタノリッジ) Aを送信し てクロックストレッチを解除した後 (タイミング T104)、送信レジスタ 104に格納されて!、る データを送信開始する (タイミング Τ105)。このように、本発明の構成では、上記のタイ
ミング T103と T104の間に従来技術では必要だったデータ記憶部 110からのデータ読 み出し処理時間が不要となり、クロックストレッチ状態の «I続時間が最小限に抑制さ れ、高速にデータ送信を行うことができる。 Fig. 4 shows the signal timing outline of the data transmission control according to the present invention. The slave device 100 configured as the data transmission control device according to the present invention receives the data transmission request from the master device 500 through the I2C interface. FIG. 2 conceptually shows the signal timing relationship until data 1 which is the transmission data of 1 starts to be transmitted to the master device 500. After detecting the start condition S generated by the master device 500 (timing T101), the slave device 100 receives the 7-bit slave address information transmitted from the master device 500 (timing T102) and subsequently transmits it. When the received R / W bit is received, the clock stretch is set and the slave address information and R / W bit information contained in the first byte received are analyzed, and the slave address matches the address of its own device. Since the value of the R / W bit is “T”, it is determined that the request is a data transmission request to the slave device 100 (timing T103). After that, the slave device 100 transmits acknowledgment information (attenuation) A to cancel clock stretching (timing T104), and then starts transmitting data stored in the transmission register 104 (timing Τ105). Thus, in the configuration of the present invention, the above tie is used. The time required to read data from the data storage unit 110, which was necessary in the prior art, between the T103 and T104 is no longer required, and the «I duration time in the clock stretch state is minimized, allowing high-speed data transmission. It can be carried out.
[0036] 以上実施例においては、装置間の通信インターフェースとして I2Cインターフェース を用いた場合を代表例として説明したが、他の通信インターフェースを用いた場合で も本発明は同様に適用できる。 In the above embodiments, the case where the I2C interface is used as a communication interface between apparatuses has been described as a representative example. However, the present invention can be similarly applied to cases where other communication interfaces are used.
また、本発明は実施例の構成の中のマスター装置、スレーブ装置のいずれにも適 用できるだけでなぐデータの到達の確認応答を行 、ながらデータ通信する任意の 装置に対しても同様に適用できる。 In addition, the present invention can be applied to both a master device and a slave device in the configuration of the embodiment, and can be similarly applied to any device that performs data communication while performing a data arrival confirmation response. .
符号の説明 Explanation of symbols
[0037] 100,200,900 スレーブ装置 [0037] 100,200,900 slave device
101 受信レジスタ 101 Receive register
102 受信データ解析部 102 Received data analysis unit
103 データ読み出し部 103 Data reading part
104 送信レジスタ 104 Transmit register
105 送信スィッチ 105 Transmission switch
110,910 データ記憶部 110,910 Data storage
111,911 データ列 111,911 data strings
170,180,570,580,970,980 オープンドレイン回路 170,180,570,580,970,980 Open drain circuit
171,181,571,581,971,981 バッファ 171,181,571,581,971,981 buffer
500 マスター装置 500 master device
600 電源電圧 600 Supply voltage
700 クロック信号線 SCL 700 Clock signal line SCL
701 クロック信号 SCL 701 Clock signal SCL
760,860 プルアップ抵抗 (Rp) 760,860 Pull-up resistor (Rp)
800 データ信号線 SDA 800 Data signal line SDA
801 データ信号 SDA 801 Data signal SDA
810 スレーブ装置側の時間軸
マスター装置側の時間軸
810 Slave device time axis Master device time axis
Claims
[1] データ記憶部に格納されているデータ列力 所定の順序でデータを読み出し、通信 相手装置からのデータ到達の確認応答を取りながらデータの送信を制御する方法に おいて、 [1] Data string power stored in the data storage unit In a method of reading data in a predetermined order and controlling the transmission of data while receiving confirmation of arrival of data from the communication partner device,
予め前記データ記憶部力 送信するデータを読み出して送信レジスタへ格納し、 データ送信タイミング検出時に前記送信レジスタに格納されて ヽるデータを送信す る、 Read the data to be transmitted in advance and store it in the transmission register, and transmit the data stored in the transmission register when the data transmission timing is detected.
ことを特徴とするデータ送信制御方法。 And a data transmission control method.
[2] 請求項 1に記載のデータ送信制御方法にお!、て、 [2] In the data transmission control method according to claim 1,!
前記データ送信タイミングは通信相手装置からのデータ送信要求情報受信時、自 装置からの自律的なデータ送信要求発生時、および通信相手装置からのデータ到 達の確認応答情報受信時の 、ずれかである、 The data transmission timing may be different when data transmission request information is received from the communication partner device, when an autonomous data transmission request is generated from the device, and when data acknowledgment response information is received from the communication partner device. is there,
ことを特徴とするデータ送信制御方法。 And a data transmission control method.
[3] 請求項 1に記載のデータ送信制御方法にお!、て、 [3] In the data transmission control method according to claim 1,!
I2Cシリアルインターフェースの通信プロトコルに準拠してデータ送信およびデータ 到達の確認応答を行う、 In accordance with the communication protocol of the I2C serial interface, send data and confirm the arrival of data.
ことを特徴とするデータ送信制御方法。 And a data transmission control method.
[4] 送信するデータ列を格納するデータ記憶部と、 [4] a data storage unit for storing a data string to be transmitted;
通信相手装置との間でデータ到達の確認応答を取りながらデータを送信する手段 予め前記データ記憶部から送信するデータを読み出す手段と、 Means for transmitting data while taking a data arrival confirmation response with the communication partner device; means for reading data to be transmitted from the data storage unit in advance;
前記読み出したデータを格納する送信レジスタと、 A transmission register for storing the read data;
データ送信タイミング検出時に前記送信レジスタに格納されて ヽるデータを送信す る手段を備える、 Means for transmitting data stored in the transmission register when detecting data transmission timing;
ことを特徴とするデータ送信制御装置。 A data transmission control device.
[5] 請求項 4に記載のデータ送信制御装置にお 、て、 [5] In the data transmission control device according to claim 4,
前記データ送信タイミングは通信相手装置からのデータ送信要求情報受信時、自 装置からの自律的なデータ送信要求発生時、及び通信相手装置からのデータ到達
の確認応答情報受信時の 、ずれかである、 The data transmission timing is determined when data transmission request information is received from the communication partner device, when an autonomous data transmission request is generated from the own device, and when data arrives from the communication partner device. It is a gap when receiving confirmation response information.
ことを特徴とするデータ送信制御装置。 A data transmission control device.
請求項 4に記載のデータ送信制御装置において、 In the data transmission control device according to claim 4,
I2Cシリアルインターフェースの通信プロトコルに準拠してデータ送信およびデ 到達の確認応答を行う、 In accordance with the communication protocol of the I2C serial interface, data transmission and de-acknowledgment confirmation are performed.
ことを特徴とするデータ送信制御装置。
A data transmission control device.
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JPWO2006090473A1 (en) | 2008-07-24 |
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