WO2006090473A1

WO2006090473A1 - Data transmission control method and data transmission control apparatus

Info

Publication number: WO2006090473A1
Application number: PCT/JP2005/003204
Authority: WO
Inventors: Shuichi Yasuda
Original assignee: Fujitsu Limited
Priority date: 2005-02-25
Filing date: 2005-02-25
Publication date: 2006-08-31
Also published as: JP4801658B2; JPWO2006090473A1

Abstract

[PROBLEMS] In a conventional technique of transmitting data with an acknowledgement of arrival of the data being received, a reading of the data from a data storing part (memory) and a transmission of the read data were performed in a sequential processing order. For example, in a data transmission based on I2C interface specification, during a time-consuming reading of data from the memory, the clock signal was held to temporarily halt the data transmission, thereby establishing a timing adjustment. This temporal halt would occur every one-byte of transmission, causing a reduction in the data transfer rate. [MEANS FOR SOLVING PROBLEMS] A standby time or the like during reception of an acknowledgement is utilized to read data from the data storing part and then store the data into a transmission register in advance. Upon detection of a transmission timing, the data stored in the transmission register is transmitted, thereby raising the speed of the data transmission process.

Description

Specification

Data transmission control method and data transmission control device

Technical field

TECHNICAL FIELD [0001] The present invention relates to a data transmission technique, and more particularly to a data transmission method for high-speed data transmission when data is transmitted between devices while receiving a response to confirm the arrival of data with a communication partner device. The present invention relates to a data transmission control method and a data transmission control device.

Background art

[0002] There are various methods for transmitting data between devices. As a method for transmitting data through a serial interface, the I2C interface proposed by Philips is known.

[0003] Fig. 5 shows a concept of connection between devices for data transmission, and conceptually shows an example of connection between devices using the I2C interface.

The I2C interface uses a master signal 500 and a plurality of slave devices 100, 200 using two types of signal lines: clock signal line SCL (Serial Clock Line) 700 and data signal line SDA (Serial Data Line) 800. , Can transmit data between 900. Figure 5 shows the case where there are three slave devices. A slave device is assigned a 7-bit slave address, and any number of slave devices within the range represented by the slave address can be connected.

[0004] The clock signal line SCL700 is a signal power line for outputting the clock signal. When the clock signal line SCL is set to "Low" in the slave device, the master device is connected to the clock signal line SCL700. Pause output. This state is called “clock stretch”. The data signal line SDA800 is a signal line for sending and receiving data between the master device and the slave device. The clock signal line SCL700 and the data signal line SDA800 are supplied via the pull-up resistors (Rp) 760 and 860, respectively. Connected to (VDD) 600!

[0005] FIG. 6 is a conceptual diagram of signal line connection between devices for data transmission, and conceptually shows an example of signal line connection between a master device and a slave device using an I2C interface. The Here, the connection between slave device 100 and master device 500 shown in the connection concept between devices in FIG. 5 is shown as an example.

Both the clock signal line SCL700 and the data signal line SDA800 are configured to be capable of bidirectional communication with open drain drive, and the slave device 100 includes open drain circuits 170 and 180 and corresponding reception buffers 171 and 181. A data storage unit 110 for storing a data string 111 to be transmitted / received is provided.

Similarly, the master device 500 includes open drain circuits 570 and 580 and reception buffers 571 and 581 corresponding to the clock signal line SCL700 and the data signal line SDA800. Here, the description of the data storage unit of the master device 500 is omitted.

FIG. 7 shows a data transmission sequence (1), which is a sequence example when data is transmitted from the master device to the slave device through the I2C interface. A case where a data string (data 1 1 data n) is transmitted from the master device 500 to the slave device 100 shown in the connection concept between the devices in FIG. 5 is shown as a representative example.

[0007] The data transmission timing viewed from the master device 500 side is shown along the time axis 850, and the data transmission timing viewed from the slave device 100 side force is shown along the time axis 810. Master device 500 first generates start condition S, which is a condition for starting data transmission (sequence MS01), and then the slave device address (slave address: 7 bits) and data as the first byte data. Indicates the transmission direction of

Transmit R / W (Read / Write) bit (1 bit) (sequence MS02, MS03). In the example of FIG. 7, since the data transmission direction is transmission, that is, “Write” as seen from the master device, the value of the R / W bit is set to the bit value “0” meaning “Write”. The slave device 100 collates the slave address assigned to the own device with the slave address information transmitted from the master device card. If they match, the acknowledge signal A, which is confirmation response information, is returned to the master device. (Sequence MS04). In the I2C interface, acknowledge signal means to set the data signal line SDA to "Low".

[0008] Next, master device 500 transmits a memory address indicating the address of the data storage area in data storage unit 110 of slave device 100 (sequence MS05), and after receiving an acknowledge (sequence MS06), master device 500 Data storage capacity in device 500 Data 1 that is the first data is transmitted (sequence MS07). Then, if the response to that is returned (sequence MS08), the data is sequentially transmitted in the same manner as V, then the last data n is transmitted (sequence MS09), and the acknowledgment A for that is sent. After receiving (sequence MS10), a stop condition P is generated (sequence MS11), and the data transmission sequence is terminated. In the example of the above transmission sequence, immediately before transmitting a data string (data 1 1 data n), it is a sequence that transmits the memory address of the data storage area of the slave device 100 that stores the data string. It is specially specified for the I2C interface!

FIG. 8 shows a data transmission sequence (2), which is a sequence example when data is transmitted from the slave device to the master device through the I2C interface. A case where a data string (data 1 1 data n) is transmitted from the slave device 100 to the master device 500 shown in the connection concept between the devices in FIG. 5 will be shown as a representative example.

[0010] The data transmission timing as viewed from the master device 500 side is shown along the time axis 850, and the data transmission timing as viewed from the slave device 100 side is shown along the time axis 810. The master device 500 first generates a start condition S, which is a condition for starting data transmission (sequence SM01), then slave device address information (slave address: 7 bits) and information to be transmitted next (memory) R / W (Read / Write) bit (1 bit) indicating the transmission direction of (address) is transmitted (sequence SM02, SM03). In the example of FIG. 8, the transmission direction of the “memory address” information is transmission, that is, “Write” as seen from the master device, so the bit value “0” meaning “Write” is set. Slave device 100 collates the slave address assigned to its own device with the slave address information sent to the master device, and if they match, acknowledge A, which is acknowledgment information, is returned to the master device (sequence SM04). ) Next, the master device 500 transmits “memory address” information, which is the address of the data storage area in the data storage unit 110 of the slave device 100 (sequence MS05), and receives the acknowledge A corresponding thereto (sequence SM06).

[0011] Subsequently, the master device 500 again generates a start condition S (sequence SM07), and the slave device 100 to the master device 500 as the transmission direction of slave address information (7 bits) of the same slave device 100 and the next data. Send R / W bit information ("1") indicating the direction to (Sequence SM08, SM09) After receiving acknowledgment A, which is acknowledgment information (sequence SM10), it waits for data to be transmitted from slave device 100.

On the other hand, the slave device 100 having received the R / W bit of “Γ”, which means the slave address information and the data transmission to the master device in the sequence SM08, SM09, is stored in the data storage unit 110. Data area force indicated by “memory address” specified in sequence SM05 above Reads data 1 as the first data and transmits it to master device 500 (sequence SM11). Acknowledge A which is confirmation response information of master device strength is returned. Waits for it (sequence SM12). Thereafter, the data is sequentially read from the data storage unit 110 and transmitted to the master device 500 in the same procedure. After the data n which is the last data is transmitted (sequence SM13, SM14), the master device 500 transmits the transmission end information. Returns a non-notification NA, then generates a stop condition (sequence SM15) and terminates the data transmission sequence.

[0013] The data transmitted from the master device to the slave device in the above-described sequences SM08 and SM09, that is, the slave address information (7 bits), the value, and the R / W bit of T, are transmitted from the slave device to the master device. Since this means a data transmission request, this data is also referred to as a “data transmission request” in the following description.

In addition, the “memory address” shown in the data transmission sequence (2) in FIG. 8 above is specified in particular for the I2C interface!

[0014] Figure 9 shows the signal timing (1) during data transmission. The clock signal SCL701 and the data signal SDA801 are generated during the generation of the start condition, the transmission of the data bit, and the generation of the stop condition by the I2C interface. Show time relationship.

The start condition C01 is a state in which the data signal SDA 801 changes from “High” to “Low” while the clock signal SCL701 is in the “High” state, which means the start of data transmission. In the I2C interface, t indicates the setup time of start condition C01 and start

SU.STA

Each minimum value of t indicating the hold time of condition C01 is specified! Speak.

HD.STA

[0015] During data bit transmission, the state of the data signal SDA 801 must be constant while the clock signal SCL701 is "High", and the data signal SDA801 is between "High" and "Low". The state can be changed only when the clock signal SCL701 is "Low", and the data signal SD A801 is sampled at the rising edge of the clock signal SCL701. In the I2C interface, the setup time t of the data signal SDA801 and the hold of the data signal SDA801

SU.DAT

Time t, low signal pulse width t of clock signal SCL701, and clock signal SCL

HD.DAT LOW

The minimum value of each 701 High signal pulse width t is specified.

HIGH

[0016] The stop condition C02 is the data signal SDA while the clock signal SCL701 is "High".

The state in which 801 changes from “Low” to “High” means the end of data transmission. In the I2C interface, the setup time t of the stop condition C02 and the stop condition

SU.STO

The minimum value of the interval t between C02 and the next start condition C03 is specified.

BUF

[0017] Figure 10 shows the signal timing (2) during data transmission. The time relationship between the fixed time t of the data signal SDA801 and the allowable clock stretch time t in the I2C interface.

AA Strech

Show.

As shown in the signal timing (1) during data transmission in FIG. 9, the data signal SDA 801 is sampled at the rising edge of the clock signal SCL701. For this reason, for example, when data is transmitted to the slave device master device, it takes time to read data from the data storage unit of the slave device, and the determination time t of the data signal SDA801 increases,

AA

As a result, the output of the data signal SDA801 may be delayed. In such a case, it is possible to prevent the data signal SDA801 from being sampled by clock stretching, that is, by holding the clock signal SCL801 in the “Low” state on the slave device side. The confirmation time t of the signal SDA801 can be extended. Figure 10

AA

Signal timing (2) during data transmission indicates such a situation. In the I2C interface, the data signal SDA801 has a fixed time t and a clock stretch allowable time t.

AA Strech

The upper limit is specified for V!

[0018] FIG. 11 is a signal timing overview of the prior art data transmission control. The first byte is transmitted from the master device 500 to the slave device 900 configured in the prior art via the I2C interface. On the other hand, the signal timing relationship until the slave device 900 starts to transmit data 1 as the first transmission data to the master device 500 is conceptually shown. Composed of prior art, slave device 900 is generated by master device 500 After the start condition S is detected (timing T901), the 7-bit slave address information sent from the master device 500 and the R / W bit sent in (! (1 byte reception) sets the clock stretch, analyzes the slave address information and R / W bit information contained in the received 1 byte, and the slave address matches the address of its own device and the value of the R / W bit Since it is “l”, it is determined that the request is a data transmission request from the master device 500 to the slave device 900 (timing T903). Then, after reading data 1 which is the first transmission data from the data storage unit 910 (timing T904), transmit acknowledge Α to release clock stretch (timing Τ 905) and start transmission of the read data 1 (Timing Τ906). In this example, it takes time to read data from the data storage unit 910, which is the internal memory of the slave device 900 (timing Τ904), and the confirmation time t and the clock stretch time t of the data signal SDA801 are large values.

AA Strech

Shows the case.

FIG. 12 shows a configuration of a data transmission control device of the prior art. The slave device 900 shown in the connection concept of FIG. 5 is shown as being configured by the prior art.

Information transmitted from the master device 500 via the data signal line SDA800 under the control of the clock signal line SCL700 is input to the reception register 901 via the buffer 981. After setting the clock stretch, the reception data analysis unit 902 reads the data stored in the reception register 901 and analyzes the contents. For example, it may be information indicating a data transmission request from the master device. For example, the data read transmission unit 903 is activated, the first data is read from the data string 911 stored in the data storage unit 910, an acknowledgment is transmitted, and the first data read after the clock stretch is released. Send.

After that, it waits for the receipt of the confirmation response information from the master device 500, reads the data to be transmitted next from the data string 911 with the clock stretch set after receiving the confirmation response information, releases the clock stretch and reads it The process of transmitting data is repeated until the transmission end information (non acknowledge) is returned from the master device 500. Here, setting and releasing of clock stretching is performed by driving the open drain circuit 970, and transmission of data and acknowledgment information drives the open drain circuit 980. Is done.

On the other hand, only when activated by the received data analysis unit 902, the data read transmission unit 903 reads data in a predetermined order from the data sequence 911 stored in the data storage unit 910 and reads the data. The data is transferred to the received data analysis unit 902.

As described above, the conventional data transmission control is configured to read data from the data storage unit 910 in the clock stretch state and then output the read data to the data signal line SDA800. The data transmission timing was affected by the data read time from the data storage unit 910 and fluctuated in the direction of delay.

[0021] Fig. 13 is an operation flow (1) of the data transmission control of the prior art. The slave device 900 (configured as a transmission control device of the prior art) after the reception of 1-byte information of the data transmission request information from the master device. Demonstrate the data transmission control processing procedure. When the slave device 900 configured in the prior art receives the first byte of data from the master device 500 (step S901), the slave device 900 first sets the clock stretch and holds the clock signal line SCL900 at "Low". After (step S902), the slave address and R / W bit contents included in the first byte received are analyzed, and if the slave address matches its own device address and the R / W bit has a value of 1 ” Then, it is determined that it means a data transmission request from the slave device to the master device (step S903), and the leading force of the area storing the transmission data string in the data storage unit 910 is read out. After (step S904), after transmitting the confirmation response information (attenuation) for the first byte information received in step S901 to the master device 500 (step S905) The lock stretch is released (step S906), and the data read in step S904 is transmitted to the master device 500 (step S907).

[0022] Next, it waits for the receipt of acknowledgment (information) or transmission end information (non-acknowledge) from master device 500 (step S908), and determines whether the received information is acknowledged or non-acknowledged (step S909). In case of non-acknowledge (YES), the processing is terminated, and in case of acknowledge (NO), the following processing is performed.

After setting the clock stretch (step S910), send data in the data storage unit 910 The data to be transmitted next is read (step S911), the clock stretch is canceled (step S912), the read data is transmitted (step S913), and the process returns to step S908.

Here, the method for determining the start area address of the data string 911 stored in the data storage unit 910 is described in this operation flow, but the data shown in FIG. In the sequence SM05 shown in the transmission sequence (2), the master device 500 notifies the slave device 900 in advance.

FIG. 14 is an operation flow (2) of the data transmission control of the prior art, and the master device when the master device configured as the data transmission control device of the prior art autonomously transmits data to the slave device The processing procedure of the data transmission control on the side is shown.

The master device configured in the prior art reads the data string force data stored in its own data storage unit (S921) and transmits the data to the slave device (step S922). Wait for a reply of acknowledgment information (Attanoridge) (step S923). When the acknowledgment information is received from the slave device, it is determined whether or not the data transmitted immediately before is the final data of the data string (S924). If it is not the final data (NO), return to step S921 to read the next data. If it is final data (YES), the process is terminated. As described above, in the data transmission control method of the prior art, when data is transmitted from the own device by autonomous timing, the data is first read from the data storage unit, and then the read data is transmitted. Wait for the acknowledgment information for the data to be sent back to the other device. Since the data sequence is transmitted by repeating this processing procedure, the data transmission timing varies due to variations in the data read processing time from the data storage unit, and the transmission completion time of the entire data sequence also varies considerably. It will be.

The details of the data transmission technology using the I2C interface described above are disclosed in Non-Patent Document 1.

Non-Patent Document 1: 12C Bus Specification, Version 2.1, January 2000, published by Philips Japan. Disclosure of the invention

[Problems to be solved by the invention] Slave devices that conform to the conventional I2C interface specifications adjust the timing of data transmission using clock stretching as described above. For example, when a slave device transmits a data string in response to a data transmission request from a master device, it takes time to read the data from the data storage unit, so that data is transmitted by a clock stretch during the read time. It was paused. This clock stretch state occurs every time one byte of data is read, and when transmitting a large amount of data string, it was a factor that deteriorated the data transmission performance of the entire system.

In the data transmission control based on the conventional I2C interface as described above, for example, when trying to conform to the SFP (Small Form-factor Pluggable) specification used in the design of the optical module, Confirmation time t of signal SDA (e.g. 4.5

AA

s) and clock stretch allowable time t (for example, within 5 s) are very short.

Strech

One device strength When data is received, the slave device must immediately transmit data to the master device, which may be difficult to handle with the conventional data transmission control method. It is an object of the present invention to provide a data transmission control method and a data transmission control device for speeding up data transmission when data is transmitted and received while receiving acknowledgment of data arrival between devices.

(Means for solving problems)

[0026] The present invention relates to a method for controlling data transmission while reading data in a predetermined order and storing data in a data storage unit and receiving a confirmation response for data arrival as much as the communication partner device. The data to be transmitted is previously read from the data storage unit and stored in the transmission register, and the data stored in the transmission register is transmitted when the data transmission timing is detected.

As a result, the data to be transmitted next is already stored in the transmission register when the data transmission timing is detected, and the data is transmitted in a processing time sufficient to switch the transmission switch from the transmission register to the data signal line. And delay of data transmission timing can be minimized.

[0027] Further, according to the present invention, the data transmission timing is determined when data transmission request information is received from a communication partner device, when an autonomous data transmission request is generated from the device, and the communication partner device. It is also possible to configure so that it is a deviation when receiving acknowledgment information of data arrival from.

As a result, the data transmission timing delay can be suppressed in a manner that covers all possible cases for data transmission conditions, and high-speed data transmission of the entire apparatus can be achieved.

[0028] The present invention can be further configured to perform data transmission and data arrival confirmation response in accordance with the communication protocol of the I2C serial interface.

According to this, high-speed data transmission can be achieved while generally supporting connection between various devices in a form compliant with the communication protocol of the I2C serial interface.

[0029] (Effect of the invention)

When transmitting data while receiving a data confirmation response between devices, the data to be transmitted next is read in advance and stored in the transmission register before the transmission timing is detected. At this time, the data stored in the transmission register can be immediately output to the data signal line, and high-speed data transmission can be achieved.

Brief Description of Drawings

[0030] [Fig. 1] Configuration of data transmission control device of the present invention

[Fig. 2] Operation flow of data transmission control of the present invention (1)

[Fig. 3] Operation flow of data transmission control of the present invention (2)

[Fig. 4] Outline of signal timing for data transmission control of the present invention

[Fig.5] Connection concept between devices for data transmission

[Figure 6] Concept of signal connection between devices for data transmission

[Figure 7] Data transmission / reception sequence (1)

[Figure 8] Data transmission / reception sequence (2)

[Figure 9] Signal timing during data transmission (1)

[Figure 10] Signal timing of data transmission information (2)

[Figure 11] Overview of signal timing for data transmission control in the prior art

[Fig.12] Configuration of prior art data transmission control device [Fig.13] Operation flow of conventional data transmission control (1)

[Fig.14] Operation flow of data transmission control in the prior art (2)

BEST MODE FOR CARRYING OUT THE INVENTION

(Example)

FIG. 1 shows the configuration of the data transmission control device of the present invention. Here, an example is shown in which the slave device 100 shown in the connection concept of FIG. 5 is configured as the data transmission control device of the present invention.

In the data transmission control apparatus according to the present invention, first, the data reading unit 103 is stored in the data storage unit 110!, And the data is read from the data string 111 and stored in the transmission register 104. Notify

On the other hand, information transmitted from the master device 500 via the data signal line SDA800 is input to the reception register 101 via the buffer 181, and the reception data analysis unit 102 receives the data stored in the reception register 101. After reading and setting the clock stretch, analyze the contents, and if it is the data transmission request information from the master device, return the confirmation response information (analog) and then cancel the clock stretch. Clock stretch is set and released by driving the open drain circuit 170 of the clock signal line SCL700.

Thereafter, the transmission switch 105 is turned ON, and the data stored in the transmission register is output to the open drain circuit 180 and transmitted as a serial signal to the data signal line SDA800. At the same time, the data reading unit 103 is activated and the data storage unit 110 is activated. Start reading the next data from.

On the other hand, the reception data analysis unit 102 waits for receipt of confirmation response information (atanridge) from the master device in parallel with the next data read processing of the data read unit 103 activated above, and when the confirmation response information is received. When the next data reading completion notification is received from the data reading unit 103, the transmission switch 105 is turned ON and the data stored in the transmission register is transmitted to the master device. At this point in time, the next data read process is performed in advance, so normally the data to be transmitted next is already stored in the transmission register 104, and only the process of turning ON the transmission switch 105 is performed. Send immediately at cash register The data stored in the master is transmitted to the master device. Here, during the process of determining whether or not the response information has been received, the clock stretch may actually be set. However, since this time is negligible compared to the time for reading data from the memory, the essence of the present invention. Has no effect.

[0032] In addition, the received data analysis unit 102 waits for a next data read completion notification from the data read unit 103 that does not operate in parallel with the next data read processing of the data read unit 103, and recognizes the read completion notification. It may be configured to wait for reception of confirmation response information (atanridge) from the master device at the time. Even in this case, since the reception timing of the acknowledgment information (attenuation) is usually later than the data read completion timing of the data storage unit, the data transmission timing can be similarly accelerated.

The above processing procedure is repeated until the transmission end information (non acknowledge) indicating the end of data transmission from the master device is received, and the data transmission sequence is terminated. In this way, the data is not transmitted after the data is read from the data storage unit 110 as in the prior art, but is transmitted in parallel while waiting for reception of the response confirmation information from the communication partner device. Since the data is read from the data storage unit 110 and prepared, the data transmission timing is accelerated by the data reading time, and the data transmission speed can be increased.

The above-described embodiments are the same as those described in the case where the data transmission control configuration of the present invention is incorporated on the slave device side, and this configuration can be configured in the same manner when the data is transmitted from the master device to the slave device. The next transmission data is stored in the transmission register while waiting for receipt of acknowledgment information from the slave device that is the data transmission partner, so that the processing speed for the data read time from the data storage unit Can be improved.

FIG. 2 is an operation flow (1) of data transmission control according to the present invention, and shows a processing procedure of data transmission control of the slave device 100 when data transmission request information is received from the master device 500.

The slave device 100 configured by the transmission control device of the present invention is a data storage unit first. Data to be transmitted first from 110 is read in advance and stored in the transmission register 104 (step S 101).

Next, when the first byte is received from the master device 500 (step S102), the clock stretch is set and the clock signal line SCL700 is held "Low" (step S103), and then the received first byte is received. Analyzes the stored slave address information and the contents of the R / W bit, and the slave address is the same as the address assigned to the local device! /, And the R / W bit value is, 1 " If it is determined that the request is also a data transmission request to the master device (step S104), after sending acknowledgment information (a knowledge) to the master device 500 (step S105), the clock stretch is canceled (step S106). The transmission switch 105 is switched to the ON (connected) state and the data in the transmission register is transmitted to the master device (step 107), where the first area of the transmission data string 111 in the data storage unit 110 is allocated. For less, this operation flow is described as ヽ, but are previously notified from the master device 500 to the slave device 100 in the sequence SM05 shown by the data transmission sequence of FIG. 8 (2).

Next, after reading the next data in the data string 11 in the data storage unit 110 and storing it in the transmission register 104 (step S108), the confirmation response information from the master device 500 (the “analog”) or the transmission end information (the non-acknowledge). Wait for reception (step S109), determine whether the received information is non-acknowledged or acknowledged (step S110), if it is non-acknowledged (YES) terminate processing, if not acknowledged (NO), send The data stored in the register 104 is transmitted by switching the transmission switch 105 (step SI11), and the process returns to step S108. In the process of step S110 above, clock stretch may be set during the process of determining whether the received data is the acknowledgment response information (attenuation), but this can be ignored compared to the data read time from the memory. Therefore, the essence of the present invention is not affected.

As described above, since the clock stretch is not set during the process of reading data from the time-consuming memory, the delay in data transmission timing can be minimized, and high-speed data transmission can be achieved.

FIG. 3 is an operation flow (2) of the data transmission control of the present invention. The master device 500 configured by the data transmission control device of the present invention autonomously sends data to the slave device 100. The processing procedure of data transmission control in the case of transmission is shown.

The master device 500 reads the transmission data of its own data storage unit and stores the data in the transmission register (step S121). After the data stored in the transmission register is transmitted by switching the transmission switch (step S122), the data storage unit also reads out the data to be transmitted next and stores it in the transmission register (step S123). Waiting for the receipt of confirmation response information from the slave device 100 for the data transmitted to the device 100, and receiving the confirmation response information (step S124), it is determined whether the data transmitted immediately before is the final data power ( In step S125), if it is not final data (NO), the process returns to step S122, and if final, (YES) processing is terminated. In this way, the data stored in the transmission register is processed by simply switching the transmission switch, and the data reading process of the data storage unit that requires time is performed on the data transmitted immediately before. Since it is performed during the time period required for the return of acknowledgment information from the communication partner device, the data to be transmitted next is usually already stored in the transmission register when the acknowledgment information is received. The next data can be transmitted with a minimum processing time.

Fig. 4 shows the signal timing outline of the data transmission control according to the present invention. The slave device 100 configured as the data transmission control device according to the present invention receives the data transmission request from the master device 500 through the I2C interface. FIG. 2 conceptually shows the signal timing relationship until data 1 which is the transmission data of 1 starts to be transmitted to the master device 500. After detecting the start condition S generated by the master device 500 (timing T101), the slave device 100 receives the 7-bit slave address information transmitted from the master device 500 (timing T102) and subsequently transmits it. When the received R / W bit is received, the clock stretch is set and the slave address information and R / W bit information contained in the first byte received are analyzed, and the slave address matches the address of its own device. Since the value of the R / W bit is “T”, it is determined that the request is a data transmission request to the slave device 100 (timing T103). After that, the slave device 100 transmits acknowledgment information (attenuation) A to cancel clock stretching (timing T104), and then starts transmitting data stored in the transmission register 104 (timing Τ105). Thus, in the configuration of the present invention, the above tie is used. The time required to read data from the data storage unit 110, which was necessary in the prior art, between the T103 and T104 is no longer required, and the «I duration time in the clock stretch state is minimized, allowing high-speed data transmission. It can be carried out.

In the above embodiments, the case where the I2C interface is used as a communication interface between apparatuses has been described as a representative example. However, the present invention can be similarly applied to cases where other communication interfaces are used.

In addition, the present invention can be applied to both a master device and a slave device in the configuration of the embodiment, and can be similarly applied to any device that performs data communication while performing a data arrival confirmation response. .

Explanation of symbols

[0037] 100,200,900 slave device

101 Receive register

102 Received data analysis unit

103 Data reading part

104 Transmit register

105 Transmission switch

110,910 Data storage

111,911 data strings

170,180,570,580,970,980 Open drain circuit

171,181,571,581,971,981 buffer

500 master device

600 Supply voltage

700 Clock signal line SCL

701 Clock signal SCL

760,860 Pull-up resistor (Rp)

800 Data signal line SDA

801 Data signal SDA

810 Slave device time axis Master device time axis

Claims

The scope of the claims

[1] Data string power stored in the data storage unit In a method of reading data in a predetermined order and controlling the transmission of data while receiving confirmation of arrival of data from the communication partner device,

Read the data to be transmitted in advance and store it in the transmission register, and transmit the data stored in the transmission register when the data transmission timing is detected.

And a data transmission control method.

[2] In the data transmission control method according to claim 1,!

The data transmission timing may be different when data transmission request information is received from the communication partner device, when an autonomous data transmission request is generated from the device, and when data acknowledgment response information is received from the communication partner device. is there,

And a data transmission control method.

[3] In the data transmission control method according to claim 1,!

In accordance with the communication protocol of the I2C serial interface, send data and confirm the arrival of data.

And a data transmission control method.

[4] a data storage unit for storing a data string to be transmitted;

Means for transmitting data while taking a data arrival confirmation response with the communication partner device; means for reading data to be transmitted from the data storage unit in advance;

A transmission register for storing the read data;

Means for transmitting data stored in the transmission register when detecting data transmission timing;

A data transmission control device.

[5] In the data transmission control device according to claim 4,

The data transmission timing is determined when data transmission request information is received from the communication partner device, when an autonomous data transmission request is generated from the own device, and when data arrives from the communication partner device. It is a gap when receiving confirmation response information.

A data transmission control device.

In the data transmission control device according to claim 4,

In accordance with the communication protocol of the I2C serial interface, data transmission and de-acknowledgment confirmation are performed.

A data transmission control device.