JP4801658B2 - Data transmission control method and data transmission control device - Google Patents

Description

  The present invention relates to a data transmission technique, and in particular, a data transmission control method and data transmission for speeding up data transmission when transmitting data between devices while receiving a data arrival confirmation response with a communication partner device. The present invention relates to a control device.

  There are various methods for transmitting data between devices, and an I2C interface proposed by Philips is known as a method for transmitting data through a serial interface.

FIG. 5 shows a concept of connection between devices for data transmission, and conceptually shows an example of connection between devices using the I2C interface.
In the I2C interface, a master device 500 and a plurality of slave devices 100, 200, 900 are used by using two types of signal lines, a clock signal line SCL (Serial Clock Line) 700 and a data signal line SDA (Serial Data Line) 800. Data can be transmitted to and from. Although FIG. 5 shows a case where there are three slave devices, a 7-bit slave address is assigned to the slave device, and an arbitrary number of slave devices within the range represented by the slave address can be connected.

  The clock signal line SCL700 is a signal line for outputting a clock signal from the master device. However, when the clock signal line SCL is in a “Low” state in the slave device, the master device temporarily outputs the clock signal line SCL700. Stop. This state is called “clock stretch”. The data signal line SDA800 is a signal line for transmitting and receiving data between the master device and the slave device. The clock signal line SCL700 and the data signal line SDA800 are connected to the supply voltage (Pp VDD) 600.

FIG. 6 is a conceptual diagram of signal line connection between devices for data transmission, and conceptually shows an example of signal line connection between a master device and a slave device using an I2C interface. Here, the connection between the slave device 100 and the master device 500 shown in the connection concept between the devices in FIG. 5 is shown as an example.
Both the clock signal line SCL700 and the data signal line SDA800 are configured to be capable of bidirectional communication with open drain drive, and the slave device 100 includes open drain circuits 170 and 180 and corresponding reception buffers 171 and 181; A data storage unit 110 that stores a data string 111 to be transmitted and received is provided.
Similarly, the master device 500 includes open drain circuits 570 and 580 and reception buffers 571 and 581 corresponding to the clock signal line SCL700 and the data signal line SDA800. Here, description of the data storage unit of the master device 500 is omitted.

  FIG. 7 shows a data transmission sequence (1), which is a sequence example when data is transmitted from the master device to the slave device through the I2C interface. A case where a data string (data 1 to data n) is transmitted from the master device 500 to the slave device 100 shown in the connection concept between the devices in FIG. 5 is shown as a representative example.

The data transmission timing seen from the master device 500 side is shown along the time axis 850, and the data transmission timing seen from the slave device 100 side is shown along the time axis 810.
The master device 500 first generates a start condition S that is a condition for starting data transmission (sequence MS01), and then, as the first byte data, the address (slave address: 7 bits) and data of the slave device that is the transmission destination The R / W (Read / Write) bit (1 bit) indicating the transmission direction is transmitted (sequence MS02, MS03). In the example of FIG. 7, since the data transmission direction is transmission, that is, “Write” as seen from the master device, the value of the R / W bit is set to the bit value “0” meaning “Write”. Slave device 100 collates the slave address assigned to itself with the slave address information transmitted from the master device, and if they match, acknowledge signal A, which is acknowledgment information, is returned to the master device (sequence MS04). . In the I2C interface, the acknowledge signal means that the data signal line SDA is set to “Low”.

  Next, the master device 500 transmits a memory address indicating the address of the data storage area in the data storage unit 110 of the slave device 100 (sequence MS05), and after receiving an acknowledge (sequence MS06), Data 1 that is the first data read from the data storage unit is transmitted (sequence MS07). Then, if an acknowledgment is returned (sequence MS08), data is sequentially transmitted in the same manner, data n which is the last data is transmitted (sequence MS09), and an acknowledge A is received (sequence MS09). After the sequence MS10), a stop condition P is generated (sequence MS11), and the data transmission sequence is terminated. In the example of the transmission sequence described above, the memory address of the data storage area of the slave device 100 that stores the data string is transmitted immediately before transmitting the data string (data 1 to data n). Is not specified in the I2C interface.

  FIG. 8 shows a data transmission sequence (2), which is a sequence example when data is transmitted from the slave device to the master device through the I2C interface. A case where a data string (data 1 to data n) is transmitted from the slave device 100 to the master device 500 shown in the connection concept between the devices in FIG. 5 is shown as a representative example.

The data transmission timing seen from the master device 500 side is shown along the time axis 850, and the data transmission timing seen from the slave device 100 side is shown along the time axis 810.
The master device 500 first generates a start condition S that is a condition for starting data transmission (sequence SM01), and then slave device address information (slave address: 7 bits) and information to be transmitted next (memory address). The R / W (Read / Write) bit (1 bit) indicating the transmission direction is transmitted (sequence SM02, SM03). In the example of FIG. 8, since the transmission direction of the “memory address” information is transmission, that is, “Write” as seen from the master device, the bit value “0” meaning “Write” is set. The slave device 100 collates the slave address assigned to the own device with the slave address information transmitted from the master device. If they match, the slave device 100 returns acknowledgment A as acknowledgment information to the master device (sequence SM04). Next, the master device 500 transmits “memory address” information, which is the address of the data storage area in the data storage unit 110 of the slave device 100 (sequence MS05), and receives an acknowledge A for the information (sequence SM06).

  Subsequently, the master device 500 generates the start condition S again (sequence SM07), and means the direction from the slave device 100 to the master device 500 as the transmission direction of the slave address information (7 bits) of the same slave device 100 and the next data. R / W bit information (“1”) to be transmitted is transmitted (sequence SM08, SM09), and acknowledgment A corresponding thereto is received (sequence SM10), and then data is transmitted from slave device 100. Wait for.

  On the other hand, the slave device 100 that has received the slave address information and the R / W bit of the value “1” indicating data transmission from the slave device to the master device in the above-described sequences SM08 and SM09, the sequence in the data storage unit 110 Data 1 that is the first data is read from the data area indicated by the “memory address” specified by SM05 and transmitted to master device 500 (sequence SM11), and acknowledgment A that is confirmation response information from the master device is returned. Wait for (sequence SM12). Thereafter, the data is sequentially read from the data storage unit 110 and transmitted to the master device 500 in the same procedure. After the data n as the last data is transmitted (sequences SM13 and SM14), the master device 500 transmits the non-acknowledgement as transmission end information. NA is returned, then a stop condition is generated (sequence SM15), and the data transmission sequence is terminated.

The data transmitted from the master device to the slave device in the above-described sequences SM08 and SM09, that is, the slave address information (7 bits) and the R / W bit of the value “1” are data transmission requests from the slave device to the master device. This means that this data is also referred to as “data transmission request” in the following description.
Further, the “memory address” shown in the data transmission sequence (2) in FIG. 8 is not particularly defined in the I2C interface.

FIG. 9 is a signal timing (1) at the time of data transmission, and shows a time relationship between the clock signal SCL701 and the data signal SDA801 at the time of generation of a start condition, transmission of a data bit, and generation of a stop condition by the I2C interface. ing.
The start condition C01 is a state in which the data signal SDA801 changes from “High” to “Low” while the clock signal SCL701 is in the “High” state, which means the start of data transmission. In the I2C interface, minimum values of t _SU.STA indicating the setup time of the start condition C01 and t _HD.STA indicating the hold time of the start condition C01 are defined.

During the transmission of data bits, the state of the data signal SDA801 must be constant while the clock signal SCL701 is “High”, and the state can be changed between the “High” and “Low” of the data signal SDA801. Is limited to when the clock signal SCL701 is "Low", and the data signal SDA801 is sampled at the rising edge of the clock signal SCL701. In the I2C interface, the setup time t _{SU.DAT of} the data signal SDA801, the hold time t _HD.DAT of the data signal SDA801, the low signal pulse width t _{LOW of} the clock signal SCL701, and the high signal pulse width t _HIGH of the clock signal SCL701, respectively. The minimum value is specified.

The stop condition C02 is a state in which the data signal SDA801 changes from “Low” to “High” while the clock signal SCL701 is in the “High” state, and means the end of data transmission. In the I2C interface, the minimum value of the setup time t _{SU.STO of} the stop condition C02 and the interval t _BUF between the stop condition C02 and the next start condition C03 is defined.

FIG. 10 shows a signal timing (2) at the time of data transmission, and shows the time relationship between the fixed time t _AA of the data signal SDA801 and the clock stretch allowable time t _Strech in the I2C interface.
As shown in the signal timing (1) at the time of data transmission in FIG. 9, the data signal SDA801 is sampled at the rising edge of the clock signal SCL701. For this reason, for example, when data is transmitted from the slave device to the master device, it takes time to read data from the data storage unit of the slave device, and the determination time t _AA of the data signal SDA801 increases, and as a result, the data signal The output of SDA801 may be delayed. In such a case, sampling of the data signal SDA801 can be prevented from being performed by clock stretching, that is, by holding the clock signal SCL801 in the "Low" state on the slave device side. The determination time t _{AA of} SDA 801 can be extended. Signal timing (2) during data transmission in FIG. 10 shows such a situation. In the I2C interface, the upper limit is not defined for the fixed time t _AA of the data signal SDA801 and the clock stretch allowable time t _Strech .

FIG. 11 is an outline of signal timing of data transmission control in the prior art. In the I2C interface, the first one byte is transmitted from the master device 500 to the slave device 900 configured in the prior art, and the slave device 900 first responds. The signal timing relationship until transmission of data 1 as transmission data to the master device 500 is conceptually shown.
After detecting the start condition S generated by the master device 500 (timing T901), the slave device 900 configured in the prior art continues with the 7-bit slave address information transmitted from the master device 500 (timing T902). When the received R / W bit is received (1 byte reception), clock stretch is set, the slave address information and R / W bit information included in the received 1 byte are analyzed, and the slave address is Since the R / W bit value is “1”, it is determined that the request is a data transmission request from the master device 500 to the slave device 900 (timing T903). Then, after data 1 as the first transmission data is read from the data storage unit 910 (timing T904), the acknowledge A is transmitted to cancel the clock stretch (timing T905), and transmission of the read data 1 is started (time T904). Timing T906). In this example, it takes time to read data from the data storage unit 910 which is the internal memory of the slave device 900 (timing T904), and the fixed time t _AA and the clock stretch time t _{Strech of} the data signal SDA801 become large values. Shows the case.

FIG. 12 shows the configuration of a data transmission control device of the prior art, and shows that the slave device 900 shown in the connection concept of FIG. 5 is configured by the prior art.
Information transmitted from the master device 500 via the data signal line SDA800 under the control of the clock signal line SCL700 is input to the reception register 901 via the buffer 981. After setting the clock stretch, the reception data analysis unit 902 reads the data stored in the reception register 901 and analyzes the contents thereof.For example, if it is information indicating a data transmission request from the master device, The data read / send unit 903 is activated to read the first data from the data string 911 stored in the data storage unit 910, send an acknowledgment (acknowledge), and send the read first data after canceling the clock stretch. .
After that, it waits for the receipt of the confirmation response information from the master device 500, reads the data to be transmitted next from the data string 911 with the clock stretch set after receiving the confirmation response information, cancels the clock stretch, and reads the read data. The process is repeated until transmission end information (non-acknowledgement) is returned from the master device 500. Here, setting and canceling of the clock stretch is performed by driving the open drain circuit 970, and transmission of data and acknowledgment information is performed by driving the open drain circuit 980.

On the other hand, the data read / transmit unit 903 reads data in a predetermined order from the data string 911 stored in the data storage unit 910 only when activated by the received data analysis unit 902, and the read data is analyzed for the received data Delivered to part 902.
As described above, the conventional data transmission control is configured to output data to the data signal line SDA800 after the data is read from the data storage unit 910 in the clock stretch state, and to the data signal line SDA800. The data transmission timing is affected by the data reading time from the data storage unit 910, and fluctuates in a direction of delay by that amount.

FIG. 13 is an operation flow (1) of the data transmission control of the prior art, and the slave device 900 after the time when the 1-byte information of the data transmission request information is received from the master device (configured as a prior art transmission control device). The processing procedure of the data transmission control is shown.
When the slave device 900 configured in the prior art receives the first byte of data from the master device 500 (step S901), first, after setting the clock stretch and holding the clock signal line SCL900 at "Low" (Step S902), analyzing the slave address and the contents of the R / W bit included in the first byte received, if the slave address matches the own device address and the value of the R / W bit is `` 1 '', It is determined that it means a data transmission request from the slave device to the master device (step S903). Then, after reading the first data from the beginning of the area where the transmission data string is stored in the data storage unit 910 (step S904), the confirmation response information (acknowledgement) for the information of the first byte received in step S901 above ) Is transmitted to the master device 500 (step S905), the clock stretch is canceled (step S906), and the data read in step S904 is transmitted to the master device 500 (step S907).

Next, it waits for receipt of acknowledgment information (acknowledge) or transmission end information (non-acknowledge) from master device 500 (step S908), and determines whether the received information is acknowledge or non-acknowledge (step S909). If acknowledged (YES), the process is terminated, and if acknowledged (NO), the next process is performed.
After setting the clock stretch (step S910), the next data to be transmitted is read from the transmission data string 911 in the data storage unit 910 (step S911). After the clock stretch is canceled (step S912), the read data is transmitted. (Step S913), the process returns to Step S908.
Here, although the method for determining the head area address of the data string 911 stored in the data storage unit 910 is not described in this operation flow, it is shown by the data transmission sequence (2) in FIG. In the sequence SM05, the master device 500 notifies the slave device 900 in advance.

FIG. 14 is an operation flow (2) of the data transmission control of the prior art. Data on the master device side when the master device configured as the data transmission control device of the prior art autonomously transmits data to the slave device. The processing procedure of transmission control is shown.
The master device configured in the prior art reads the data from the data string stored in its own data storage unit (S921) and transmits the data to the slave device (step S922). It waits for a reply of confirmation response information (acknowledge) (step S923). When confirmation response information is received from the slave device, it is determined whether or not the data transmitted immediately before is the final data of the data string (S924). If it is not the final data (NO), return to step S921 to read the next data In the case of final data (YES), the process is terminated. As described above, in the data transmission control method of the prior art, when data is transmitted from the own device at an autonomous timing, the data is first read from the data storage unit, and then the read data is transmitted. Wait until the acknowledgment information for is returned from the communication partner device. Since the data sequence is transmitted by repeating this processing procedure, the data transmission timing varies due to variations in the data read processing time from the data storage unit, and the transmission completion time of the entire data sequence also varies considerably. become.

The details of the data transmission technology using the I2C interface described above are disclosed in Non-Patent Document 1.
I2C bus specification, version 2.1, published in January 2000 by Philips Japan.

(Problems to be solved by the invention)
A slave device compliant with the conventional I2C interface specification adjusts the timing of data transmission using clock stretching as described above. For example, when a slave device transmits a data string in response to a data transmission request from a master device, it takes time to read data from the data storage unit, so data transmission is temporarily suspended by clock stretching during the read time. I was letting. This clock stretch state occurs every time 1-byte data is read, and when transmitting a large amount of data string, it has been a factor of reducing the data transmission performance of the entire system.
In the data transmission control based on the conventional I2C interface as described above, for example, when trying to conform to the SFP (Small Form-factor Pluggable) specification used in the design of the optical module, The signal SDA decision time t _AA (for example, within _4.5 μs) and the clock stretch allowable time t _Strech (for example, within 5 μs) are very short, so when receiving data from the master device, the slave device must immediately send data to the master device. In other words, it may be difficult to cope with the conventional data transmission control method.
SUMMARY OF THE INVENTION An object of the present invention is to provide a data transmission control method and a data transmission control device for speeding up data transmission when data is transmitted / received while receiving acknowledgment of data arrival between devices.
(Means for solving the problem)

The present invention relates to a method for reading data in a predetermined order from a data string stored in a data storage unit and controlling transmission of data while receiving a confirmation of arrival of data from a communication partner device. The data to be transmitted is read out and stored in the transmission register, and the data stored in the transmission register is transmitted when the data transmission timing is detected.
As a result, the data to be transmitted next is already stored in the transmission register when the data transmission timing is detected, and the data can be transmitted within the processing time required to switch the transmission switch from the transmission register to the data signal line. The delay in data transmission timing can be minimized.

In the present invention, the data transmission timing is determined when the data transmission request information is received from the communication partner device, when the autonomous data transmission request is generated from the own device, and when the data arrival confirmation response information is received from the communication partner device. It can also be configured to be either.
Thereby, the timing delay of data transmission can be suppressed in a form that covers all cases considered as conditions for transmitting data, and the data transmission speed of the entire apparatus can be increased.

The present invention can be further configured to perform data transmission and confirmation of data arrival in accordance with the communication protocol of the I2C serial interface.
According to this, in accordance with the communication protocol of the I2C serial interface, it is possible to increase the speed of data transmission while generally supporting connection between various devices.

(The invention's effect)
When transmitting data while receiving data acknowledgment between devices, the data to be transmitted next is read from the data storage unit in advance and stored in the transmission register before detecting the transmission timing, so that the transmission timing detection point In this case, the data stored in the transmission register can be immediately output to the data signal line, and the data transmission speed can be increased.

Configuration of data transmission control device of the present invention Operation flow (1) of data transmission control of the present invention Operation flow (2) of data transmission control of the present invention Outline of signal timing of data transmission control of the present invention Connection concept between devices for data transmission Signal connection concept between devices for data transmission Data transmission / reception sequence (1) Data transmission / reception sequence (2) Signal timing during data transmission (1) Signal timing of data transmission information (2) Overview of signal timing for conventional data transmission control Configuration of prior art data transmission control device Operation flow of conventional data transmission control (1) Operation flow of conventional data transmission control (2)

(Example)
FIG. 1 shows a configuration of a data transmission control device according to the present invention. Here, an example in which the slave device 100 shown in the connection concept of FIG. 5 is configured as a data transmission control device according to the present invention is shown.
In the data transmission control device of the present invention, first, the data reading unit 103 reads data from the data string 111 stored in the data storage unit 110, stores the data in the transmission register 104, and notifies the reception data analysis unit 102 to that effect. To do.
On the other hand, information transmitted from the master device 500 via the data signal line SDA800 is input to the reception register 101 via the buffer 181, and the reception data analysis unit 102 reads the data stored in the reception register 101. After setting the clock stretch, the contents thereof are analyzed, and if it is data transmission request information from the master device, the acknowledgment response information (acknowledge) is returned and then the clock stretch is canceled. The setting and cancellation of the clock stretch is performed by driving the open drain circuit 170 of the clock signal line SCL700.
After that, the transmission switch 105 is turned on, and the data stored in the transmission register is output to the open drain circuit 180 and transmitted as a serial signal to the data signal line SDA800. At the same time, the data reading unit 103 is activated and the data storage unit 110 The next data reading process is started.
On the other hand, the reception data analysis unit 102 waits for the receipt of confirmation response information (acknowledge) from the master device in parallel with the next data read processing of the data read unit 103 activated above, and the data is received when the confirmation response information is received. If the notification of the completion of the next data read from the read unit 103 is received, the transmission switch 105 is turned on to transmit the data stored in the transmission register to the master device. At this time, since the next data reading process is performed in advance, normally, the data to be transmitted next is already stored in the transmission register 104, and immediately after only the process of turning ON the transmission switch 105, Data stored in the transmission register is transmitted to the master device. Here, during the process of determining whether or not the acknowledgment information has been received, a clock stretch may actually be set. However, since this time is negligible compared to the data reading time from the memory, the essence of the present invention. Has no effect.

In addition, the reception data analysis unit 102 does not operate in parallel with the next data reading process of the data reading unit 103, but waits for a read completion notification of the next data from the data reading unit 103 and recognizes the read completion notification. You may comprise so that reception of the confirmation response information (acknowledgement) from a master apparatus may be waited. Even in this case, the reception timing of the confirmation response information (acknowledgement) is usually later than the data reading completion timing from the data storage unit, so that the data transmission timing can be similarly accelerated.
The above processing procedure is repeated until the transmission end information (non-acknowledgement) indicating the end of data transmission from the master device is received, and the data transmission sequence is terminated.
In this way, instead of transmitting the data after reading the data from the data storage unit 110 as in the prior art, the data is transmitted next in parallel while waiting for reception of the response confirmation information from the communication partner device. Since data is read from the data storage unit 110 and prepared, the data transmission timing is accelerated by the data read time, and the data transmission speed can be increased.
The above embodiment has been described in the case where the configuration of the data transmission control of the present invention is incorporated on the slave device side. However, the same configuration is also adopted when the data is transmitted from the master device to the slave device by incorporating it in the master device. By storing the next transmission data in the transmission register while waiting for reception of the acknowledgment information from the slave device that is the data transmission partner, the processing speed for the data read time from the data storage unit can be increased. Can be improved.

FIG. 2 shows an operation flow (1) of data transmission control according to the present invention, and shows a processing procedure of data transmission control of the slave device 100 when data transmission request information is received from the master device 500.
The slave device 100 configured by the transmission control device of the present invention first reads data to be transmitted first from the data storage unit 110 and stores it in the transmission register 104 (step S101).
Next, when the first byte is received from the master device 500 (step S102), the clock stretch is set and the clock signal line SCL700 is held "Low" (step S103), and then stored in the received first byte. The slave address information and the contents of the R / W bit are analyzed, the slave address matches the address assigned to the own device, the value of the R / W bit is “1”, and the slave device to the master device If it is determined that the request is a data transmission request (step S104), the acknowledgment information (acknowledge) is transmitted to the master device 500 (step S105), the clock stretch is canceled (step S106), and the transmission switch 105 is turned on ( Switch to the (connection) state and transmit the data in the transmission register to the master device (step 107). Here, although the start area address of the transmission data string 111 in the data storage unit 110 is not described in this operation flow, the master device 500 in the sequence SM05 shown in the data transmission sequence (2) of FIG. To the slave device 100 in advance.
Next, after the next data is read from the data string 111 in the data storage unit 110 and stored in the transmission register 104 (step S108), confirmation response information (acknowledge) or transmission end information (non-acknowledge) from the master device 500 is stored. Waits for reception (step S109), determines whether the received information is non-acknowledged or acknowledged (step S110), terminates the process if it is non-acknowledged (YES), and transmits if it is not acknowledged (NO) and transmits The data stored in the register 104 is transmitted by switching the transmission switch 105 (step S111), and the process returns to step S108. In the process of step S110 described above, a clock stretch may be set during the process of determining whether the received data is confirmation response information (acknowledgement), but it can be ignored compared to the data read time from the memory. It does not affect the essence of the present invention.
As described above, since the clock stretch is not set during the data reading process from the time-consuming memory, the delay of the data transmission timing can be minimized and the data transmission can be speeded up.

FIG. 3 is an operation flow (2) of the data transmission control of the present invention. Data transmission control when the master apparatus 500 configured by the data transmission control apparatus of the present invention autonomously transmits data to the slave apparatus 100. The processing procedure of is shown.
The master device 500 reads the transmission data from the data storage unit of its own device, and then stores the data in the transmission register (step S121). After the data stored in the transmission register is transmitted by switching the transmission switch (step S122), the data to be transmitted next is read from the data storage unit and stored in the transmission register (step S123), and the slave is immediately before. Waiting for the receipt of acknowledgment information (acknowledge) from the slave device 100 for the data sent to the device 100, and receiving the acknowledgment information (step S124), it is determined whether the data sent immediately before is the final data (step S125). ), If it is not final data (NO), return to the above step S122, and if it is final (YES), the process is terminated. In this way, the data stored in the transmission register is processed by simply switching the transmission switch, and the data read processing from the data storage unit that takes time is performed as a confirmation response from the communication partner device for the data transmitted immediately before. Since it is performed during the time period required for returning information (acknowledgement), the data to be transmitted next is normally already stored in the transmission register when the acknowledgment information is received. The next data can be transmitted in time.

FIG. 4 is an outline of signal timing for data transmission control according to the present invention. The slave device 100 configured as the data transmission control device according to the present invention receives the data transmission request from the master device 500 through the I2C interface. The signal timing relationship until data 1 as data is started to be transmitted to the master device 500 is conceptually shown.
After detecting the start condition S generated by the master device 500 (timing T101), the slave device 100 receives the 7-bit slave address information transmitted from the master device 500 (timing T102), and is subsequently transmitted. Set the clock stretch when the incoming R / W bit is received, analyze the slave address information and R / W bit information contained in the first received byte, and the slave address matches the address of the device Since the value of the R / W bit is “1”, it is determined that the request is a data transmission request to the slave device 100 (timing T103). Thereafter, the slave device 100 transmits confirmation response information (acknowledge) A to cancel the clock stretch (timing T104), and then starts transmitting the data stored in the transmission register 104 (timing T105). As described above, in the configuration of the present invention, the time for reading data from the data storage unit 110, which was necessary in the prior art between the timings T103 and T104, is unnecessary, and the duration time of the clock stretch state is minimized. Therefore, data transmission can be performed at high speed.

In the above embodiments, the case where the I2C interface is used as a communication interface between apparatuses has been described as a representative example. However, the present invention can be similarly applied even when other communication interfaces are used.
Further, the present invention can be applied not only to the master device and the slave device in the configuration of the embodiment, but also to any device that performs data communication while confirming the arrival of data.

Explanation of symbols

100,200,900 slave device
101 Receive register
102 Received data analysis unit
103 Data reading part
104 Transmit register
105 Transmit switch
110,910 Data storage
111,911 data strings
170,180,570,580,970,980 Open drain circuit
171,181,571,581,971,981 buffer
500 master device
600 Supply voltage
700 Clock signal line SCL
701 Clock signal SCL
760,860 Pull-up resistor (Rp)
800 Data signal line SDA
801 Data signal SDA
810 Slave device time axis
850 Master device time axis

Claims (6)

In a method of reading data in a predetermined order from a data string stored in a data storage unit and controlling transmission of data while taking a confirmation response of data arrival from a communication partner device,
Receiving a clock signal transmitted by a clock signal line from the communication partner device;
Read the data to be transmitted from the data storage unit in advance and store it in the transmission register,
When receiving information from the communication partner device, set the clock signal line to a transmission stop state,
Determining that the information received from the communication partner device is data transmission request information;
Cancel the transmission stop state of the clock signal line,
Transmitting data stored in the transmission register at the time of data transmission timing detection;
And a data transmission control method. The data transmission control method according to claim 1,
Wherein the data transmission timing, the transmission when the slave device for data transmission and reception based on the control of the communication partner apparatus to become the master device receives the data transmission request information from the master device or the slave device to the master device The data arrival confirmation response information for the received data is received from the master device,
And a data transmission control method. The data transmission control method according to claim 1,
In accordance with the communication protocol of the I2C serial interface, send data and confirm the arrival of data,
And a data transmission control method. A data storage unit for storing a data string to be transmitted;
Means for receiving a clock signal transmitted by a clock signal line from a communication partner device;
It means for transmitting data while taking the acknowledgment data arrival with the communication partner apparatus,
Means for reading data to be transmitted from the data storage unit in advance;
A transmission register for storing the read data;
When receiving information from the communication partner device, the clock signal line is set to a transmission stop state, and it is determined that the received information is data transmission request information, and then the transmission of the clock signal line is stopped. Means for releasing the state;
Means for transmitting data stored in the transmission register when detecting data transmission timing;
A data transmission control device. In the data transmission control device according to claim 4 ,
Wherein the data transmission control unit performs data transmission and reception based on the control of the master device to be the communication partner device, wherein the data transmission timing, when receiving the data transmission request information from the master device, or to the master device When the data arrival confirmation response information regarding the transmitted data is received from the master device,
A data transmission control device. In the data transmission control device according to claim 4 ,
In accordance with the communication protocol of the I2C serial interface, send data and confirm the arrival of data,
A data transmission control device.

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