JP5652866B2 - Bus arbitration circuit and bus arbitration method - Google Patents

Description

  The present invention relates to a bus arbitration circuit, and more particularly to a bus arbitration circuit and a bus arbitration method that can be applied to a computer apparatus, an information processing apparatus, and the like.

  2. Description of the Related Art Conventionally, in a system in which a plurality of devices share a bus, a bus arbitration circuit that determines which device is given the bus use right and arbitrates the bus use right is provided. When a conventional bus arbitration circuit is used, if a specific device is busy (during a transfer cycle), another device repeats a retry until data transfer by the specific device is completed. If such an operation continues, other devices cannot transfer data.

  Therefore, in this type of bus arbitration circuit, when a specific device is busy (during the transfer cycle), a method is proposed to prevent data transfer from becoming impossible due to repeated retry of other devices. Has been.

  For example, Patent Literature 1 below describes a bus arbitration circuit that monitors the busy state of a device connected to a bus, stores a device that repeats retry, and preferentially starts data transfer by the device. Yes.

JP 2002-366511 A

  However, in the bus arbitration circuit described in Patent Document 1, a bus use right is preferentially given to a specific device that repeats retrying, but other devices occupy the bus until the bus use right is obtained. Yes. Therefore, there has been a problem that a specific device has to wait for data transfer or repeat the retry.

  Further, when a specific device fails and the transfer cycle cannot be completed, a measure for opening the bus is necessary, and the bus cannot be released until the condition is met. For this reason, there is a problem that other devices have to wait for data transfer or repeat retries.

  Therefore, the present invention has been made in view of the above-described problems in the prior art, and can perform data transfer by a plurality of devices at the same time. An object is to provide a bus arbitration circuit system capable of data transfer.

In order to achieve the above object, the present invention provides a bus arbitration circuit in which a plurality of devices are connected, and transmits data received from the plurality of devices to a common bus. a plurality of queuing buffer for storing a predetermined area, has a temporary buffer to hold the data, and each received data transmitted from a plurality of devices respectively held in the temporary buffer, and held on the temporary buffer A plurality of reception control units for controlling writing of the data to the queuing buffer and information indicating a queuing buffer that includes a plurality of areas and stores data received from the device, the plurality of reception control units Coherency buffer that stores data in a predetermined area according to the order in which data is received, and information stored in the coherency buffer Based reads data from the queuing buffer in sequence which has received the data, and a transmission control unit that transmits to the bus, the reception control unit, the presence or absence of error for data stored in the temporary buffer If the data is judged to have an error, the data is initialized .

  According to the present invention, a reception control unit that controls writing of data received from a plurality of devices to a queuing buffer, and a queuing buffer that stores received data are independently provided for each device. Because it is provided, data can be received from multiple devices at the same time, and even when a specific device cannot transmit data, other devices can transmit data normally without being affected. It becomes possible to do.

  In addition, a coherency buffer that holds information indicating the queuing buffer in which the received data is stored based on the order in which each reception control unit receives the data is provided, so that the data received from each device is received in the order received. Can be sent to the bus.

  In the bus arbitration circuit, the queuing buffer includes a write pointer for designating an area for storing data received by the reception control unit and a read pointer for designating an area for storing data read by the transmission control unit. The coherency buffer includes an order wait pointer for specifying an area for storing information indicating a queuing buffer in which data received from the device is stored, and a queuing in which data to be transmitted to the bus is stored A next transmission pointer that designates an area in which information indicating a buffer is stored, and the reception control unit stores data received from the device in an area designated by the write pointer of the queuing buffer, Completion of reception indicating that data from the device has been received normally Is generated and transmitted to the queuing buffer and the coherency buffer, and data from the reception control unit corresponding to the reception completion signal is stored in an area designated by the order wait pointer of the coherency buffer. Information indicating a queuing buffer is stored, the write pointer and the order wait pointer are incremented based on the reception completion signal, and the transmission control unit is stored in an area designated by the next transmission pointer of the coherency buffer. Refers to information, reads the data stored in the area specified by the read pointer of the queuing buffer corresponding to the referenced information, transmits the data to the bus, and completes the data transmission to the bus A transmission completion signal indicating the queuing buffer and Serial transmitted to coherency buffer, it is possible to increment the read pointer and the next transmission pointer based on the transmission completion signal.

  In the bus arbitration circuit, priority is set for the plurality of reception control units, and the coherency buffer is configured to receive a plurality of reception completion signals simultaneously received from the plurality of reception control units and the set priority order. And storing information indicating a queuing buffer in which data from the reception control unit with the highest priority is stored in an area designated by the order wait pointer, and receiving control with the higher priority according to the priority. Information indicating a queuing buffer in which data from the storage unit is stored can be sequentially stored in the next area, and the order wait pointer can be incremented by the number of the plurality of reception completion signals received simultaneously.

  According to the present invention, since the priority order is set in advance for a plurality of reception control units, the data transmission order is determined according to the set priority order even when data is simultaneously received from a plurality of devices. It becomes possible to do.

The present invention also provides a bus arbitration method for a bus arbitration circuit in which a plurality of devices are connected and data received from the plurality of devices is transmitted to a common bus, and the data transmitted from the plurality of devices is transmitted. When received by each of a plurality of reception control units, each of the received data is held in a temporary buffer, whether there is an error in the plurality of data held in the temporary buffer, and when it is determined that there is no error in the data , together with the respectively stored in a predetermined area of a plurality of queuing buffer comprising said data from a plurality of regions, if it is determined that there is an error in the data, the data is initialized and data received from the device Information indicating the stored queuing buffer is stored in a coherent area consisting of a plurality of areas according to the order in which the plurality of reception control units receive data. Stored in a predetermined area of Nshibaffa, based on the coherency information stored in the buffer, the data read out data from the queuing buffer in sequence that has received, and transmits to the bus.

  According to the present invention, data transfer by a plurality of devices can be performed at the same time as in the above invention, and data transfer by another device can be performed even if a specific device fails.

  As described above, according to the present invention, data transfer by a plurality of devices can be performed simultaneously, and data transfer by other devices can be performed even when a specific device fails.

It is a block diagram which shows the structure of an example of the bus arbitration circuit by one embodiment of this invention. It is a state transition diagram for demonstrating the state of a reception control part.

  Next, modes for carrying out the invention will be described in detail with reference to the drawings.

  FIG. 1 shows an embodiment of a bus arbitration circuit according to the present invention. A bus 2 and devices 3 a to 3 c sharing the bus 2 are connected to the bus arbitration circuit 1. In the example illustrated in FIG. 1, the three devices 3 a to 3 c are connected. However, the present invention is not limited to this, and two or less devices or four or more devices may be connected.

  Here, data transmitted from each of the devices 3a to 3c will be described. Data transmitted from each of the devices 3a to 3c to the bus arbitration circuit 1 is stored in a payload of a predetermined packet and transmitted in units of packets. A start packet (SOP; Start Of Packet) and an end packet (EOP; End Of Packet) are added to the beginning and end of the packet, respectively.

  The bus arbitration circuit 1 is roughly divided into reception control units 11a to 11c, queuing buffers 12a to 12c, a coherency buffer 13, and a transmission control unit 14. The reception control units 11 a to 11 c and the queuing buffers 12 a to 12 c are provided independently corresponding to devices connected to the bus arbitration circuit 1. In the following description, the reception control units 11a to 11c and the queuing buffers 12a to 12c are simply referred to as the reception control unit 11 and the queuing buffer 12 when it is not necessary to distinguish between them.

  The reception controllers 11a to 11c receive data from the devices 3a to 3c and control writing of the received data to the queuing buffers 12a to 12c. Temporary buffers 21a to 21c are connected to the reception control units 11a to 11c, and packets received from the devices 3a to 3c are stored in the temporary buffers 21a to 21c. The reception control units 11a to 11c determine whether or not the packet has been normally received by determining the presence or absence of the SOP and EOP added to the received packet. The data stored in 21a-21c is written into queuing buffers 12a-12c.

  Further, the reception control units 11a to 11c generate a reception completion signal indicating that the data has been normally received, and the reception completion signal is transmitted to write pointers 22a to 22c of the queuing buffers 12a to 12c described later and the coherency buffer 13 respectively. To the order waiting pointer 24.

  The queuing buffers 12a to 12c are provided with a plurality of areas for storing data received from the reception control units 11a to 11c, and connected to the write pointers 22a to 22c and the read pointers 23a to 23c.

  The write pointers 22a to 22c are pointers for designating in which of the plurality of areas in the queuing buffers 12a to 12c the data received from the reception control units 11a to 11c are stored. The write pointers 22a to 22c increment the pointer by one when receiving the reception completion signal from the reception control units 11a to 11c.

  The read pointers 23a to 23c (hereinafter, simply referred to as the read pointer 23 when there is no need to distinguish between them) are stored in any of the data stored in the plurality of areas of the queuing buffers 12a to 12c. This is a pointer for designating whether stored data is read out and transmitted. When the read pointers 23a to 23c receive a transmission completion signal described later from the transmission control unit 14, the read pointers 23a to 23c increment the pointer by one.

  The queuing buffers 12a to 12c store the received data in areas designated by the write pointers 22a to 22c under the control of the reception control units 11a to 11c. Further, the queuing buffers 12a to 12c read out data from the area designated by the read pointers 23a to 23c and transfer the data to the transmission control unit 14 under the control of the transmission control unit 14 described later.

  The coherency buffer 13 stores a plurality of areas for storing information indicating the queuing buffers 12a to 12c in which the received data is stored in order to transmit the data received from the devices 3a to 3c to the bus 2 in the order received. And the order waiting pointer 24 and the next transmission pointer 25 are connected.

  The order wait pointer 24 is a pointer for designating an area for storing information indicating the queuing buffers 12a to 12c in which data waiting for the order of transmission to the bus 2 is stored. The order wait pointer 24 increments the pointer by one when receiving the reception completion signal from the reception control units 11a to 11c.

  The next transmission pointer 25 is a pointer for designating an area in which information indicating the queuing buffers 12 a to 12 c in which data to be transmitted next to the bus 2 is stored among a plurality of areas in the coherency buffer 13. . When the next transmission pointer 25 receives a transmission completion signal described later from the transmission control unit 14, the next transmission pointer 25 increments the pointer by one.

  When the coherency buffer 13 receives a reception completion signal from a predetermined reception control unit among the reception control units 11a to 11c, the coherency buffer 13 moves from the predetermined reception control unit 11 to an area designated by the order wait pointer 24 based on the reception completion signal. Information indicating the queuing buffer 12 storing the data (hereinafter referred to as “information indicating the queuing buffer 12”) is stored.

  The transmission control unit 14 controls reading of data from the queuing buffers 12 a to 12 c and transmission to the bus 2. When transmission to the bus 2 becomes possible, the transmission control unit 14 stores the data waiting for transmission based on the information stored in the area indicated by the next transmission pointer 25 of the coherency buffer 13. Data in the area indicated by the read pointers 23 a to 23 c is read from the buffers 12 a to 12 c and transmitted to the bus 2. Further, the transmission control unit 14 generates a transmission completion signal indicating that transmission of data to the bus 2 is completed, and transmits this transmission completion signal to the read pointers 23 a to 23 c and the next transmission pointer 25.

  Next, the operation of the bus arbitration circuit 1 having the above configuration will be described with reference to FIGS. FIG. 2 is a state transition diagram illustrating an example of operations in the reception control units 11a to 11c. Hereinafter, an operation when data is transferred from the device 3a will be described as an example.

  In a conventional bus arbitration circuit, the start or standby of data transfer from a device is controlled by a control signal such as a chip select signal, a ready signal, or a wait signal from a reception control unit.

  In contrast, in the present embodiment, a reception control unit that receives data transmitted from a plurality of devices and a queuing buffer that stores the received data are provided independently for each device. Yes. Therefore, when transferring data from a device, a control signal such as a chip select signal used in a conventional bus arbitration circuit is unnecessary, and the transfer from each device can be accepted by the reception control unit.

  For example, when the interfaces between the devices 3a to 3c and the reception control units 11a to 11c have a format of start packet (SOP) → payload → check → end packet (EOP), the reception control units 11a to 11c The state shown in FIG.

  In the initial state, the reception control unit 11a is in the SOP state (step S1 in FIG. 2). When receiving the packet from the device 3a, the reception control unit 11a determines whether there is an SOP added to the head of the packet. When the SOP is recognized from the received packet, the state transits to the payload state (step S2 in FIG. 2). On the other hand, when SOP is not recognized, it waits as it is.

  When the state transitions to the payload state (step S2), the reception control unit 11a holds the data stored in the payload of the received packet in the temporary buffer 21a. When data reception from the device 3a is completed, the state transitions to the check state (step S3 in FIG. 2).

  When the state transitions to the check state (step S3), the reception control unit 11a determines whether there is an error in the packets received so far. If it is determined that there is no error, the state transitions to the EOP state (step S4 in FIG. 2). On the other hand, if it is determined that there is an error, the data held in the temporary buffer 21a is initialized, and the state transitions to the SOP state (step S1). Then, it waits until the next packet is transferred from the device 3a.

  When the state transitions to the EOP state (step S4), the reception control unit 11a determines whether or not there is an EOP added to the end of the received packet. When EOP is recognized from the received packet, it is determined that the packet has been normally received. Then, the reception control unit 11a generates a reception completion signal and transmits it to the write pointer 22a and the order wait pointer 24. Further, it waits until the state transits to the SOP state (step S1) and the next packet is received. On the other hand, if EOP is not recognized, the process stands by as it is.

  The reception control unit 11a stores the data held in the temporary buffer 21a in an area designated by the write pointer 22a of the queuing buffer 12a. The write pointer 22a is incremented by 1 by the reception completion signal received from the reception control unit 11a.

  For example, when the area designated by the write pointer 22a is the first area, the data of the currently transmitted packet is stored in the first area of the queuing buffer 12a. The write pointer 22a is incremented by 1 by the reception completion signal, and designates the second area which is the next area. Therefore, the data of the next transmitted packet is stored in the second area of the queuing buffer 12a.

  In this manner, the pointer is incremented by 1 by the reception completion signal, whereby the data of the packet received from the device 3a is sequentially stored in a predetermined area of the queuing buffer 12a designated by the write pointer 22a.

  When packets are transmitted from the other devices 3b and 3c, the same processing is performed, and the reception control units 11b and 11c receive the packets from the devices 3b and 3c and store them in the queuing buffers 12b and 12c. To do. That is, when storing packet data transmitted from the devices 3a to 3c in the queuing buffers 12a to 12c, it is not necessary to consider the relationship with other devices, and the data can be received independently. it can.

  When the coherency buffer 13 receives a reception completion signal from the reception control unit 11a, the coherency buffer 13 holds information indicating the queuing buffer 12a in which data from the reception control unit 11a is stored in an area designated by the order wait pointer 24. The order wait pointer 24 is incremented by 1 by the reception completion signal.

  Similarly, when receiving completion signals are received from the reception control units 11b and 11c, the queuing buffers 12b and 12c in which the data from the reception control units 11b and 11c are stored in the area designated by the order wait pointer 24. Holds the information shown.

  For example, information indicating the queuing buffers 12a, 12b, and 12c in which the data from the reception control units 11a, 11b, and 11c are stored is a value “01”, a value “10”, and a value “11”, respectively. Is received in the order of the reception control units 11a, 11c, 11b, and 11b. In this case, a value “01”, which is information indicating the queuing buffer 12a, is written in the first area of the coherency buffer 13 specified by the order wait pointer 24 first. Next, the order waiting pointer 24 is incremented by 1 by the reception completion signal, and a value “11” that is information indicating the queuing buffer 12 c is written in the second area of the coherency buffer 13. Hereinafter, similarly, a value “10”, which is information indicating the queuing buffer 12b, is written in the third area of the coherency buffer 13, and information indicating the queuing buffer 12b is written in the fourth area. A certain value “10” will be written.

  When transmission to the bus 2 becomes possible, the transmission control unit 14 refers to the information held in the area designated by the next transmission pointer 25 of the coherency buffer 13 and determines which reception control among the plurality of reception control units 11a to 11c. It is determined whether data from the unit 11 is waiting for transmission. Then, the transmission control unit 14 reads the data stored in the predetermined area designated by the read pointer 23 of the queuing buffer 12 corresponding to the information held in the area designated by the next transmission pointer 25, and sends it to the bus 2. To send.

  When the transmission to the bus 2 is normally completed, the transmission control unit 14 transmits a transmission completion signal to the next transmission pointer 25 and the read pointer 23 corresponding to the queuing buffer 12 from which the data has been read. Increment.

  Next, the transmission control unit 14 refers to the information held in the area designated by the next transmission pointer 25 incremented by 1, and the predetermined area designated by the read pointer 23 of the queuing buffer 12 corresponding to this information The data stored in is sent to the bus 2. Thereafter, similarly, the transmission control unit 14 refers to the information held in the area designated by the next transmission pointer 25, sequentially reads the data stored in the predetermined area of the queuing buffer 12, and sends the data to the bus 2. To send.

  In the above example, assuming that the next transmission pointer 25 first designates the first area of the coherency buffer 13, the transmission control unit 14 stores the information held in the first area of the coherency buffer 13. Refer to Since the information held in the first area is the value “01”, the transmission control unit 14 determines that it is waiting for transmission from the reception control unit 11a. Then, the data stored in the area designated by the read pointer 23 a of the queuing buffer 12 a corresponding to the value “01” is read and transmitted to the bus 2.

  When transmission to the bus 2 is normally completed, the transmission control unit 14 transmits a transmission completion signal to the next transmission pointer 25 and the read pointer 23a, and increments each pointer by one. As a result, the area designated by the next transmission pointer 25 becomes the second area.

  Next, the transmission control unit 14 refers to the information held in the second area of the coherency buffer 13. Since the information held in the second area is the value “11”, the transmission control unit 14 determines that it is waiting for transmission from the reception control unit 11c, and the queuing buffer 12c corresponding to the value “11”. The data stored in the area designated by the read pointer 23c is read and transmitted to the bus 2.

  When transmission to the bus 2 is normally completed, the transmission control unit 14 transmits a transmission completion signal to the next transmission pointer 25 and the read pointer 23c, and increments each pointer by one. As a result, the area designated by the next transmission pointer 25 becomes the third area.

  Hereinafter, similarly, the transmission control unit 14 refers to the information held in the third and fourth areas designated by the next transmission pointer 25. Since the information held in the third and fourth areas is the value “10”, the transmission control unit 14 stores the information in the area designated by the read pointer 23c of the queuing buffer 12c corresponding to the value “11”. The read data is read and transmitted to the bus 2.

  In this way, the received data is received by sequentially reading the data transmitted from the plurality of devices 3 a to 3 c and stored in the queuing buffers 12 a to 12 c based on the information held in the coherency buffer 13. It can be transmitted to the bus 2 in order.

  As described above, according to the present embodiment, the reception control unit that receives data transmitted from a plurality of devices connected to the outside and the queuing buffer that stores the received data are set according to the device. Since each is provided independently, data can be received simultaneously from a plurality of devices without being affected by other devices. For this reason, even if a certain device cannot transmit data due to some influence, other devices can transmit data normally without being affected by the influence.

  In addition, according to the present embodiment, since the coherency buffer that holds information indicating the queuing buffer in which the received data is stored is provided based on the order in which the data is received, the data received from each device is received. Can be sent to the bus in the order specified.

  Furthermore, according to the present embodiment, since the reception control unit and the queuing buffer are provided independently according to the device, it is possible to transfer data without giving the bus use right to each device. .

  Next, another embodiment according to the present invention will be described.

  In the bus arbitration circuit 1 to which a plurality of devices are connected, it is conceivable that data transmitted from the devices 3a to 3c is received simultaneously. In such a case, in the embodiment shown in FIGS. 1 and 2, when the reception of data is completed, the reception control units 11 a to 11 c simultaneously generate reception completion signals and transmit them to the order wait pointer 24. become.

  At this time, the order wait pointer 24 receives a plurality of reception completion signals simultaneously. For this reason, the coherency buffer 13 cannot determine which information indicating the queuing buffer 12 in which the data from the reception control unit 11 should be stored in the area specified by the order wait pointer 24, and receives the received data. When transmitting to the bus 2, it is conceivable that transmission cannot be performed in an appropriate transmission order.

  Therefore, in this embodiment, even when data is received simultaneously from a plurality of devices, a priority order is set for the reception control unit corresponding to each device so that the order of transmitting the received data to the bus can be determined. To do.

  The configuration of the bus arbitration circuit 1 according to the present embodiment is the same as that of the bus arbitration circuit 1 according to the embodiment shown in FIG.

  The operation of the bus arbitration circuit 1 according to the present embodiment will be described with reference to FIG. However, the operation of storing the data transmitted from each of the devices 3a to 3c in the queuing buffers 12a to 12c and the operation of reading the data from the queuing buffers 12a to 12c and transmitting them to the bus 2 are described above. Since it is the same as that of FIG.

  In the present embodiment, priorities are set in advance for the reception controllers 11a to 11c. When the coherency buffer 13 receives a plurality of reception completion signals simultaneously, the coherency buffer 13 is a queue in which data from the reception control unit 11 having the highest priority is stored in an area designated by the order wait pointer 24 based on a preset priority. Information indicating the in-buffer 12 is held. Next, information indicating the queuing buffer 12 in which data from the reception control unit 11 having the next highest priority is stored is held in an area immediately ahead of this area. In the same manner, information indicating the queuing buffer 12 is sequentially held in a further area according to the priority order.

  The order waiting pointer 24 is incremented by a predetermined number according to the number of reception completion signals received simultaneously. The incremented number is the number of reception completion signals received simultaneously. For example, the order wait pointer 24 is incremented by 2 when two reception completion signals are received, and is incremented by 3 when three reception completion signals are received.

  Here, as an example, the case where the priority order is the order of the reception control units 11a, 11b, and 11c will be described based on the specific example described in the above-described embodiment. For example, when two data transmitted from the devices 3a and 3b are simultaneously received by the reception control units 11a and 11b, the reception control units 11a and 11b respectively generate reception completion signals and wait for the order of the coherency buffer 13 24 simultaneously.

  When the area of the coherency buffer 13 that is first designated by the order wait pointer 24 is the first area, the data from the reception control unit 11a is stored in the first area in accordance with a preset priority order. A value “01” that is information indicating the queuing buffer 12a is written, and a value “10” that is information indicating the queuing buffer 12b in which data from the reception control unit 11b is stored is written in the second area. . The order wait pointer 24 is incremented by 2 because two reception completion signals are received simultaneously.

  For example, when three data transmitted from the devices 3a, 3b, and 3c are simultaneously received by the reception control units 11a, 11b, and 11c, the order waiting pointer 24 designates according to a preset priority order. A value “01”, which is information indicating the queuing buffer 12a, is written in the first area, and a value “10”, which is information indicating the queuing buffer 12b, is written in the second area. The value “11”, which is information indicating the queuing buffer 12c, is written in Then, the order wait pointer 24 is incremented by 3 because three reception completion signals are received simultaneously.

  Thus, by determining the incremented number of the order wait pointer 24 in accordance with the number of reception completion signals received simultaneously, data reception from each subsequent device can be appropriately performed.

  As described above, according to the present embodiment, since the priority order is set in advance for a plurality of reception control units, the priority order is set even when data is simultaneously received from a plurality of devices. The data transmission order can be determined according to the priorities, and the data can be appropriately transmitted to the bus.

  As mentioned above, although one embodiment of this invention and other embodiment were described, this invention is not limited to one embodiment and other embodiment of this invention mentioned above, The summary of this invention is provided. Various modifications and applications are possible without departing from the scope.

DESCRIPTION OF SYMBOLS 1 Bus arbitration circuit 2 Bus 3 (3a-3c) Device 11 (11a-11c) Reception control part 12 (12a-12c) Queuing buffer 13 Coherency buffer 14 Transmission control part 21 (21a-21c) Temporary buffer 22 (22a- 22c) Write pointer 23 (23a-23c) Read pointer 24 Order wait pointer 25 Next transmission pointer

Claims (4)

A bus arbitration circuit for connecting a plurality of devices and transmitting data received from the plurality of devices to a common bus,
A plurality of queuing buffers that are composed of a plurality of areas and store data in a predetermined area;
A temporary buffer for holding data; receiving data transmitted from a plurality of devices ; holding the data in the temporary buffer ; and controlling writing of the data held in the temporary buffer to the queuing buffer A plurality of reception control units;
A coherency buffer that includes a plurality of areas and stores information indicating a queuing buffer in which data received from the device is stored in a predetermined area according to the order in which the plurality of reception control units receive the data;
Based on the information stored in the coherency buffer, the data is read from the queuing buffer in the order in which the data is received, and a transmission control unit that transmits to the bus ,
The bus arbitration circuit , wherein the reception control unit determines whether or not there is an error in the data held in the temporary buffer, and initializes the data when determining that the data has an error . The queuing buffer is
A write pointer for designating an area for storing data received by the reception control unit;
A read pointer for designating an area for storing data read by the transmission control unit;
The coherency buffer is
An order wait pointer for designating an area for storing information indicating a queuing buffer in which data received from the device is stored;
A next transmission pointer for designating an area storing information indicating a queuing buffer in which data to be transmitted to the bus is stored;
The reception control unit
Store the data received from the device in the area specified by the write pointer of the queuing buffer;
Generating a reception completion signal indicating that data from the device has been normally received, and transmitting the signal to the queuing buffer and the coherency buffer;
Storing information indicating a queuing buffer in which data from a reception control unit corresponding to the reception completion signal is stored in an area designated by the order wait pointer of the coherency buffer;
Based on the reception completion signal, the write pointer and the order wait pointer are incremented,
The transmission control unit
Referring to the information stored in the area specified by the next transmission pointer of the coherency buffer;
Read the data stored in the area specified by the read pointer of the queuing buffer corresponding to the referenced information and send it to the bus,
Generating a transmission completion signal indicating completion of data transmission to the bus, and transmitting to the queuing buffer and the coherency buffer;
The bus arbitration circuit according to claim 1, wherein the read pointer and the next transmission pointer are incremented based on the transmission completion signal. Setting priorities for the plurality of reception control units;
The coherency buffer is
Based on a plurality of reception completion signals received simultaneously from the plurality of reception control units and the set priority, information indicating a queuing buffer storing data from the reception control unit having the highest priority, Store in the area specified by the waiting pointer,
According to the priority, information indicating a queuing buffer in which data from a reception control unit with a high priority is stored is sequentially stored in the next area,
3. The bus arbitration circuit according to claim 2, wherein the order waiting pointer is incremented by the number of the plurality of reception completion signals received simultaneously. A bus arbitration method of a bus arbitration circuit, in which a plurality of devices are connected and data received from the plurality of devices is transmitted to a common bus,
Each of the data received from a plurality of devices is received by a plurality of reception control units,
Each of the received data is held in a temporary buffer,
It is determined whether or not there is an error in a plurality of data held in the temporary buffer, and when it is determined that there is no error in the data, the data is stored in a predetermined area of a plurality of queuing buffers each including a plurality of areas. In addition, when it is determined that there is an error in the data, the data is initialized ,
Information indicating a queuing buffer in which data received from the device is stored is stored in a predetermined area of a coherency buffer including a plurality of areas in accordance with the order in which the plurality of reception control units receive data;
A bus arbitration method comprising: reading data from the queuing buffer in the order in which the data is received based on information stored in the coherency buffer and transmitting the data to the bus.

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