JP2003324032A - Capacitor array and capacitor module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor array in which an equivalent series inductance is reduced. <P>SOLUTION: A chip 11 has four built-in capacitor parts 14a-14d, in parallel. A side electrode 12a of the capacitor part 14a is connected to a side electrode 12d of the capacitor part 14b, with a short circuit electrode 13a formed on a third side surface 11c. A side electrode 12b of the capacitor part 14a is connected to a side electrode 12c of the capacitor part 14b, with a short circuit electrode 13b formed on a fourth side surface 11d. A side electrode 12e of the capacitor part 14c is connected to a side electrode 12h of the capacitor part 14d, with a short circuit electrode 13c formed on the third side surface 11c. A side electrode 12f of the capacitor part 14c is connected to a side electrode 12g of the capacitor part 14d, with a short circuit electrode 13d formed on the fourth side surface 11d. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor array including a plurality of capacitor parts and a capacitor module including the capacitor array and a conductor pattern for array connection.

[0002]

2. Description of the Related Art An active device such as a CPU (Central Processing Unit) may malfunction due to noise superimposed on its power supply wiring, and a bypass capacitor is used to prevent this.

FIG. 1A shows an example of a circuit in which a bypass capacitor is used. Reference numeral 1 in the figure is DC / D.
C converter, 2 CPU, 3 resistance component of power supply wiring,
4 is a bypass capacitor. Bypass capacitor 4
Has one end connected to the power supply line and the other end grounded. The noise superimposed on the power supply line is
Removed by.

[0004]

As shown in FIG. 1A, the bypass capacitor 4 has an inductance L (equivalent series inductance: ES) in addition to the capacitance C.
L), due to the influence of the magnetic field generated by the inductance L when the change component when the predetermined power is supplied to the CPU 2 flows to the bypass capacitor 4,
As shown in FIG. 1B, a phenomenon occurs in which the input voltage Vcc to the CPU 2 drops significantly, and this drop in the input voltage Vcc causes a malfunction in the CPU 2.

The present invention was created in view of the above circumstances, and an object of the present invention is to provide a capacitor array capable of reducing the equivalent series inductance, and a capacitor module using this capacitor array.

[0006]

In order to achieve the above object, the capacitor array of the present invention comprises a chip having a rectangular parallelepiped shape and two or more capacitor units built in parallel, and a pair of capacitors corresponding to each capacitor unit. A capacitor array in which one of the side surface electrodes is formed on the first side surface of the chip and the other is formed on the second side surface of the chip opposite to the first side surface. A short-circuit electrode connecting the side electrode on the first side surface of one of the plurality of capacitor sections and the side electrode on the second side surface of the other capacitor section is formed on the third side surface of the chip, and The short-circuit electrode connecting the side surface electrode on the second side surface of the capacitor section and the side surface electrode on the first side surface of the other capacitor section is formed on the fourth side surface of the chip facing the third side surface. Special To.

In this capacitor array, an electric potential is applied to one of the capacitor sections forming a set so that a current in a predetermined direction flows through the capacitor section, and when there is a capacitor section that does not form a set, the capacitor section is set in the predetermined direction. Alternatively, it is used by applying a potential so that a current flows in the opposite direction. When an electric potential is applied to one of the capacitor units forming the set so that a current in a predetermined direction flows, a current in the opposite direction flows in the other capacitor unit of the set due to the presence of the short-circuit electrode.

That is, a current in a predetermined direction flows in a part of the capacitor part and a current in the opposite direction flows in another capacitor part, and a magnetic field generated by the inductance of the capacitor part through which the current in the predetermined direction flows is generated. The direction of the magnetic field generated by the inductance of the capacitor part in which the current flows in the opposite direction becomes opposite to the direction of the magnetic field, which causes a magnetic field canceling action, and the magnetic field canceling action substantially reduces the equivalent series inductance.

Further, the capacitor module of the present invention is
Two or more capacitor parts are built in parallel in a chip having a rectangular parallelepiped shape, one of a pair of side surface electrodes corresponding to each capacitor part is formed on the first side surface of the chip, and the other is opposed to the first side surface. Is formed on the second side surface of the chip, and two capacitor sections are set as one set, and a side surface electrode on the first side surface of one of the one to a plurality of sets and a second side surface of the other capacitor section are formed. A short-circuit electrode for connecting to a side surface electrode is formed on the third side surface of the chip, and connects the side surface electrode on the second side surface of one capacitor section and the side surface electrode on the first side surface of the other capacitor section. A capacitor array having short-circuit electrodes formed on the fourth side surface of the chip that faces the third side surface, and a potential can be applied to one of the capacitor sections forming the set so that a current in a predetermined direction flows in the capacitor section. Structure When the capacitor unit does not resides comprises an array connecting conductor pattern capable of imparting a potential to a predetermined direction or the opposite direction of the current flowing through the capacitor portion, and its features in that.

According to this capacitor module, a current in a predetermined direction can flow through a part of the capacitor part of the capacitor array through the conductor pattern for array connection, and a current in the opposite direction can flow through another capacitor part. The direction of the magnetic field generated by the inductance of the capacitor section in which the current flows in the opposite direction and the direction of the magnetic field generated by the inductance of the capacitor section in which the current flows in the opposite direction are caused to cause a magnetic field canceling action. The substantial equivalent series inductance can be reduced.

The above and other objects, constitutional features, and operational effects of the present invention will be apparent from the following description and the accompanying drawings.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 2A is a perspective view of a capacitor array to which the present invention is applied as seen from above, and FIG. 2B is a perspective view of this capacitor array as seen from below. 3A is a cross-sectional view of the capacitor array shown in FIG. 2A, FIG. 3B is a cross-sectional view taken along the line AA of FIG. 3A, and FIG. 4 is FIG. 4 is an equivalent circuit diagram of the capacitor array shown in FIG.

This capacitor array 10 has a rectangular parallelepiped chip 11 made of ceramics or the like, and has a total of four capacitor portions 14a to 1 having individual capacitances substantially equal to each other.
4d are built in parallel. Reference numeral 11a in the drawing denotes a first side surface of the chip 11, 11b denotes a second side surface of the chip 11,
Reference numeral 11c is a third side surface of the chip 11, and 11d is a fourth side surface of the chip 11. Each capacitor unit 14a to 14d is shown in FIG.
As shown in (B), it has a structure in which a large number of internal electrodes are laminated via ceramics, etc.
A large number of internal electrodes forming 14d are alternately exposed on the first side surface 11a of the chip 11 and the second side surface 11b opposite thereto.

On the first side surface 11a of the chip 11, side surface electrodes 12 corresponding to the capacitor portions 14a to 14d are formed.
a, 12c, 12e, 12g are formed at intervals,
It joins to the exposed edge of many internal electrodes which comprise each capacitor | condenser part 14a-14d. Further, on the second side surface 11b of the chip 11, side surface electrodes 12b, 12d, 12f, 12h corresponding to the respective capacitor portions 14a to 14d are formed at intervals, and a large number of internal parts constituting the respective capacitor portions 14a to 14d are formed. It is joined to the exposed edge of the electrode. Side electrodes 12a and 12b forming a pair correspond to the first capacitor section 14a from the left in FIG. 3A, and side electrodes 12c and 12d forming a pair are the second capacitors from the left in FIG. 3A. Side electrodes 12e and 12f forming a pair corresponding to the portion 14b correspond to the third capacitor portion 14c from the left in FIG. 3A, and side electrodes 12g and 12h forming a pair correspond to the side electrodes 12g and 12h in FIG. 3A. It corresponds to the fourth capacitor section 14d from the left.

Further, the side surface electrode 12 on the first side surface 11a of the first capacitor portion 14a from the left in FIG. 3 (A).
a and the second side surface 1 of the second capacitor portion 14b from the left
As shown in FIG. 2A, the side surface electrode 12d on the first side 1b is the short-circuit electrode 1 formed on the third side surface 11c in an oblique shape.
It is connected by 3a. In addition, the side surface electrode 12b on the second side surface 11b of the first capacitor section 14a from the left in FIG. 3A and the second capacitor section 14 from the left.
The side surface electrode 12c on the first side surface 11a of FIG.
As shown in (B), the fourth side surface 11d is connected to the fourth side surface 11d by a short-circuit electrode 13b formed in an oblique shape.

Further, the side surface electrode 12 on the first side surface 11a of the third capacitor portion 14c from the left in FIG. 3 (A).
e and the second side surface 1 of the fourth capacitor portion 14d from the left
As shown in FIG. 2A, the side surface electrode 12h on the first side 1b is the short-circuit electrode 1 formed in the oblique shape on the third side surface 11c.
Connected by 3c. In addition, the side surface electrode 12f on the second side surface 11b of the third capacitor section 14c from the left in FIG. 3A and the fourth capacitor section 14 from the left.
The side surface electrode 12g on the first side surface 11a of FIG.
As shown in (B), the fourth side surface 11d is connected to the fourth side surface 11d by a short-circuit electrode 13d formed in an oblique shape.

That is, in the capacitor array 10,
Two adjacent capacitor parts 14a and 14b and 14c
And 14d form a total of two groups, and the first side surface 11a of one of the capacitor sections 14a and 14c of each group is formed.
Side electrodes 12a and 12e and the other capacitor section 1
4b, 14d side electrode 12d on the second side 11b,
The short-circuit electrodes 13a and 13c connecting to 12h are the chip 1
The side surface electrode 1 formed on the third side surface 11c of No. 1 and on the second side surface 11b of one of the capacitor portions 14a and 14c.
Short-circuit electrodes 13b and 13d connecting 2b and 12f with the side surface electrodes 12c and 12g on the first side surface 11a of the other capacitor portion 14b and 14d are formed on the fourth side surface 11d of the chip 11 facing the third side surface 11c. ing.

FIG. 5 is a block diagram of a capacitor module using the capacitor array 10, and FIG. 6 is an equivalent circuit diagram of the capacitor module shown in FIG.

This capacitor module is composed of the capacitor array 10 and an array-connecting conductor pattern (no reference numeral) formed on the main surface of a substrate 20 made of plastic, ceramics or the like. By the way, + in FIGS. 5 and 6 is a symbol indicating a power source potential, and G is a symbol indicating a ground potential.

The conductor pattern for array connection is one of the eight side surface electrodes 12a to 12h of the capacitor array 10.
Two lands 21a corresponding to the side surface electrodes 12a and 12b of the first capacitor section 14a from the left in FIG.
21b, and two lands 21a and 21b corresponding to the side surface electrodes 12e and 12f of the third capacitor portion 14c from the left in FIG. 3A. Also, the lower side 2 in FIG.
The two lands 21a and 21c are connected to the conductor line 22 for power supply potential, and the upper two lands 21b and 21d in FIG. 5 are connected to the conductor line 23 for ground potential. Incidentally, the ground potential conductor wire 23 may be formed not on the main surface of the substrate 20 but on the back surface. In this case, through holes are formed in the upper two lands 21b and 21d in FIG. It is preferable to connect the lands 21b and 21d to the ground potential conductor wire provided on the back surface of the substrate 20 via the.

The capacitor array 10 is shown in FIG.
The first side surface 11 of the first capacitor section 14a from the left
The side surface electrode 12a on the second side surface 11b is connected to the land 21a, and the side surface electrode 12b on the second side surface 11b is connected to the land 21a.
The side surface electrode 12e which is joined to b and is on the first side surface 11a of the third capacitor portion 14c from the left in FIG. 3 (A).
Is bonded to the land 21c, and the side surface electrode 12f on the second side surface 11b is bonded to the land 21d. The other four side surface electrodes 12c, 12d, 12 of the capacitor array 10
Since g and 12h have no corresponding land, they are not in electrical contact with the array connecting conductor pattern. Incidentally, in FIG. 5, the side electrodes 12a, 12b, 12e, 12 are shown.
Illustration of a joining material such as solder used when joining f and the lands 21a to 21d is omitted.

The capacitor array 10 shown in FIG.
5 can be used in place of the bypass capacitor 4 shown in FIG. 1 by using the array connecting conductor pattern shown in FIG. 5 or a conductor pattern similar to this that allows input and output. In this case, the capacitor array 10
The side electrodes 12a and 12e may be connected to the power supply wiring and the side electrodes 12b and 12f may be grounded.

Further, the bypass capacitor 4 shown in FIG. 1 is used without changing the capacitor module shown in FIG.
Can be used instead of. In this case, the conductor wire 22 for power supply potential may be connected to the power supply wiring and the conductor wire 23 for ground potential may be grounded.

In any case, the substrate 20 is not always necessary, and a similar array connecting conductor pattern C is used.
A capacitor module having the same equivalent circuit as that of FIG. 6 can be configured by forming the capacitor array 10 on the back surface of the PU package or the back surface or main surface of the substrate on which the CPU 2 is attached and mounting the capacitor array 10 on the conductor pattern for array connection.

As indicated by an arrow in FIG. 6, when a predetermined electric power is supplied to the CPU 2, the change component at that time flows into each of the capacitor sections 14a to 14d. Specifically, a current flows upward in the first capacitor section 14a from the left and the third capacitor section 14c from the left in FIG. 6, and the short-circuit electrode 13a and the short-circuit electrode 13a in the second capacitor section 14b from the left. 1
Due to the presence of 3b, a current flows downward in the figure, and short-circuit electrodes 13c and 13d are provided in the fourth capacitor section 14d from the left.
The current flows downward in the figure due to the presence of.

That is, the first capacitor section 14 from the left
Since the direction of the current flowing through a and the third capacitor unit 14c is opposite to the direction of the current flowing through the second capacitor unit 14b from the left and the fourth capacitor unit 14d, the first capacitor from the left The inductance 14a1 of the part 14a and the third capacitor part 14 from the left
The direction of the magnetic field generated by the inductance 14c1 of c, the inductance 14b1 of the second capacitor section 14b from the left, and the fourth capacitor section 14 of the left.
The direction of the magnetic field generated by the inductance 14d1 of d is opposite to the direction of the magnetic field, and the magnetic field canceling action occurs. This magnetic field canceling action substantially reduces the equivalent series inductance.

Moreover, four capacitor sections 14a-14
Since a potential is applied so that a current in a predetermined direction flows in half of d and a current in the opposite direction flows in the other half, it is possible to appropriately exert the above-mentioned magnetic field canceling action, and at the same time, in each capacitor portion 14a to 14d. Since the electric potentials are applied so that the directions of the flowing currents are alternately opposite directions, the above-mentioned magnetic field canceling action can be more effectively exhibited, whereby the equivalent series inductance can be surely reduced.

Therefore, it is possible to prevent a phenomenon in which the input voltage Vcc to the CPU 2 greatly drops due to the influence of the magnetic field generated by the equivalent series inductance, and prevent the CPU 2 from malfunctioning due to the drop of the input voltage Vcc. it can.

In the capacitor module shown in FIG. 5, the four side surface electrodes 12c, 12d, 12g, 12h of the capacitor array 10 are used as conductor patterns for array connection.
7 has no corresponding land, but as shown in FIG. 7, dummy lands 21e, 21f, 21 which are not continuous with both conductor lines 22 and 23 are provided in order to secure mounting strength.
g and 21h are provided, and these lands 21e, 21f and 2 are provided.
The four side surface electrodes 12c, 12d, 12g, 12h of the capacitor array 10 may be joined to 1g, 21h.

Further, the short-circuit electrodes 13a and 13c of oblique shape are formed on the third side surface 11c of the capacitor array 10, and the short-circuit electrodes 13b of oblique formation are formed on the fourth side surface 11d.
, And 13d are shown, the short-circuit electrodes 13a to 13d may have a bent shape as shown in FIGS. 8A and 8B or another shape. Absent.

[Second Embodiment] FIG. 9A is a perspective view of a capacitor array to which the present invention is applied as seen from above, and FIG.
(B) is a perspective view of this capacitor array as seen from below,
10A is a cross-sectional view of the capacitor array shown in FIG. 9A, FIG. 10B is a cross-sectional view taken along the line BB of FIG. 9A, and FIG. 11 is shown in FIG. 9A. FIG. 6 is an equivalent circuit diagram of the capacitor array.

This capacitor array 30 has a rectangular parallelepiped chip 31 made of ceramics or the like, and has a total of two capacitor portions 34a, 3 each having substantially the same capacitance.
4b are built in parallel. Reference numeral 31a in the drawing denotes a first side surface of the chip 31, 31b denotes a second side surface of the chip 31,
Reference numeral 31c is the third side surface of the chip 31, and 31d is the fourth side surface of the chip 31. Each capacitor section 34a, 34b is shown in FIG.
As shown in 0 (B), it has a structure in which a large number of internal electrodes are laminated via ceramics or the like, and each capacitor part 34
A large number of internal electrodes forming a and 34b are alternately exposed on the first side surface 31a of the chip 31 and the second side surface 31b opposite thereto.

On the first side surface 31a of the chip 31, side surface electrodes 32 corresponding to the capacitor portions 34a and 34b are formed.
a and 32c are formed at intervals, and each capacitor unit 3
4a, 34b are joined to the exposed edges of many internal electrodes. Further, on the second side surface 31b of the chip 31, side surface electrodes 32b and 32d corresponding to the capacitor portions 34a and 34b are formed at intervals, and exposed ends of a large number of internal electrodes forming the capacitor portions 34a and 34b. It is joined to the edge. The side electrodes 32a and 32b forming a pair correspond to the first capacitor section 34a from the left in FIG. 10A, and the side electrodes 32c and 32d forming a pair are 2 from the left.
It corresponds to the th capacitor section 34b.

Further, the side surface electrode 3 on the first side surface 31a of the first capacitor section 34a from the left in FIG. 10 (A).
2a and the side surface electrode 32d on the second side surface 31b of the second capacitor portion 34b from the left are formed by the short-circuit electrode 33a formed in the oblique shape on the third side surface 31c as shown in FIG. 9 (A). It is connected. In addition, the second side surface 31b of the first capacitor unit 34a from the left in FIG.
9B and the side electrode 32c on the first side surface 31a of the second capacitor portion 34b from the left are formed in an oblique shape on the fourth side surface 31d, as shown in FIG. 9B. It is connected by the short-circuit electrode 33b.

That is, in the capacitor array 30,
One set is composed of two adjacent capacitor sections 34a and 34b, and is located on the side surface electrode 32a on the first side surface 31a of one capacitor section 34a of this set and on the second side surface 31b of the other capacitor section 34b. The short-circuit electrode 33a connecting to the side surface electrode 32d is the third electrode of the chip 31.
One capacitor portion 34 formed on the side surface 31c
a side electrode 32b on the second side surface 31b of a and side surface electrode 32c on the first side surface 31a of the other capacitor portion 34b.
A short-circuit electrode 33b that connects to and is formed on the fourth side surface 31d of the chip 31 that faces the third side surface 11c.

FIG. 12 is a block diagram of a capacitor module using the capacitor array 30, and FIG. 13 is an equivalent circuit diagram of the capacitor module shown in FIG.

This capacitor module comprises the capacitor array 30 and an array-connecting conductor pattern (no reference numeral) formed on the main surface of a substrate 40 made of plastic, ceramics or the like. By the way, + in FIGS. 12 and 13 is a symbol indicating a power source potential, and G is a symbol indicating a ground potential.

The conductor pattern for array connection is one of the four side surface electrodes 32a to 32d of the capacitor array 30.
Two lands 41 corresponding to the side electrodes 32a and 32b of the first capacitor section 34a from the left in FIG.
a and 41b. The lower land 41a in FIG. 12 is connected to the power supply potential conductor wire 42, and the upper land 41b in FIG. 12 is connected to the ground potential conductor wire 43. Incidentally, the ground potential conductor wire 43 may be formed not on the main surface of the substrate 40 but on the back surface. In this case, a through hole is formed in the upper land 41b in FIG. 12, and this through hole is used. Land 41b and substrate 20
It is advisable to connect to the ground potential conductor wire provided on the back surface of the.

The capacitor array 30 is shown in FIG.
The side surface electrode 32a on the first side surface 31a of the first capacitor section 34a from the left in (A) is bonded to the land 41a, and the side surface electrode 32b on the second side surface 31b is bonded to the land 41b. It is mounted on the conductor pattern for array connection. The other two side surface electrodes 32c and 32d of the capacitor array 30 do not have corresponding lands, and therefore are not in electrical contact with the array connecting conductor pattern. Incidentally, in FIG. 5, a bonding material such as solder used when bonding the side electrodes 32a and 32b and the lands 21a and 21b is not shown.

The capacitor array 30 shown in FIG.
Can be used in place of the bypass capacitor 4 shown in FIG. 1 by using the array connecting conductor pattern shown in FIG. 12 or a conductor pattern similar to this that allows input and output. In this case, the capacitor array 3
0 side electrode 32a is connected to the power supply wiring to connect the side electrode 32a.
b may be grounded.

The capacitor module shown in FIG. 12 can be used as it is in place of the bypass capacitor 4 shown in FIG. In this case, the power supply potential conductor wire 42 may be connected to the power supply wiring to ground the ground potential conductor wire 43.

In any case, the substrate 40 is not always necessary, and the same array connecting conductor pattern C is used.
A capacitor module having the same equivalent circuit as in FIG. 13 can be formed by forming the capacitor array 30 on the back surface of the PU package or the back surface or the main surface of the substrate on which the CPU 2 is attached and mounting the capacitor array 30 on the conductor pattern for array connection.

As indicated by the arrow in FIG. 13, when the CPU 2 is supplied with a predetermined electric power, the change component at that time flows into the respective capacitor sections 34a and 34b. Specifically, FIG.
A current flows upward in the figure in the first capacitor section 34a from the left in the figure, and a current flows downward in the figure in the second capacitor section 14b from the left due to the presence of the short-circuit electrodes 33a and 33b.

That is, the first capacitor section 34 from the left
Since the direction of the current flowing through a is opposite to the direction of the current flowing through the second capacitor section 34b from the left,
The direction of the magnetic field generated by the inductance 34a1 of the first capacitor section 34a from the left and the direction of the magnetic field generated by the inductance 34b1 of the second capacitor section 34b from the left are opposite to each other and a magnetic field canceling action occurs. By this magnetic field cancellation effect, the substantial equivalent series inductance is reduced.

Therefore, it is possible to prevent the phenomenon in which the input voltage Vcc to the CPU 2 greatly drops due to the influence of the magnetic field generated by the equivalent series inductance, and prevent the CPU 2 from malfunctioning due to the drop in the input voltage Vcc. it can.

In the capacitor module shown in FIG. 12, the conductor pattern for array connection does not have lands corresponding to the two side electrodes 32c and 32d of the capacitor array 30, but as shown in FIG. In order to secure the mounting strength, dummy lands 41c and 41d which are not continuous with the conductor lines 42 and 43 are provided, and the two side electrodes 32c and 32d of the capacitor array 30 are joined to these lands 41c and 41d. Good.

Further, an obliquely arranged short-circuit electrode 33a is formed on the third side surface 31c of the capacitor array 30, and
The fourth side surface 31d is shown with the obliquely formed short-circuit electrodes 33b formed. The short-circuit electrodes 33a and 33b have a bent shape as shown in FIGS. 15 (A) and 15 (B), and others. It is also possible to adopt the shape of.

[Third Embodiment] FIG. 16A is a perspective view of a capacitor array to which the present invention is applied as seen from above, FIG.
6 (B) is a perspective view of the capacitor array as seen from below, FIG. 17 (A) is a cross-sectional view of the capacitor array shown in FIG. 16 (A), and FIG. 17 (B) is of FIG. 17 (A). C-C
18 is an equivalent circuit diagram of the capacitor array shown in FIG. 16 (A).

This capacitor array 50 has a rectangular parallelepiped chip 51 made of ceramics or the like, and has a total of three capacitor portions 14a to 1 having substantially the same capacitance.
4c is built in parallel. Reference numeral 51a in the drawing denotes a first side surface of the chip 51, 51b denotes a second side surface of the chip 51,
Reference numeral 51c is the third side surface of the chip 51, and 51d is the fourth side surface of the chip 51. Each capacitor unit 54a to 54c is shown in FIG.
As shown in FIG. 7 (B), it has a structure in which a large number of internal electrodes are laminated with ceramics or the like interposed therebetween.
~ 54c is the first internal electrode of the chip 51.
The side surfaces 51a and the second side surfaces 51b facing the side surfaces 51a are alternately exposed.

Further, on the first side surface 51a of the chip 51, side surface electrodes 52 corresponding to the capacitor portions 54a to 54c are formed.
a, 52c, and 52e are formed at intervals, and are joined to the exposed edges of a large number of internal electrodes that form the capacitor portions 54a to 54c. Further, the second side surface 5 of the chip 51
Side electrodes 52b, 52d, and 52f corresponding to the respective capacitor portions 54a to 54c are formed in the 1b at intervals, and are joined to the exposed edges of a large number of internal electrodes forming the respective capacitor portions 54a to 54c. . Side electrode pair 5
Reference numerals 2a and 52b correspond to the first capacitor section 54a from the left in FIG. 17 (A), and side electrodes 52c and 52d forming a pair correspond to the second capacitor section 54b from the left in FIG. 17 (A). , The side electrodes 52e and 52f forming a pair correspond to the third capacitor section 54c from the left in FIG.

Further, the side surface electrode 5 on the first side surface 51a of the first capacitor section 54a from the left in FIG. 17A.
2a and the side surface electrode 52d on the second side surface 51b of the second capacitor portion 54b from the left are formed by the short-circuit electrode 53a formed in the oblique shape on the third side surface 51c as shown in FIG. 16 (A). It is connected. In addition, FIG.
The second side surface 51 of the first capacitor section 54a from the left
The side surface electrode 52b on the side b and the side surface electrode 52c on the first side surface 51a of the second capacitor portion 54b from the left are
As shown in FIG. 16B, the fourth side surface 51d is connected to the fourth side surface 51d by a short-circuit electrode 53b formed in an oblique shape.

That is, in the capacitor array 50,
One set is composed of two adjacent capacitor parts 54a and 54b, and is located on the side surface electrode 52a on the first side surface 51a of one of the capacitor parts 54a of this set and on the second side surface 51b of the other capacitor part 54b. The short-circuit electrode 53a connecting to the side surface electrode 52d is the third of the chip 51.
One capacitor portion 54 formed on the side surface 51c
a side electrode 52b on the second side surface 51b of a and side surface electrode 52c on the first side surface 51a of the other capacitor portion 54b.
A short-circuit electrode 53b that connects to and is formed on the fourth side surface 51d of the chip 51 that faces the third side surface 51c. In addition, the side surface electrodes 52e and 52f of the other capacitor section 54c.
The short-circuit electrode as described above is not connected to.

FIG. 19 is a block diagram of a capacitor module using the capacitor array 50, and FIG. 20 is an equivalent circuit diagram of the capacitor module shown in FIG.

This capacitor module comprises the capacitor array 50 and an array-connecting conductor pattern (not shown) formed on the main surface of a substrate 60 made of plastic, ceramics or the like. By the way, + in FIGS. 19 and 20 is a symbol indicating a power source potential, and G is a symbol indicating a ground potential.

The conductor pattern for array connection is one of the six side surface electrodes 52a to 52f of the capacitor array 50.
Two lands 61 corresponding to the side surface electrodes 52a and 52b of the first capacitor section 54a from the left in FIG. 17A.
17a and two lands 61a and 61b corresponding to the side surface electrodes 52e and 52f of the third capacitor portion 54c from the left in FIG. 17A. The lower two lands 61a and 61c in FIG. 19 are connected to the power supply potential conductor line 62, and the upper two lands 61b and 61b in FIG.
61d is connected to the ground potential conductor wire 63. By the way, the ground potential conductor wire 63 may be formed on the back surface of the substrate 60 instead of the main surface. In this case, through holes are formed in the upper two lands 61b and 61d in FIG. It is preferable to connect the lands 61b and 61d to the ground potential conductor wire provided on the back surface of the substrate 60 via the.

The capacitor array 50 is shown in FIG.
The side surface electrode 52a on the first side surface 51a of the first capacitor portion 54a from the left in (A) is joined to the land 61a, and the side surface electrode 52b on the second side surface 51b is joined to the land 61b. The side surface electrode 52e on the first side surface 51a of the third capacitor portion 54c from the left in FIG. 17A is joined to the land 61c, and the second side surface 51 is formed.
The side surface electrode 52f at b is mounted on the array connecting conductor pattern so as to be bonded to the land 61d. The other two side surface electrodes 52c and 52d of the capacitor array 50
Since the corresponding land does not exist, it is not in electrical contact with the array connecting conductor pattern. By the way, Figure 1
In FIG. 9, a joining material such as solder used when joining the side electrodes 52a, 52b, 52e, 52f and the lands 61a to 61d is not shown.

The capacitor array 5 shown in FIG.
0 can be used in place of the bypass capacitor 4 shown in FIG. 1 by using the array connecting conductor pattern shown in FIG. 19 or a conductor pattern similar to this which allows input and output. In this case, the side electrodes 52a and 52e of the capacitor array 50 may be connected to the power supply wiring and the side electrodes 52b and 52f may be grounded.

The capacitor module shown in FIG. 19 can be used as it is in place of the bypass capacitor 4 shown in FIG. In this case, the power source potential conductor wire 62 may be connected to the power source wiring to ground the ground potential conductor wire 63.

In any case, the substrate 60 is not always necessary, and a similar array connecting conductor pattern is used for the CPU.
A capacitor module having the same equivalent circuit as in FIG. 19 can be configured by forming the capacitor array 50 on the back surface of the package or the back surface or the main surface of the substrate on which the CPU 2 is attached and mounting the array connecting conductor pattern.

As shown by the arrow in FIG. 20, when the predetermined power is supplied to the CPU 2, the change component at that time flows into each of the capacitor sections 54a to 54c. Specifically, FIG.
An electric current flows upward in the figure in the first capacitor section 54a from the left and the third capacitor section 54c from the left, and downward in the figure due to the presence of the short-circuit electrodes 53a and 53b in the second capacitor section 54b from the left. Current flows through.

That is, the first capacitor section 54 from the left
a and the direction of the current flowing through the third capacitor section 54c are opposite to the direction of the current flowing through the second capacitor section 54b from the left, the inductance 54a1 of the first capacitor section 54a from the left 3 from the left
Inductance 54c of the th capacitor section 54c
The direction of the magnetic field generated by 1 and the direction of the magnetic field generated by the inductance 54b1 of the second capacitor section 54b from the left are opposite to each other to cause a magnetic field canceling action, and this magnetic field canceling action causes a substantial equivalent series. Inductance is reduced.

Therefore, it is possible to suppress a phenomenon in which the input voltage Vcc to the CPU 2 greatly drops due to the influence of the magnetic field generated by the equivalent series inductance, and to prevent the CPU 2 from malfunctioning due to the drop of the input voltage Vcc. it can.

In the capacitor module shown in FIG. 19, the array connecting conductor pattern has no lands corresponding to the two side surface electrodes 52c and 52d of the capacitor array 50, but as shown in FIG. In order to secure the mounting strength, dummy lands 61e and 61f which are not continuous with the conductor lines 62 and 63 are provided, and the two side surface electrodes 52c and 52d of the capacitor array 50 are joined to these lands 61e and 61f. Good.

Further, an obliquely-shaped short-circuit electrode 53a is formed on the third side surface 51c of the capacitor array 50, and
The fourth side surface 51d is shown with the short-circuit electrodes 53b formed obliquely, but the short-circuit electrodes 53a and 53b have a bent shape as shown in FIGS. 22 (A) and 22 (B), and others. It is also possible to adopt the shape of.

Furthermore, in the capacitor module shown in FIG. 19, the first capacitor section 54 from the left in FIG.
a and the third capacitor section 54c from the left, an electric current flows upward in the figure, and the second capacitor section 54b from the left flows in a downward direction in the figure. As shown in FIG. 23, as shown in FIG. 23, the current flows upward in the first capacitor section 54a from the left in FIG. 23, and the second capacitor section 54b from the left and the third capacitor from the left. The same effect as described above can be obtained by adopting, as the array-connecting conductor pattern, a part capable of applying a power supply potential and a ground potential so that a current flows downward in the drawing in the portion 54c.

As described above, in the above-described first embodiment, the one in which a total of four capacitor units 14a to 14d are built is shown as the capacitor array 10, and in the above-described second embodiment, a total of two capacitor units 34a and 34b are built-in. This is shown as the capacitor array 30, and in the above-described third embodiment, the one in which a total of three capacitor units 54a to 54c are incorporated is shown as the capacitor array 50. However, when the number of capacitor units is an even number other than 4 or 2, Even if there is an odd number (excluding 1) other than 3 even if there are three capacitor sections, basically, two capacitor sections are set as one group, and the first capacitor section of one of the plurality of groups is divided into two groups. A short-circuit electrode that connects the side surface electrode on one side surface and the side surface electrode on the second side surface of the other capacitor portion is formed on the third side surface of the chip, and the second side of one capacitor portion is formed. If a short-circuit electrode that connects the side electrode on the side of the other side to the side electrode on the side of the first side of the other capacitor portion is formed on the fourth side surface of the chip facing the third side surface, a capacitor array with the same effect can be obtained. be able to. In this case, two adjacent capacitor units may form one set, or if the total number of capacitor units is an even number, a total number of / 2 sets may be provided, and If the number is odd, (total −
You may make it provide the group of 1) / 2.

Further, in the above-described first to third embodiments, C
Although the capacitor array and the capacitor module are used instead of the bypass capacitor used for the power input system of the PU, the above capacitor module is used instead of the bypass capacitor used for the power input system of active devices other than the CPU. However, the same effect as described above can be obtained, and the problem caused by the equivalent series inductance can be eliminated by using the capacitor module instead of the capacitor used in a place other than the power input system.

[0068]

As described in detail above, according to the present invention,
The equivalent series inductance can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a circuit using a bypass capacitor and a diagram showing a phenomenon in which an input voltage to a CPU drops significantly.

FIG. 2 is a perspective view of the capacitor array as seen from above and a perspective view of the capacitor array as seen from below according to the first embodiment of the present invention.

3 is a cross-sectional view of the capacitor array shown in FIG. 2,
The AA line sectional view

4 is an equivalent circuit diagram of the capacitor array shown in FIG.

5 is a configuration diagram of a capacitor module using the capacitor array shown in FIG.

6 is an equivalent circuit diagram of the capacitor module shown in FIG.

FIG. 7 is a diagram showing a modified example of the array connecting conductor pattern shown in FIG.

FIG. 8 is a diagram showing a modification of the short-circuit electrode shown in FIG.

FIG. 9 is a perspective view of the capacitor array seen from the upper side and a perspective view of the capacitor array seen from the lower side according to the second embodiment of the present invention.

10 is a horizontal cross-sectional view of the capacitor array shown in FIG. 9 and a cross-sectional view taken along line BB thereof.

11 is an equivalent circuit diagram of the capacitor array shown in FIG.

12 is a block diagram of a capacitor module using the capacitor array shown in FIG.

13 is an equivalent circuit diagram of the capacitor module shown in FIG.

FIG. 14 is a view showing a modified example of the array connecting conductor pattern shown in FIG.

15 is a diagram showing a modification of the short-circuit electrode shown in FIG.

FIG. 16 is a perspective view of the capacitor array seen from the upper side and a perspective view of the capacitor array seen from the lower side according to the third embodiment of the present invention.

FIG. 17 is a horizontal cross-sectional view of the capacitor array shown in FIG. 16 and a cross-sectional view taken along the line CC of FIG.

18 is an equivalent circuit diagram of the capacitor array shown in FIG.

19 is a configuration diagram of a capacitor module using the capacitor array shown in FIG.

20 is an equivalent circuit diagram of the capacitor module shown in FIG.

FIG. 21 is a view showing a modification of the array connecting conductor pattern shown in FIG.

22 is a diagram showing a modification of the short-circuit electrode shown in FIG.

FIG. 23 is a diagram showing another modification of the array connecting conductor pattern shown in FIG. 19;

[Explanation of symbols]

10 ... Capacitor array, 11a ... 1st side surface, 11b ...
2nd side surface, 11c ... 3rd side surface, 11d ... 4th side surface, 12
a-12h ... Side electrode, 13a-13d ... Short-circuit electrode, 1
4a to 14d ... Capacitor section, 14a1 to 14d1 ... Inductance, 20 ... Substrate, 21a to 21h ... Land,
22 ... Conductor wire for power potential, 23 ... Conductor wire for ground potential, 3
0 ... Capacitor array, 31a ... 1st side surface, 31b ... 2nd side surface, 31c ... 3rd side surface, 31d ... 4th side surface, 32a
-32d ... Side electrode, 33a, 33b ... Short-circuit electrode, 34
a, 34b ... Capacitor part, 34a1, 34b1 ... Inductance, 40 ... Substrate, 41a-41d ... Land, 4
2 ... Conductor wire for power supply potential, 43 ... Conductor wire for ground potential, 50
... condenser array, 51a ... first side surface, 51b ... second
Side surface, 51c ... Third side surface, 51d ... Fourth side surface, 52a-
52f ... Side electrode, 53a, 53b ... Short-circuit electrode, 53a
-53c ... Capacitor part, 53a1-53c1 ... Inductance, 60 ... Board, 61a-61f ... Land, 62
... power source potential conductor wire, 63 ... ground potential conductor wire.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Mitsuo Nakajima             6-16-20 Ueno, Taito-ku, Tokyo Sun invitation             Denden Co., Ltd. F term (reference) 5E082 AA01 AB03 BB07 BC14 BC39                       CC03 CC13 EE04 FF05 FG26                       FG46 MM22 MM23 MM24

Claims (8)

[Claims] 1. A chip having a rectangular parallelepiped shape has two or more capacitor parts built in in parallel, one of a pair of side surface electrodes corresponding to each capacitor part is formed on the first side surface of the chip, and the other is A capacitor array formed on a second side surface of a chip facing a first side surface, wherein two capacitor sections are set as one set, and a side surface electrode on the first side surface of one of the capacitor sections of one to a plurality of sets. A short-circuit electrode connecting to the side surface electrode on the second side surface of the other capacitor portion is formed on the third side surface of the chip, and the side surface electrode on the second side surface of the one capacitor portion and the first side surface of the other capacitor portion are formed. A capacitor array, wherein a short-circuit electrode connecting to a side surface electrode on the side surface is formed on the fourth side surface of the chip facing the third side surface. 2. One of two adjacent capacitor parts is provided.
The capacitor array according to claim 1, wherein two sets are configured. 3. When the total number of capacitor parts is an even number, a set of total number / 2 is provided, and when the number of capacitor parts is an odd number, a set of (total number-1) / 2 is provided. The capacitor array according to claim 1 or 2. 4. A chip having a rectangular parallelepiped shape is provided with two or more capacitor parts in parallel, one of a pair of side surface electrodes corresponding to each capacitor part is formed on the first side surface of the chip, and the other is formed. The capacitor is formed on the second side surface of the chip facing the first side surface, and the two capacitor sections are set as one set, and the side surface electrode on the first side surface of one of the capacitor sections of one to a plurality of sets and the other capacitor section. A short-circuit electrode connecting to a side surface electrode on the second side surface of the chip is formed on the third side surface of the chip, and a side surface electrode on the second side surface of one capacitor section and a side surface on the first side surface of the other capacitor section. The fourth electrode of the chip in which the short-circuit electrode connecting to the electrode faces the third side surface.
A potential can be applied to the capacitor array formed on the side surface and one of the capacitor parts that make up the set so that a current in a predetermined direction flows through the capacitor part.If there is a capacitor part that does not make up the set, this capacitor part An array-connecting conductor pattern capable of applying a potential so that a current flows in a predetermined direction or in a reverse direction. 5. The capacitor module according to claim 4, wherein the capacitor array forms one set by two adjacent capacitor units. 6. The capacitor array is provided with a total number / 2 set when the total number of capacitor parts is an even number, and is provided with (total number-1) / 2 set when the total number of capacitor parts is an odd number. 6. The capacitor module according to claim 4 or 5. 7. The conductor pattern for array connection is provided with a land of the number obtained by multiplying the number of sets by 2 when the total number of capacitor parts in the capacitor array is an even number and the number of sets is total number / 2. 7. The number of lands obtained by adding 2 to the number obtained by multiplying the number of sets by 2 is provided when the total number of capacitor units in is an odd number and the number of sets is (total number-1) / 2. The capacitor module described in. 8. The array connecting conductor pattern is provided on a back surface or a main surface of a package or a substrate to which an active device is attached, according to any one of claims 4 to 7. Capacitor module.