JP2003318360A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法

Info

Publication number
JP2003318360A
JP2003318360A JP2002116982A JP2002116982A JP2003318360A JP 2003318360 A JP2003318360 A JP 2003318360A JP 2002116982 A JP2002116982 A JP 2002116982A JP 2002116982 A JP2002116982 A JP 2002116982A JP 2003318360 A JP2003318360 A JP 2003318360A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor device
semiconductor
tab
electrode pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002116982A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003318360A5 (https=
Inventor
Daiki Ishimura
大樹 石村
Katsunori Takahashi
勝則 高橋
Mitsuru Sakamoto
満 坂本
Tadashi Asari
直史 浅利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Ltd
Renesas Northern Japan Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Renesas Northern Japan Semiconductor Inc filed Critical Hitachi Ltd
Priority to JP2002116982A priority Critical patent/JP2003318360A/ja
Priority to US10/417,092 priority patent/US6849952B2/en
Publication of JP2003318360A publication Critical patent/JP2003318360A/ja
Publication of JP2003318360A5 publication Critical patent/JP2003318360A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
    • H10W40/77—Auxiliary members characterised by their shape
    • H10W40/778—Auxiliary members characterised by their shape in encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07511—Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5366—Shapes of wire connectors the bond wires having kinks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5434—Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2002116982A 2002-04-19 2002-04-19 半導体装置およびその製造方法 Pending JP2003318360A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002116982A JP2003318360A (ja) 2002-04-19 2002-04-19 半導体装置およびその製造方法
US10/417,092 US6849952B2 (en) 2002-04-19 2003-04-17 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002116982A JP2003318360A (ja) 2002-04-19 2002-04-19 半導体装置およびその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007166097A Division JP4892418B2 (ja) 2007-06-25 2007-06-25 半導体装置

Publications (2)

Publication Number Publication Date
JP2003318360A true JP2003318360A (ja) 2003-11-07
JP2003318360A5 JP2003318360A5 (https=) 2005-09-22

Family

ID=29534329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002116982A Pending JP2003318360A (ja) 2002-04-19 2002-04-19 半導体装置およびその製造方法

Country Status (2)

Country Link
US (1) US6849952B2 (https=)
JP (1) JP2003318360A (https=)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285877A (ja) * 2004-03-26 2005-10-13 Nec Semicon Package Solutions Ltd 半導体装置およびその製造方法
JP2007258751A (ja) * 2007-06-25 2007-10-04 Renesas Technology Corp 半導体装置
US8432015B2 (en) 2007-09-13 2013-04-30 Toyota Jidosha Kabushiki Kaisha Semiconductor device and wire bonding method
JP2013128019A (ja) * 2011-12-16 2013-06-27 Renesas Electronics Corp 半導体装置
CN113644003A (zh) * 2021-08-10 2021-11-12 致真存储(北京)科技有限公司 一种已图形化的磁性隧道结晶圆的磁阻测试结构及其使用方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI233674B (en) * 2003-07-29 2005-06-01 Advanced Semiconductor Eng Multi-chip semiconductor package and manufacturing method thereof
US7554179B2 (en) * 2005-02-08 2009-06-30 Stats Chippac Ltd. Multi-leadframe semiconductor package and method of manufacture
US7560821B2 (en) * 2005-03-24 2009-07-14 Sumitomo Bakelite Company, Ltd Area mount type semiconductor device, and die bonding resin composition and encapsulating resin composition used for the same
TWI305389B (en) * 2005-09-05 2009-01-11 Advanced Semiconductor Eng Matrix package substrate process
US8236607B2 (en) * 2009-06-19 2012-08-07 Stats Chippac Ltd. Integrated circuit packaging system with stacked integrated circuit and method of manufacture thereof
TW201106499A (en) * 2009-08-03 2011-02-16 Forward Electronics Co Ltd High-efficiency light emitting diode

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100192179B1 (ko) * 1996-03-06 1999-06-15 김영환 반도체 패키지
JP3481444B2 (ja) * 1998-01-14 2003-12-22 シャープ株式会社 半導体装置及びその製造方法
JP3565319B2 (ja) * 1999-04-14 2004-09-15 シャープ株式会社 半導体装置及びその製造方法
JP2001015644A (ja) 1999-06-28 2001-01-19 Toshiba Corp 半導体パッケージ及びその製造方法
JP3460646B2 (ja) 1999-10-29 2003-10-27 松下電器産業株式会社 樹脂封止型半導体装置およびその製造方法
JP3737333B2 (ja) 2000-03-17 2006-01-18 沖電気工業株式会社 半導体装置
KR100559664B1 (ko) * 2000-03-25 2006-03-10 앰코 테크놀로지 코리아 주식회사 반도체패키지
JP2002076248A (ja) * 2000-08-29 2002-03-15 Oki Micro Design Co Ltd マルチチップパッケージ
JP3683179B2 (ja) * 2000-12-26 2005-08-17 松下電器産業株式会社 半導体装置及びその製造方法
US6388313B1 (en) * 2001-01-30 2002-05-14 Siliconware Precision Industries Co., Ltd. Multi-chip module
TW523887B (en) * 2001-11-15 2003-03-11 Siliconware Precision Industries Co Ltd Semiconductor packaged device and its manufacturing method
US6472736B1 (en) * 2002-03-13 2002-10-29 Kingpak Technology Inc. Stacked structure for memory chips

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285877A (ja) * 2004-03-26 2005-10-13 Nec Semicon Package Solutions Ltd 半導体装置およびその製造方法
JP2007258751A (ja) * 2007-06-25 2007-10-04 Renesas Technology Corp 半導体装置
US8432015B2 (en) 2007-09-13 2013-04-30 Toyota Jidosha Kabushiki Kaisha Semiconductor device and wire bonding method
JP2013128019A (ja) * 2011-12-16 2013-06-27 Renesas Electronics Corp 半導体装置
US8637966B2 (en) 2011-12-16 2014-01-28 Renesas Electronics Corporation Semiconductor device
US8803303B2 (en) 2011-12-16 2014-08-12 Renesas Electronics Corporation Semiconductor device
CN113644003A (zh) * 2021-08-10 2021-11-12 致真存储(北京)科技有限公司 一种已图形化的磁性隧道结晶圆的磁阻测试结构及其使用方法

Also Published As

Publication number Publication date
US6849952B2 (en) 2005-02-01
US20040021231A1 (en) 2004-02-05

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