JP2003304051A - Circuit board and method of improving its solder wettability - Google Patents

Circuit board and method of improving its solder wettability

Info

Publication number
JP2003304051A
JP2003304051A JP2002108856A JP2002108856A JP2003304051A JP 2003304051 A JP2003304051 A JP 2003304051A JP 2002108856 A JP2002108856 A JP 2002108856A JP 2002108856 A JP2002108856 A JP 2002108856A JP 2003304051 A JP2003304051 A JP 2003304051A
Authority
JP
Japan
Prior art keywords
circuit board
solder
circuit
metal
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002108856A
Other languages
Japanese (ja)
Other versions
JP3827605B2 (en
Inventor
Takeshi Iwamoto
豪 岩元
Yoshihiko Tsujimura
好彦 辻村
Nobuyuki Yoshino
信行 吉野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denka Co Ltd
Original Assignee
Denki Kagaku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denki Kagaku Kogyo KK filed Critical Denki Kagaku Kogyo KK
Priority to JP2002108856A priority Critical patent/JP3827605B2/en
Publication of JP2003304051A publication Critical patent/JP2003304051A/en
Application granted granted Critical
Publication of JP3827605B2 publication Critical patent/JP3827605B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Chemically Coating (AREA)
  • Cleaning And De-Greasing Of Metallic Materials By Chemical Methods (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board that can remarkably reduce solder voids. <P>SOLUTION: In a method of improving solder wettability of circuit board, the surface of a plated-Ni film formed on a metallic circuit is cleaned with electrolytic water of ≥10 in pH, ≤-800 mV in equilibrium potential, and ≥10.0 mS/m in electrical conductivity. It is preferable to heat-treat the surface of the plated-Ni film at a temperature of 280±10°C in a vacuum of ≤1 Pa before cleaning. The circuit board is cleaned by this method. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、回路基板及び回路
基板の半田濡れ性向上方法に関する。詳しくは、Niめ
っきの施された金属回路に、シリコンチップ等の半導体
素子を半田付けする際に、半田ボイドといわれている欠
陥を激減することができる技術に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board and a method for improving solder wettability of the circuit board. More specifically, the present invention relates to a technique capable of drastically reducing defects called solder voids when soldering a semiconductor element such as a silicon chip to a Ni-plated metal circuit.

【0002】[0002]

【従来の技術】半導体素子の搭載されたモジュールが解
決すべき今日の課題は、近来のエレクトロニクス技術の
発展に伴う高出力化が進む中、回路基板の耐久性を高め
るとともに、半導体素子から発生した熱を効率よく速や
かに系外に逃がすこと、例えば熱伝導を阻害する半田ボ
イドを低減することである。
2. Description of the Related Art Today's problems to be solved by a module equipped with a semiconductor element are caused by the semiconductor element as well as the durability of a circuit board, while the output is being increased with the recent development of electronic technology. Efficiently and quickly releasing heat to the outside of the system, for example, reducing solder voids that hinder heat conduction.

【0003】回路基板の基本構造は、セラミックス基板
の表面に金属回路、裏面に金属放熱板が形成され、該金
属回路と金属放熱板にNiめっきが施されている。そし
て、モジュールの組み立ての際に、金属回路に半導体素
子が搭載され、金属放熱板面にヒートシンク取付用のベ
ース板が半田付けされる。
The basic structure of a circuit board is such that a metal circuit is formed on the front surface of a ceramic substrate and a metal heat dissipation plate is formed on the back surface, and the metal circuit and the metal heat dissipation plate are plated with Ni. Then, when the module is assembled, the semiconductor element is mounted on the metal circuit, and the base plate for mounting the heat sink is soldered to the surface of the metal heat dissipation plate.

【0004】セラミックス基板の材質としては、アルミ
ナ、窒化アルミニウム、窒化ケイ素等、また金属回路、
金属放熱板、ベース板の材質としては、銅、アルミニウ
ム、それらの合金等が用いられている。また、セラミッ
クス基板と金属回路、金属放熱板との接合は、Ag、C
u又はAg−Cu合金とTi、Zr、Hf等の活性金属
成分を含むろう材を用いる活性金属ろう付け法が主流と
なっている。
Materials for the ceramic substrate include alumina, aluminum nitride, silicon nitride, metal circuits,
Copper, aluminum, alloys thereof, and the like are used as materials for the metal heat dissipation plate and the base plate. In addition, the bonding of the ceramic substrate, the metal circuit, and the metal heat sink is made of Ag, C
The active metal brazing method using a brazing material containing an u or Ag-Cu alloy and an active metal component such as Ti, Zr, or Hf is predominant.

【0005】回路基板にヒートサイクル等の熱負荷が加
わると、セラミックス基板と金属の熱膨張差に起因する
熱応力が発生し、セラミックス基板と金属回路、金属放
熱板(以下、両者を「金属回路等」という。)との接合
端面において、セラミックス基板にクラックが発生す
る。このクラックは、熱負荷のサイクル数の増加と共に
進展し、極端な場合には絶縁破壊に至る。このような、
クラックの発生を抑制するため、金属回路等の材質とし
て、熱応力がCuよりも小さいAlが用いられるように
なっている。
When a thermal load such as a heat cycle is applied to the circuit board, thermal stress is generated due to a difference in thermal expansion between the ceramic substrate and the metal, and the ceramic substrate, the metal circuit, and the metal radiator plate (hereinafter, both are referred to as “metal circuit”). Etc.)), a crack is generated in the ceramic substrate at the joint end face. This crack progresses with an increase in the number of cycles of heat load, and in an extreme case, it causes dielectric breakdown. like this,
In order to suppress the generation of cracks, Al having a thermal stress smaller than that of Cu is used as a material for the metal circuit or the like.

【0006】Al回路と半導体素子や、Al放熱板とベ
ース板の接合には、Pb−Sn系の半田が用いられるた
め、金属(Al)回路等表面にはNiめっきを施す必要
がある。金属回路等がCu材質である場合も、酸化防止
や半田との反応による信頼性低下を防ぐため、一般的に
はNiめっきが施される。半田付けには、フラックスを
用いて大気中又は窒素中でリフローする方法と、フラッ
クスを用いないで水素雰囲気下でリフローする方法等が
採用されている。
Since Pb-Sn solder is used for joining the Al circuit and the semiconductor element and the Al heat sink and the base plate, it is necessary to apply Ni plating to the surface of the metal (Al) circuit or the like. Even when the metal circuit or the like is made of Cu, Ni plating is generally applied in order to prevent oxidation and decrease in reliability due to reaction with solder. For soldering, a method of reflowing in air or nitrogen using a flux, a method of reflowing in a hydrogen atmosphere without using a flux, and the like are adopted.

【0007】半田ボイドが発生する要因の1つに、金属
回路等表面のNiめっき膜に対する半田の濡れ性があ
る。濡れ性が不十分であると、半田ボイドの原因とな
り、逆に強すぎると、半田付け部分以外への半田流れが
原因となるので、金属回路等表面のNiめっき膜に対す
る半田濡れ性には適正値がある。この濡れ性は、目視で
は判断できないような微小な酸化皮膜、有機物の存在に
よって悪化するものであるところ、適切に評価する方法
はない。
One of the factors that cause solder voids is the wettability of solder to the Ni plating film on the surface of a metal circuit or the like. If the wettability is insufficient, it will cause solder voids. Conversely, if it is too strong, it will cause solder flow to areas other than the soldered part. There is value. This wettability is deteriorated by the presence of a minute oxide film or organic matter that cannot be visually determined, but there is no method for evaluating it appropriately.

【0008】そこで、従来は経験に頼り、適度な組成持
つ洗浄水で洗浄してから、半導体素子が半田付けされて
いると考えられる。しかしながら、その洗浄水の組成は
明白にされておらず、また半田ボイドも激減されずに、
半田ボイド率として数%、多い場合には数十%もあった
ので、更なる改善の余地があった。
Therefore, it is considered that the semiconductor element is conventionally soldered after relying on experience and washing with washing water having an appropriate composition. However, the composition of the cleaning water has not been clarified, and the solder voids have not been drastically reduced,
There was room for further improvement because the solder void ratio was several percent, and in many cases several tens percent.

【0009】[0009]

【発明が解決しようとする課題】本発明の目的は、上記
に鑑み、半田ボイドが激減する回路基板を提供すること
である。本発明の目的は、特定組成の電解水を用い、金
属回路等に施されたNiめっき膜面を洗浄することによ
って達成することができる。
SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a circuit board in which solder voids are drastically reduced. The object of the present invention can be achieved by cleaning the surface of the Ni-plated film applied to the metal circuit or the like with electrolyzed water having a specific composition.

【0010】[0010]

【課題を解決するための手段】すなわち、本発明は、p
H10以上、酸化還元電位−800mV以下、電気伝導
度10.0mS/m以上の電解水で、金属回路に施され
たNiめっき膜面を洗浄することを特徴とする回路基板
の半田濡れ性向上方法である。この場合において、洗浄
する前のNiめっき膜面が、1Pa以下の真空中、温度
280±10℃で熱処理されていることが好ましい。ま
た、本発明は、このような方法で洗浄された回路基板で
ある。
That is, the present invention provides p
Method for improving solder wettability of a circuit board, which comprises cleaning the Ni plating film surface applied to a metal circuit with electrolyzed water having H10 or more, oxidation-reduction potential of -800 mV or less and electric conductivity of 10.0 mS / m or more Is. In this case, it is preferable that the Ni-plated film surface before cleaning is heat-treated at a temperature of 280 ± 10 ° C. in a vacuum of 1 Pa or less. Further, the present invention is a circuit board cleaned by such a method.

【0011】[0011]

【発明の実施の形態】以下、更に詳しく本発明を説明す
る。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail below.

【0012】本発明が洗浄の対象している回路基板は、
セラミックス基板に金属回路等が形成され、Niめっき
が施されているものである。このような回路基板には多
くの市販品と先行技術文献があり、本発明ではそれを用
いることができるが、以下、概説する。
The circuit board to be cleaned by the present invention is
A metal circuit or the like is formed on a ceramics substrate and is plated with Ni. There are many commercial products and prior art documents for such a circuit board, which can be used in the present invention, but will be outlined below.

【0013】セラミックス基板の材質は、高信頼性及び
高絶縁性の点から、窒化アルミニウム又は窒化ケイ素が
好ましい。セラミックス基板の厚みは目的によって自由
に変えられる。通常は0.635mmであるが、0.5
〜0.3mm程度の薄物でもよい。高電圧下での絶縁耐
圧を著しく高めたいときには、1〜3mmの厚物が用い
られる。
The material of the ceramic substrate is preferably aluminum nitride or silicon nitride from the viewpoint of high reliability and high insulation. The thickness of the ceramic substrate can be freely changed depending on the purpose. Usually 0.635 mm, but 0.5
A thin material of about 0.3 mm may be used. When it is desired to remarkably increase the withstand voltage under a high voltage, a material having a thickness of 1 to 3 mm is used.

【0014】金属回路等の材質としては、Al、Cu又
はAl−Cu合金であることが好ましい。これらは、単
体ないしはこれを一層として含むクラッド等の積層体の
形態で用いられる。Alは、Cuよりも降伏応力が小さ
く、塑性変形に富み、ヒートサイクルなどの熱応力負荷
時において、セラミックス基板にかかる熱応力を大幅に
低減できるので、Cuよりもセラミックス基板に発生す
るクラックを抑制することが可能となり、高い信頼性回
路基板となる。
The material of the metal circuit or the like is preferably Al, Cu or Al-Cu alloy. These are used in the form of a single body or a laminated body such as a clad including the single layer. Al has a smaller yield stress than Cu, is rich in plastic deformation, and can significantly reduce the thermal stress applied to the ceramic substrate during thermal stress load such as heat cycle. Therefore, it suppresses cracks generated in the ceramic substrate more than Cu. It becomes possible to obtain a highly reliable circuit board.

【0015】金属回路の厚みは、電気的、熱的特性の面
からAl回路の場合は0.4〜0.5mm、Cu回路は
0.3〜0.5mmであることが好ましい。一方、金属
放熱板の厚みは、半田付け時の反りを生じさせないよう
に決定される。具体的には、Al回路の場合は0.1〜
0.4mm、Cu回路は0.15〜0.4mmであるこ
とが好ましい。
The thickness of the metal circuit is preferably 0.4 to 0.5 mm in the case of the Al circuit and 0.3 to 0.5 mm in the case of the Cu circuit in terms of electrical and thermal characteristics. On the other hand, the thickness of the metal heat dissipation plate is determined so as not to cause warpage during soldering. Specifically, in the case of the Al circuit, 0.1 to 0.1
0.4 mm, and the Cu circuit is preferably 0.15 to 0.4 mm.

【0016】セラミックス基板に金属回路等を形成させ
るには、金属板とセラミックス基板とを接合した後、エ
ッチングする方法、金属板から打ち抜かれた回路及び放
熱板のパターンをセラミックス基板に接合する方法等に
よって行うことができる。接合は、活性金属ろう付け法
が好適であるが、DBC法等であってもよい。
In order to form a metal circuit or the like on the ceramic substrate, a method of bonding the metal plate and the ceramic substrate and then etching, a method of bonding the circuit punched from the metal plate and the pattern of the heat dissipation plate to the ceramic substrate, etc. Can be done by The active metal brazing method is suitable for joining, but the DBC method or the like may be used.

【0017】Niめっきが施される前の金属回路等の表
面は、研削、物理研磨、化学研磨等によって平滑化され
ていることが好ましく、表面粗さがRa≦0.2μmで
あることが好ましい。Niめっきは無電解法が好まし
く、これによってファインパターンに対応可能となる。
Niめっき膜厚は2〜8μmであることが好ましい。
The surface of the metal circuit or the like before being plated with Ni is preferably smoothed by grinding, physical polishing, chemical polishing or the like, and the surface roughness is preferably Ra ≦ 0.2 μm. . The Ni plating is preferably an electroless method, which makes it possible to deal with fine patterns.
The Ni plating film thickness is preferably 2 to 8 μm.

【0018】また、Niめっき膜と半田のSn成分との
反応性を高めるため、Niめっき膜を1Pa以下の真空
中、温度280±10℃で熱処理を行い、Niの結晶性
を高めておくこと好ましい。真空度が1Paをこえる
と、Niめっき膜の酸化が著しくなり、Sn成分との反
応性が逆に悪化する。一方、熱処理温度が270℃未満
ではNiの結晶性が十分に高まらず、また290℃超で
はNiめっき膜の硬化が起こり、回路基板に損傷を与え
る恐れがある。熱処理時間は、10〜30分間が好まし
い。
In order to increase the reactivity between the Ni plating film and the Sn component of the solder, the Ni plating film should be heat-treated at a temperature of 280 ± 10 ° C. in a vacuum of 1 Pa or less to enhance the crystallinity of Ni. preferable. When the degree of vacuum exceeds 1 Pa, the Ni plating film is significantly oxidized, and the reactivity with the Sn component is deteriorated. On the other hand, if the heat treatment temperature is lower than 270 ° C., the crystallinity of Ni is not sufficiently enhanced, and if it exceeds 290 ° C., the Ni plating film is hardened, which may damage the circuit board. The heat treatment time is preferably 10 to 30 minutes.

【0019】本発明においては、このNiめっき膜面
を、pH10以上、酸化還元電位−800mV以下、電
気伝導度10.0mS/m以上の電解水で洗浄すること
が大きな特徴である。洗浄形態は、シャワーリング、揺
動浸漬等が可能であるが、シャワーリングが好ましい。
洗浄は、Niめっき後に行ってもよく、半導体素子を半
田付けする直前に行ってもよい。前者には、めっき工程
後に洗浄槽を設ければよい工程上の利点があり、後者に
は、新たな酸化膜や有機物等がNiめっき面に形成・付
着することから回避して半田付けできる利点がある。ま
た、洗浄は両方で行ってもよい。
A major feature of the present invention is that the surface of the Ni plating film is washed with electrolyzed water having a pH of 10 or more, an oxidation-reduction potential of -800 mV or less and an electric conductivity of 10.0 mS / m or more. As the cleaning mode, a shower ring, rocking immersion, etc. are possible, but a shower ring is preferable.
The cleaning may be performed after Ni plating or immediately before soldering the semiconductor element. The former has the process advantage that a cleaning tank can be provided after the plating process, and the latter has the advantage that soldering can be avoided because new oxide films, organic substances, etc. are formed and adhere to the Ni-plated surface. There is. Moreover, you may wash by both.

【0020】電解水のpHが10よりも小さいと、半田
濡れ性に有効なOH基の生成が不十分となる。酸化還元
電位が−800mVよりも高いと、酸化膜の生成を抑制
できにくい。電気伝導度が10.0mS/mよりも小さ
いと、金属イオンを含む微粒子が除去されづらい。電解
水の不純物は、可及的に少ない方が好ましく、例えばC
-やSO4 2-等のマイナスイオン、Cu2+、Na+等の
プラスイオン等の濃度は、それぞれ0.1mg/L以下
であることが望ましい。
If the pH of the electrolyzed water is less than 10, the generation of OH groups effective for solder wettability will be insufficient. When the redox potential is higher than -800 mV, it is difficult to suppress the generation of oxide film. When the electric conductivity is less than 10.0 mS / m, it is difficult to remove the fine particles containing metal ions. It is preferable that the amount of impurities in the electrolyzed water is as small as possible.
The concentration of negative ions such as l and SO 4 2− and positive ions such as Cu 2+ and Na + is preferably 0.1 mg / L or less.

【0021】このような電解水は、電解槽内で食塩や希
塩酸を加え、目的特性となるまで電解を行う、超音波を
照射する等によって製造することができる。また、これ
の市販品、例えば日本アクア社、森永乳業社、旭ガラス
エンジニアリング社等(ウルトラクリーンテクノロジー
Vol.11 No.1 p19 参照)があるの
で、使用することもできる。
Such electrolyzed water can be produced by adding salt or dilute hydrochloric acid in an electrolysis tank, electrolyzing until the desired characteristics are obtained, and irradiating with ultrasonic waves. Further, commercially available products such as Nippon Aqua Co., Morinaga Milk Industry Co., Ltd., Asahi Glass Engineering Co., Ltd. (see Ultra Clean Technology Vol. 11 No. 1 p19) can also be used.

【0022】このようにして洗浄された本発明の回路基
板を用いれば、そのNiめっき膜面に半導体素子を半田
付けしても、その半田ボイド率が1.0%よりも小さい
くなり、モジュールの放熱特性は、Niめっき法が無電
解法であるにもかかわらず格段に向上する。半田ボイド
率の測定は、軟X線探傷装置又は超音波探傷装置を用い
て、自動的に測定することができる。測定装置の一例を
あげれば、軟X線探傷装置(ソフテックス社製「PRO
−TEST 100」)、超音波探傷装置(本多電子社
製「HA−701」)である。
When the circuit board of the present invention washed in this way is used, even if the semiconductor element is soldered to the Ni-plated film surface, the solder void ratio becomes smaller than 1.0%, and the module The heat radiation property of is significantly improved even though the Ni plating method is an electroless method. The solder void fraction can be automatically measured using a soft X-ray flaw detector or an ultrasonic flaw detector. An example of the measuring device is a soft X-ray flaw detector (“PROX” manufactured by Softex).
-TEST 100 ") and an ultrasonic flaw detector (" HA-701 "manufactured by Honda Electronics Co., Ltd.).

【0023】回路基板の金属回路面に半導体素子、金属
放熱板面にベース板を半田付けするにはPb−Sn系の
半田が用られる。半田付けには、フラックスを用いて大
気中又は窒素中でリフローする方法と、フラックスを用
いないで水素雰囲気下でリフローする方法があるが、工
程の簡略化と環境問題の点から後者が望ましい。
To solder the semiconductor element on the metal circuit surface of the circuit board and the base plate on the metal heat sink surface, Pb-Sn solder is used. For soldering, there are a method of reflowing in air or nitrogen using a flux, and a method of reflowing in a hydrogen atmosphere without using a flux, but the latter is preferable from the viewpoint of process simplification and environmental problems.

【0024】以上のように、モジュールの放熱特性はそ
の半田ボイド率が少ない方ほど優れ、特に半田ボイド率
2%を境にして大きく変化する。そこで、回路基板を量
産する場合、以下の簡易試験を行い、試験数10の半田
ボイド率の平均値(+4σ)が2%以下になるように製
造管理することが望ましい。
As described above, the heat dissipation characteristics of the module are better as the solder void rate is smaller, and in particular, the module greatly changes at the solder void rate of 2%. Therefore, when the circuit board is mass-produced, it is desirable to perform the following simple test and perform manufacturing control so that the average value (+ 4σ) of the solder void ratio of the test number 10 is 2% or less.

【0025】すなわち、回路基板の金属回路にPb(9
0%)−Sn(10%)半田片を挟んでシリコンチップ
を置く。半田片寸法は底面積5〜225mm2×厚さ
0.1〜0.5mmとし、シリコンチップ寸法は底面積
5〜225mm2×厚さ0.4〜1.0mmとする。そ
の後、水素雰囲気下、温度150℃までを15〜20℃
/分の速度で、その後は2.3〜2.5℃/分の速度で
昇温して温度350℃±5℃まで高めた後、速やかに室
温下で自然冷却して、半田付けを行う。ここで、150
℃までの昇温速度が15℃/分よりも遅いか、又は35
0℃までの昇温速度が2.3℃/分よりも遅いと、Ni
めっき膜面が酸化され、また350℃までの昇温速度を
2.5℃/分よりも速くすると、半田の溶融が十分でな
くなり、いずれの場合も半田濡れ性を正しく評価するこ
とができない。一方、150℃までの昇温速度を120
℃/分よりも速くするには装置が大がかりとなる。
That is, Pb (9
0%)-Sn (10%) solder pieces are sandwiched between the silicon chips. The solder piece has a bottom area of 5 to 225 mm 2 and a thickness of 0.1 to 0.5 mm, and the silicon chip has a bottom area of 5 to 225 mm 2 and a thickness of 0.4 to 1.0 mm. Then, in a hydrogen atmosphere, the temperature up to 150 ° C is increased to 15 to 20 ° C
/ Min, and then the temperature is raised at a rate of 2.3 to 2.5 ° C / min to raise the temperature to 350 ° C ± 5 ° C, and then quickly cooled naturally at room temperature for soldering. . Where 150
The temperature rising rate to ℃ is slower than 15 ℃ / min, or 35
If the heating rate up to 0 ° C is slower than 2.3 ° C / min, Ni
If the plating film surface is oxidized and the rate of temperature increase up to 350 ° C. is higher than 2.5 ° C./min, the melting of the solder becomes insufficient, and in any case, the solder wettability cannot be correctly evaluated. On the other hand, the rate of temperature increase up to 150 ° C is 120
The equipment becomes large-scale to make it faster than ℃ / min.

【0026】[0026]

【実施例】以下、実施例をあげて更に具体的に本発明を
説明する。
EXAMPLES The present invention will be described in more detail below with reference to examples.

【0027】実施例1〜5 比較例1〜5 セラミックス基板として、窒化アルミニウム基板の市販
品を用意した。大きさは2インチ角×厚み0.635m
mで、レーザーフラッシュ法による熱伝導率175W/
mK、3点曲げ強度420MPaである。Al板は、回
路形成用が2インチ角×厚み0.4mm、放熱板形成用
が2インチ角×厚み0.1mmのものを用いた。
Examples 1 to 5 Comparative Examples 1 to 5 Commercially available aluminum nitride substrates were prepared as ceramic substrates. The size is 2 inches square x thickness 0.635m
m, thermal conductivity of 175 W / by laser flash method
mK, three-point bending strength is 420 MPa. As the Al plate, one having a size of 2 inches square and a thickness of 0.4 mm for forming a circuit and one having a size of 2 inches square and a thickness of 0.1 mm for forming a heat sink were used.

【0028】セラミックス基板の表裏面に、Al板を接
合材(Al96.0%、Cu3.5%、Mg0.5%の
合金箔で厚みは20μm)を介して重ね、カーボン板を
ねじ込んで基板に押しつけできる治具を用い、セラミッ
クス基板に対して垂直方向に均等に加圧した。接合は、
真空又は窒素雰囲気下、温度550〜635℃で加圧を
しながら行った。
On the front and back surfaces of the ceramics substrate, Al plates were stacked with a bonding material (Al 96.0%, Cu 3.5%, Mg 0.5% alloy foil having a thickness of 20 μm) interposed therebetween, and carbon plates were screwed into the substrate. A pressing jig was used to uniformly press the ceramic substrate in the vertical direction. Joining is
It was performed under pressure in a vacuum or nitrogen atmosphere at a temperature of 550 to 635 ° C.

【0029】接合後、エッチングレジストをスクリーン
印刷してFeCl3液でエッチングした。パターンは、
回路、放熱板共に正方形(コーナーRは2mm)で、セ
ラミックス基板中央部に形成(沿面距離1mm)させ
た。ついで、エッチングレジストを剥離した後、市販の
アルカリ系エッチング剤(主成分:苛性ソーダ)を用い
て、Al表面の酸化物除去を行った。
After joining, an etching resist was screen-printed and etched with a FeCl 3 solution. The pattern is
Both the circuit and the heat dissipation plate were square (corner R was 2 mm) and formed in the central portion of the ceramic substrate (creeping distance 1 mm). Then, after removing the etching resist, a commercially available alkaline etching agent (main component: caustic soda) was used to remove oxides on the Al surface.

【0030】以上のようにして製造された回路基板のA
l回路面に、無電解Ni−Pメッキ(奥野製薬社製「ニ
ムデンSX」)を行って、5μm厚のNiめっき膜を形
成させた。一部の回路基板については、1Pa以下の真
空中、温度280℃、時間20分の条件でNiめっき膜
の熱処理を行った。その後、表1に示される各種の電解
水を用い、10分間のシャワー又は浸漬による洗浄を行
った。
A of the circuit board manufactured as described above
Electroless Ni-P plating ("Nimden SX" manufactured by Okuno Chemical Industries Co., Ltd.) was performed on the l circuit surface to form a Ni plating film having a thickness of 5 μm. For some of the circuit boards, the Ni plating film was heat-treated under a vacuum of 1 Pa or less at a temperature of 280 ° C. for 20 minutes. After that, various kinds of electrolyzed water shown in Table 1 were used for cleaning by showering or immersion for 10 minutes.

【0031】これらの回路基板を用いて実際のモジュー
ル製造を想定した以下の半田付けを行い、半田ボイド率
を測定した。それらの結果を表1に示す。その
Using these circuit boards, the following soldering was performed assuming actual module production, and the solder void ratio was measured. The results are shown in Table 1. That

【0032】半田ボイド率の測定 Al回路面にPb(90%)−Sn(10%)半田片
(底面積169mm2×厚さ0.1mm)を挟んでシリ
コンチップ(底面積169mm2×厚さ0.4mm)を
置き、水素雰囲気中にて、温度150℃までを15℃/
分の速度で、その後は2.5℃/分の速度で昇温して温
度350℃まで高めた後、速やかに室温下で自然冷却し
て半田付けを行い、半田ボイド率を軟X線探傷装置(ソ
フテックス社製「PRO−TEST 100」)を用い
て測定し、試験数10の平均値を求めた。
Measurement of Solder Void Ratio A silicon chip (bottom area 169 mm 2 × thickness) with Pb (90%)-Sn (10%) solder pieces (bottom area 169 mm 2 × thickness 0.1 mm) sandwiched between Al circuit surfaces. 0.4 mm) and put it in a hydrogen atmosphere up to a temperature of 150 ° C at 15 ° C /
After increasing the temperature to 350 ° C by raising the temperature at a rate of 1 minute and then at a rate of 2.5 ° C / minute, promptly perform natural cooling at room temperature to perform soldering to determine the solder void rate with soft X-ray flaw detection. It measured using the apparatus ("PRO-TEST 100" by Softex Co., Ltd.), and calculated | required the average value of the test number 10.

【0033】[0033]

【表1】 [Table 1]

【0034】表1の実施例と比較例の対比から、本発明
の洗浄方法によれば、半田ボイドが1%以下に激減する
ことがわかる。また、実施例1と実施例5の対比から、
洗浄する前のNiめっき膜に熱処理が行われていると、
半田ボイドが更に減少することがわかる。
From the comparison between the example and the comparative example in Table 1, it is understood that the cleaning method of the present invention drastically reduces the solder voids to 1% or less. Further, from the comparison between Example 1 and Example 5,
If the Ni plating film before cleaning is subjected to heat treatment,
It can be seen that the solder voids are further reduced.

【0035】[0035]

【発明の効果】本発明によれば、半田ボイドが激減する
回路基板が提供される。
According to the present invention, a circuit board in which solder voids are drastically reduced is provided.

フロントページの続き Fターム(参考) 4K022 AA02 AA42 BA14 DA01 EA01 EA02 4K053 PA07 PA13 QA04 RA07 RA21 SA04 SA06 TA04 TA06 TA18 YA02 YA03 YA04 5E319 AA03 AB06 AC04 AC17 BB02 BB07 CC33 CD01 GG03 5E343 AA23 BB16 BB24 BB28 BB44 BB67 CC38 CC43 CC62 DD51 EE04 EE06 EE15 EE52 ER13 ER33 GG18 Continued front page    F term (reference) 4K022 AA02 AA42 BA14 DA01 EA01                       EA02                 4K053 PA07 PA13 QA04 RA07 RA21                       SA04 SA06 TA04 TA06 TA18                       YA02 YA03 YA04                 5E319 AA03 AB06 AC04 AC17 BB02                       BB07 CC33 CD01 GG03                 5E343 AA23 BB16 BB24 BB28 BB44                       BB67 CC38 CC43 CC62 DD51                       EE04 EE06 EE15 EE52 ER13                       ER33 GG18

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 pH10以上、酸化還元電位−800m
V以下、電気伝導度10.0mS/m以上の電解水で、
金属回路に施されたNiめっき膜面を洗浄することを特
徴とする回路基板の半田濡れ性向上方法。
1. A pH of 10 or more and a redox potential of −800 m.
V or less, electrolyzed water with an electric conductivity of 10.0 mS / m or more,
A method for improving solder wettability of a circuit board, which comprises cleaning a surface of a Ni plating film applied to a metal circuit.
【請求項2】 洗浄する前のNiめっき膜面が、1Pa
以下の真空中、温度280±10℃で熱処理されている
ことを特徴とする請求項1記載の方法。
2. The Ni plating film surface before cleaning is 1 Pa.
The method according to claim 1, which is heat-treated at a temperature of 280 ± 10 ° C. in the following vacuum.
【請求項3】 請求項1又は2の方法によって洗浄され
た回路基板。
3. A circuit board cleaned by the method according to claim 1.
JP2002108856A 2002-04-11 2002-04-11 Circuit board and method for improving solder wettability of circuit board Expired - Fee Related JP3827605B2 (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6874675B2 (en) * 2002-07-12 2005-04-05 Samuel Kenneth Liem Method for manufacturing printed circuit board
CN100440468C (en) * 2005-01-31 2008-12-03 三洋电机株式会社 Method for manufacturing circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6874675B2 (en) * 2002-07-12 2005-04-05 Samuel Kenneth Liem Method for manufacturing printed circuit board
CN100440468C (en) * 2005-01-31 2008-12-03 三洋电机株式会社 Method for manufacturing circuit device

Also Published As

Publication number Publication date
JP3827605B2 (en) 2006-09-27

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