JP2003303914A - Method for manufacturing stacked electronic component - Google Patents

Method for manufacturing stacked electronic component

Info

Publication number
JP2003303914A
JP2003303914A JP2002109686A JP2002109686A JP2003303914A JP 2003303914 A JP2003303914 A JP 2003303914A JP 2002109686 A JP2002109686 A JP 2002109686A JP 2002109686 A JP2002109686 A JP 2002109686A JP 2003303914 A JP2003303914 A JP 2003303914A
Authority
JP
Japan
Prior art keywords
hole
electronic component
holes
conductor
mother
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002109686A
Other languages
Japanese (ja)
Other versions
JP3891026B2 (en
Inventor
Atsushi Kumano
篤 熊野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2002109686A priority Critical patent/JP3891026B2/en
Publication of JP2003303914A publication Critical patent/JP2003303914A/en
Application granted granted Critical
Publication of JP3891026B2 publication Critical patent/JP3891026B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a stacked electronic component having a mother laminate which is not easily distorted and with the surroundings of through-holes which are not to easily cracked or chipped during the punching process. <P>SOLUTION: A punching metal (pin) 21 lands on holes 7, from above the upper surface of a mother laminate 5 with a distortion inhibiting film 11 bonded thereto. Through-holes 10 are formed, penetrating through the mother laminate 5, each corresponding to the position of a hole 7, along virtual lines of division 8. The diameter of the through-hole 10 is longer than the shorter sides, but shorter than the longer sides, of the exposed part of the hole 7, and, as the result, the hole 7 and a conductor 9 filling up the hole 7 are separated electrically into two along the direction of the thickness of the mother laminate 5. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、積層型電子部品、
特に電子機器に内蔵される高周波モジュールなどの積層
型電子部品の製造方法に関する。
TECHNICAL FIELD The present invention relates to a laminated electronic component,
In particular, the present invention relates to a method for manufacturing a laminated electronic component such as a high frequency module built in an electronic device.

【0002】[0002]

【従来の技術】この発明にとって興味ある従来の積層型
電子部品の製造方法の一例として、特開平8−3725
1号公報記載の方法が知られている。この方法は、マザ
ー積層体の仮想分割線上に、導体が充填されている孔を
形成し、この孔を孔明け加工することにより、導体を分
断する。この後、仮想分割線に沿ってマザー積層体を所
定のサイズ毎に切断する。これにより、前記孔の導体を
外部電極として側面に有する積層型電子部品が得られ
る。
2. Description of the Related Art As an example of a conventional method for manufacturing a laminated electronic component, which is of interest to the present invention, JP-A-8-3725
The method described in Japanese Patent No. 1 is known. This method divides the conductor by forming a hole filled with the conductor on the virtual dividing line of the mother laminated body and forming a hole in the hole. After that, the mother laminated body is cut along the virtual dividing line into each predetermined size. As a result, a laminated electronic component having the conductor of the hole as an external electrode on the side surface can be obtained.

【0003】[0003]

【発明が解決しようとする課題】ところで、導体が充填
されている孔を孔明け加工する方法としては、一般的
に、パンチング加工により打ち抜く方法、ドリルによる
方法、もしくは、レーザ加工による方法などがある。そ
のうち、パンチング加工により打ち抜く方法は、加工時
間が短く、しかも、加工面の仕上がり状態が良いため、
量産に適した方法である。
By the way, as a method for forming a hole filled with a conductor, there are generally a punching method, a drilling method, a laser processing method and the like. . Among them, the method of punching by punching is short in processing time and the finished state of the processed surface is good,
This method is suitable for mass production.

【0004】しかしながら、パンチング加工は、打ち抜
きの際に局部的に発生する大きな応力のためマザー積層
体が局部的に伸びたり縮んだりして、歪みが生じるとい
う問題があった。また、パンチングの打ち抜き始め側と
終わり側(特に打ち抜き終わり側)は、応力によって貫
通孔の周囲部にひび割れや欠けが生じ易かった。
However, the punching process has a problem in that the mother laminate locally expands or contracts due to a large stress locally generated during punching, resulting in distortion. Further, on the punching start side and the punching end side (particularly, the punching end side) of the punching, cracks and chips are likely to occur around the through hole due to stress.

【0005】そこで、本発明の目的は、パンチング加工
の際に、マザー積層体が歪みにくく、かつ、貫通孔の周
囲部にひび割れや欠けが生じにくい積層型電子部品の製
造方法を提供することにある。
Therefore, an object of the present invention is to provide a method of manufacturing a laminated electronic component in which a mother laminated body is less likely to be distorted and cracks or chips are less likely to occur in the peripheral portion of a through hole during punching. is there.

【0006】[0006]

【課題を解決するための手段および作用】前記目的を達
成するため、本発明に係る積層型電子部品の製造方法
は、(a)仮想分割線を跨ぐように導体が充填された孔
を有するマザー積層体を形成する工程と、(b)マザー
積層体の表面および裏面の少なくともいずれか一方の面
に歪み抑制用フィルムを貼り付け、該歪み抑制用フィル
ムを貼り付けた面側から、仮想分割線に沿って導体が充
填された孔を電気的に分断するようにパンチング加工す
る工程と、(c)マザー積層体を仮想分割線に沿って所
定のサイズ毎に分割する工程と、を備えたことを特徴と
する。
In order to achieve the above object, the method of manufacturing a laminated electronic component according to the present invention is (a) a mother having a hole filled with a conductor so as to straddle a virtual dividing line. A step of forming a laminated body, and (b) a strain suppressing film is attached to at least one of the front surface and the back surface of the mother laminated body, and the virtual dividing line is applied from the surface side to which the strain suppressing film is attached. Along with the step of punching so as to electrically divide the holes filled with the conductor, and (c) dividing the mother laminated body into predetermined sizes along the virtual dividing line. Is characterized by.

【0007】マザー積層体は、導体が充填された孔を設
けた複数の絶縁性シートを積層することにより形成され
る。あるいは、マザー積層体は、複数の絶縁性シートを
積層した後に一括して孔を形成し、かつ、該孔に導体を
充填することにより形成される。
The mother laminated body is formed by laminating a plurality of insulating sheets having holes filled with conductors. Alternatively, the mother laminate is formed by laminating a plurality of insulating sheets and then collectively forming holes, and filling the holes with a conductor.

【0008】以上の方法により、パンチング加工による
打ち抜きの際に発生するマザー積層体の局部的な伸びや
縮みは、歪み抑制用フィルムによって抑制され、歪みが
生じにくくなる。
By the above method, the local stretch or shrinkage of the mother laminate, which occurs during punching by punching, is suppressed by the strain suppressing film, and strain is less likely to occur.

【0009】また、歪み抑制用フィルムとして光透過性
樹脂フィルムを用いることにより、孔を狙って行うパン
チング加工の位置決めが容易になる。
Further, by using the light-transmissive resin film as the distortion suppressing film, it becomes easy to position the punching process aiming at the holes.

【0010】[0010]

【発明の実施の形態】以下、本発明に係る積層型電子部
品の製造方法の一実施形態について添付の図面を参照し
て説明する。
BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a method of manufacturing a laminated electronic component according to the present invention will be described below with reference to the accompanying drawings.

【0011】図1に示すように、マザー積層体5は、例
えば誘電体や磁性体のセラミックからなる絶縁性グリー
ンシート6を複数枚積み重ねて構成したものである。各
絶縁性グリーンシート6には、レーザ加工やパンチング
加工などにより形成された矩形状の複数の孔7が仮想分
割線8上に形成されている。これらの複数の孔7には、
導電性ペーストからなる導体9がそれぞれ充填される。
そして、導体9が充填された複数の孔7を、絶縁性グリ
ーンシート6の積み重ね方向に連接することによって、
外部電極となるべき導体9が形成される。なお、マザー
積層体5の表裏面5aには矩形状の導体9が露出してお
り、この露出部が外部電極のランド(回り込み部)4a
を構成することになる。
As shown in FIG. 1, the mother laminated body 5 is constructed by stacking a plurality of insulating green sheets 6 made of, for example, dielectric or magnetic ceramics. In each insulating green sheet 6, a plurality of rectangular holes 7 formed by laser processing, punching processing, or the like are formed on the virtual dividing line 8. These plurality of holes 7 include
Each of the conductors 9 made of a conductive paste is filled.
Then, by connecting the plurality of holes 7 filled with the conductor 9 in the stacking direction of the insulating green sheets 6,
A conductor 9 to be an external electrode is formed. A rectangular conductor 9 is exposed on the front and back surfaces 5a of the mother laminated body 5, and the exposed portion is the land (wraparound portion) 4a of the external electrode.
Will be configured.

【0012】また、各絶縁性グリーンシート6のうち特
定の絶縁性グリーンシート6には、導電膜や抵抗膜を印
刷したり、上記の孔7とは別の孔を形成して導電性ペー
ストからなる導体を充填したりすることにより、仮想分
割線8によって区画される個々の積層型電子部品の内部
導体(コンデンサやインダクタなどの内部回路要素)が
形成される。この内部導体と外部電極となるべき導体9
は電気的に接続される。
In addition, a conductive film or a resistance film is printed on a specific insulating green sheet 6 of each insulating green sheet 6, or a hole different from the above-mentioned hole 7 is formed to form a conductive paste. The inner conductor (internal circuit element such as a capacitor or inductor) of each laminated electronic component partitioned by the virtual dividing line 8 is formed by filling the conductor. This inner conductor and the conductor 9 that should be the outer electrode
Are electrically connected.

【0013】次に、このマザー積層体5の表裏面5a
に、歪み抑制用フィルム11を熱圧着や加熱、あるいは
接着剤などで貼り付ける。歪み抑制用フィルム11とし
ては、例えばPET(ポリエチレンテレフタレート)、
PP(ポリプロピレン)、PEN(ポリエチレンナフタ
レート)、PC(ポリカーボネート)、PEEK(ポリ
エーテルエーテルケトン)、PSF(ポリサルホン)、
PES(ポリエーテルサルホン)、PEI(ポリエーテ
ルイミド)などの光透過性樹脂フィルムをベースフィル
ムとする材料を用いることが好ましい。後工程で、孔7
を狙って行うパンチング加工の位置決めが容易になるか
らである。本第1実施形態の場合、歪み抑制用フィルム
11には、厚さ25μmのPETフィルム(さくい性を
有するフィルム)をベースフィルムとした粘着フィルム
を用いた。
Next, the front and back surfaces 5a of this mother laminated body 5
Then, the strain suppressing film 11 is attached by thermocompression bonding, heating, or an adhesive. Examples of the strain suppressing film 11 include PET (polyethylene terephthalate),
PP (polypropylene), PEN (polyethylene naphthalate), PC (polycarbonate), PEEK (polyether ether ketone), PSF (polysulfone),
It is preferable to use a material having a light transmissive resin film as a base film, such as PES (polyether sulfone) and PEI (polyetherimide). In the subsequent process, hole 7
This is because it becomes easy to position the punching process aiming at. In the case of the first embodiment, as the strain suppressing film 11, an adhesive film having a 25 μm-thick PET film (film having scooping property) as a base film was used.

【0014】次に、図2に示すように、歪み抑制用フィ
ルム11を貼り付けた上面側から、孔7を狙って横断面
が円形のパンチング金型(ピン)21にてパンチング加
工を任意の順序で行う。これにより、マザー積層体5を
貫通する貫通孔10が仮想分割線8に沿って、孔7の位
置に対応して形成される。貫通孔10の径は孔7の露出
部の短辺寸法よりも大きくかつ露出部の長辺寸法より小
さく、マザー積層体5の厚み方向に沿って、孔7および
孔7に充填された導体9を二つに電気的に分断する。な
お、パンチング加工する際には、パンチング金型(ピ
ン)の周囲に設けられたストリッパ(図示せず)によ
り、孔明けする部分の周囲を押さえる。
Next, as shown in FIG. 2, punching is performed by a punching die (pin) 21 having a circular cross section aiming at the hole 7 from the upper surface side to which the strain suppressing film 11 is attached. Do in order. As a result, the through hole 10 penetrating the mother laminated body 5 is formed along the virtual dividing line 8 in correspondence with the position of the hole 7. The diameter of the through hole 10 is larger than the short side dimension of the exposed portion of the hole 7 and smaller than the long side dimension of the exposed portion, and along the thickness direction of the mother laminated body 5, the hole 7 and the conductor 9 filled in the hole 7 are formed. Is electrically divided into two. During punching, a stripper (not shown) provided around the punching die (pin) presses around the portion to be punched.

【0015】ここで、セラミックからなるマザー積層体
5は、応力をかけると歪み、応力を開放した後も、残留
応力が所定の緩和時間で応力緩和される粘弾性体であ
る。従って、パンチング加工による打ち抜きの際に、マ
ザー積層体5に発生する局部的な伸びや縮みを、歪み抑
制用フィルム11によって抑制し、残留応力が開放され
る緩和時間を経過後に、歪み抑制用フィルム11を剥が
す。これにより、マザー積層体5の歪みが生じにくくな
る。さらに、導体を打ち抜くパンチングの打ち抜き始め
と打ち抜き終わりの応力によって貫通孔10の周囲部に
生じていたひび割れや欠けを減少させることができる。
Here, the mother laminated body 5 made of ceramic is a viscoelastic body which is distorted when stress is applied and the residual stress is relaxed in a predetermined relaxation time even after the stress is released. Therefore, at the time of punching by punching, the strain suppressing film 11 suppresses local elongation and shrinkage occurring in the mother laminated body 5, and after the relaxation time for releasing the residual stress, the strain suppressing film is passed. Peel off 11. This makes it difficult for the mother laminated body 5 to be distorted. Furthermore, the cracks and chips that have occurred in the peripheral portion of the through hole 10 can be reduced by the stress at the punching start and punching end of punching the conductor.

【0016】また、歪み抑制用フィルム11によって、
マザー積層体5上に塵や切り粉が付着するのを防ぐこと
ができる。さらに、パンチング金型(ピン)21の先端
部が、直接にマザー積層体5の硬い表面に当たるのでは
なく、柔軟な表面を有する歪み抑制用フィルム11に最
初に当たるため、摩耗しにくい。また、歪み抑制用フィ
ルム11を取り付けた状態で取り扱うことにより、マザ
ー積層体5の工程間の搬送用としても利用することがで
きる。
Further, by the strain suppressing film 11,
It is possible to prevent dust and cutting chips from adhering to the mother laminated body 5. Furthermore, since the tip of the punching die (pin) 21 does not directly contact the hard surface of the mother laminated body 5 but first contacts the strain suppressing film 11 having a soft surface, it is hard to wear. Further, by handling the strain suppressing film 11 in the attached state, the mother laminated body 5 can be used for transportation between steps.

【0017】図3に示すように、歪み抑制用フィルム1
1を剥がした後、マザー積層体5の表面に形成されたマ
ーカー(図示せず)によって仮想分割線8をセンシング
し、仮想分割線8に沿ってダイシング(切削)により分
割溝を形成する。なお、分割溝の形成はこれ以外に、カ
ット刃やレーザやスクライブなどを用いたハーフカット
であればよい。レーザやスクライブは、マザー積層体5
の焼成後の方が好ましい。また、マザー積層体5の裏面
の分割溝に対応する位置に、カット刃やレーザやスクラ
イブなどを用いてスリットを形成してもよい。
As shown in FIG. 3, the strain suppressing film 1
After peeling off 1, the virtual dividing line 8 is sensed by a marker (not shown) formed on the surface of the mother laminated body 5, and the dividing groove is formed along the virtual dividing line 8 by dicing (cutting). Other than this, the dividing groove may be formed by half cutting using a cutting blade, a laser, a scribe, or the like. Laser and scribe are used for mother laminated body 5
Is preferred after firing. Further, slits may be formed at positions corresponding to the dividing grooves on the back surface of the mother laminated body 5 by using a cutting blade, a laser, a scribe, or the like.

【0018】さらに、マザー積層体5は焼成される。こ
のように、貫通孔10が形成され、導体9が電気的に分
断されることにより、仮想分割線8によって区画される
個々の積層型電子部品1となる部分は、互いに他のもの
に対して電気的に(機能的に)独立した状態となる。
Further, the mother laminated body 5 is fired. In this way, the through holes 10 are formed, and the conductors 9 are electrically divided, so that the portions that become the individual laminated electronic components 1 defined by the virtual dividing lines 8 are different from each other. It is electrically (functionally) independent.

【0019】この後、内部回路素子と電気的に接続され
る他の電子部品(図示せず)をマザー積層体5の裏面上
に搭載し、分割溝を利用してマザー積層体5を所定のサ
イズ毎に分割(ブレイク)し、図4に示すように、個々
の積層型電子部品1を得る。このとき、二つに分断され
た貫通孔10により、積層型電子部品1には凹部3が形
成されるとともに、その内周面の中央部に、積層体の厚
み方向に沿って、積層体の表面から裏面に延びるように
帯状に外部電極4が露出する。
Thereafter, another electronic component (not shown) electrically connected to the internal circuit element is mounted on the back surface of the mother laminated body 5, and the mother laminated body 5 is formed in a predetermined shape by utilizing the dividing groove. Dividing (breaking) for each size, individual laminated electronic components 1 are obtained as shown in FIG. At this time, the through hole 10 divided into two forms the concave portion 3 in the multilayer electronic component 1, and the central portion of the inner peripheral surface of the concave portion 3 extends along the thickness direction of the multilayer body. The external electrode 4 is exposed in a strip shape so as to extend from the front surface to the back surface.

【0020】以上の方法によれば、パンチング加工によ
る打ち抜きの際に発生するマザー積層体5の局部的な伸
びや縮みは、歪み抑制用フィルム11によって抑制さ
れ、マザー積層体5の歪みを低減することができる。図
5の(A)に示したグラフは、サイズが135mm×1
35mmのマザー積層体5の表裏面5aに歪み抑制用フ
ィルム11を貼り付け、貫通孔10を形成した後の所定
の部分の歪み量を測定したグラフである。貫通孔10を
形成する前の各部分の位置は一点鎖線で表示している。
最大歪み量は±21μmであった。一方、歪み抑制用フ
ィルム11を貼り付けないで、貫通孔10を形成した後
の歪み量を測定したグラフを図5の(B)に示す。最大
歪み量は±66μmであった。
According to the above method, the local extension or contraction of the mother laminated body 5 which occurs during punching by punching is suppressed by the strain suppressing film 11 and the distortion of the mother laminated body 5 is reduced. be able to. The graph shown in FIG. 5A has a size of 135 mm × 1.
It is a graph which measured the amount of strain of a predetermined portion after attaching the distortion control film 11 to the front and back surfaces 5a of the 35 mm mother laminated body 5 and forming the through holes 10. The position of each portion before the through hole 10 is formed is indicated by a chain line.
The maximum strain amount was ± 21 μm. On the other hand, a graph obtained by measuring the amount of strain after forming the through hole 10 without attaching the strain suppressing film 11 is shown in FIG. The maximum strain amount was ± 66 μm.

【0021】また、歪み抑制用フィルム11には、例え
ば、JIS C−2318の評価条件の下で、引っ張り
強度が3(kgf/15mm幅)以上の粘着剤付きフィ
ルムを用いることが好ましい。図6に示すように、引っ
張り強度が3(kgf/15mm幅)以下だと、歪み抑
制効果が著しく低下し、マザー積層体5の歪みを抑えら
れないからである。
For the strain suppressing film 11, it is preferable to use a film with an adhesive having a tensile strength of 3 (kgf / 15 mm width) or more under the evaluation conditions of JIS C-2318. This is because, as shown in FIG. 6, when the tensile strength is 3 (kgf / 15 mm width) or less, the strain suppressing effect is significantly reduced, and the strain of the mother laminated body 5 cannot be suppressed.

【0022】なお、本発明に係る積層型電子部品の製造
方法は、前記実施形態に限定するものではなく、その要
旨の範囲内で種々に変更することができる。例えば、マ
ザー積層体5が有している仮想分割線8上の孔7は、そ
の内側に導体が充填されているものの他に、孔7の内周
壁面にのみ、めっきや塗布などの方法により導体が形成
されているものであってもよい。
The method for manufacturing a laminated electronic component according to the present invention is not limited to the above embodiment, but can be variously modified within the scope of the gist thereof. For example, the holes 7 on the virtual dividing line 8 of the mother laminated body 5 are not only filled with a conductor inside thereof, but also only the inner wall surface of the holes 7 is formed by plating or coating. The conductor may be formed.

【0023】また、歪み抑制用フィルム11はマザー積
層体5の表裏両面に貼り付ける必要はなく、いずれか一
方の面にのみ貼り付けた後、貼り付けた面側から孔7を
パンチング加工して貫通孔10を形成してもよい。
The strain suppressing film 11 does not need to be attached to both front and back surfaces of the mother laminated body 5, and is attached only to one of the surfaces, and then the holes 7 are punched from the attached surface side. The through hole 10 may be formed.

【0024】さらに、前記実施形態では、外部電極がマ
ザー積層体の表裏面まで延びるように形成されている
が、積層体に搭載される他の部品の実装面をより大きく
確保するために、外部電極が裏面に届かないように、裏
面および裏面近傍の絶縁性グリーンシートには孔を形成
しないようにしてもよい。
Further, in the above embodiment, the external electrodes are formed so as to extend to the front and back surfaces of the mother laminated body. However, in order to secure a larger mounting surface for other parts mounted on the laminated body, No holes may be formed in the back surface and in the insulating green sheet near the back surface so that the electrodes do not reach the back surface.

【0025】また、前記実施形態では、絶縁性グリーン
シート1枚毎に矩形状の孔を形成しているが、マザー積
層体を形成した後に、積み重ね方向に一括で矩形状の孔
をレーザ加工やパンチング加工などにより形成し、その
孔に導電性ペーストを充填してもよい。そして、導電性
ペーストが充填された孔よりも小さい径を有する別の孔
をパンチング加工し、実施形態と同様に電気的に分断し
てもよい。なお、歪み抑制用フィルムは最初の孔の加工
時から貼り付けておいてもよいし、2回目の導体の分断
のときから貼り付けてもよい。また、最初の孔と2回目
の孔の形状は、最初の孔より2回目の孔の方が、短辺お
よび長辺のいずれかが小さく、かつ、導体が電気的に分
断されるような形状であれば特に限定されない。
Further, in the above-mentioned embodiment, the rectangular holes are formed for each one of the insulating green sheets. However, after forming the mother laminated body, the rectangular holes are collectively laser-processed in the stacking direction. The holes may be formed by punching and the holes may be filled with a conductive paste. Then, another hole having a diameter smaller than that of the hole filled with the conductive paste may be punched and electrically separated as in the embodiment. The strain suppressing film may be attached from the time of processing the first hole, or may be attached from the time of dividing the conductor for the second time. Further, the shapes of the first hole and the second hole are such that the second hole is smaller than the first hole in either the short side or the long side, and the conductor is electrically divided. It is not particularly limited as long as it is.

【0026】[0026]

【発明の効果】以上の説明で明らかなように、本発明に
よれば、パンチング加工による打ち抜きの際に発生する
マザー積層体の局部的な伸びや縮みは、歪み抑制用フィ
ルムによって抑制されマザー積層体の歪みを低減するこ
とができる。
As is apparent from the above description, according to the present invention, the local elongation and shrinkage of the mother laminate, which occurs during punching by punching, is suppressed by the strain suppressing film. Body strain can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る積層型電子部品の製造方法の一実
施形態を示す斜視図。
FIG. 1 is a perspective view showing an embodiment of a method for manufacturing a multilayer electronic component according to the present invention.

【図2】図1に続く製造工程を示す斜視図。FIG. 2 is a perspective view showing the manufacturing process following FIG.

【図3】図2に続く製造工程を示す要部拡大斜視図。FIG. 3 is an enlarged perspective view of essential parts showing the manufacturing process following FIG. 2;

【図4】図3に続く製造工程を示す斜視図。FIG. 4 is a perspective view showing a manufacturing process that follows FIG. 3;

【図5】貫通孔形成後のマザー積層体の歪み量を示すグ
ラフ。
FIG. 5 is a graph showing the amount of strain of the mother laminated body after forming the through holes.

【図6】歪み抑制用フィルムの引っ張り強度とマザー積
層体の歪み量との関係を示すグラフ。
FIG. 6 is a graph showing the relationship between the tensile strength of the strain suppressing film and the strain amount of the mother laminate.

【符号の説明】[Explanation of symbols]

1…積層型電子部品 4…外部電極 5…マザー積層体 7…孔 8…仮想分割線 9…導体 10…貫通孔 11…歪み抑制用フィルム 12…導体 1 ... Multilayer electronic component 4 ... External electrode 5: Mother laminate 7 ... hole 8 ... Virtual dividing line 9 ... conductor 10 ... Through hole 11 ... Distortion suppressing film 12 ... conductor

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E317 AA22 BB04 BB11 CC25 CD21 CD31 CD32 GG05 5E346 AA12 AA15 AA38 AA41 BB16 CC17 CC31 CC60 DD02 EE24 FF18 FF42 GG03 GG05 GG08 HH33    ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5E317 AA22 BB04 BB11 CC25 CD21                       CD31 CD32 GG05                 5E346 AA12 AA15 AA38 AA41 BB16                       CC17 CC31 CC60 DD02 EE24                       FF18 FF42 GG03 GG05 GG08                       HH33

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 仮想分割線を跨ぐように導体が充填され
た孔を有するマザー積層体を形成する工程と、 前記マザー積層体の表面および裏面の少なくともいずれ
か一方の面に歪み抑制用フィルムを貼り付け、該歪み抑
制用フィルムを貼り付けた面側から、仮想分割線に沿っ
て前記導体が充填された孔を電気的に分断するようにパ
ンチング加工する工程と、 前記マザー積層体を仮想分割線に沿って所定のサイズ毎
に分割する工程と、 を備えたことを特徴とする積層型電子部品の製造方法。
1. A step of forming a mother laminate having a hole filled with a conductor so as to straddle a virtual dividing line, and a strain suppressing film on at least one of a front surface and a back surface of the mother laminate. A step of sticking and punching so as to electrically divide the hole filled with the conductor along the virtual dividing line from the surface side to which the strain suppressing film is stuck, and the mother laminate is virtually divided A method of manufacturing a multilayer electronic component, comprising: dividing into predetermined sizes along a line.
【請求項2】 前記マザー積層体は、導体が充填された
孔を設けた複数の絶縁性シートを積層することにより形
成されることを特徴とする請求項1に記載の積層型電子
部品の製造方法。
2. The laminated electronic component according to claim 1, wherein the mother laminated body is formed by laminating a plurality of insulating sheets having holes filled with conductors. Method.
【請求項3】 前記マザー積層体は、複数の絶縁性シー
トを積層した後に一括して孔を形成し、かつ、該孔に導
体を充填することにより形成されることを特徴とする請
求項1に記載の積層型電子部品の製造方法。
3. The mother laminate is formed by laminating a plurality of insulating sheets and then collectively forming holes, and filling the holes with a conductor. A method for manufacturing a multilayer electronic component according to item 1.
【請求項4】 前記歪み抑制用フィルムが光透過性樹脂
フィルムであることを特徴とする請求項1〜請求項3の
いずれかに記載の積層型電子部品の製造方法。
4. The method for manufacturing a laminated electronic component according to claim 1, wherein the strain suppressing film is a light transmissive resin film.
JP2002109686A 2002-04-11 2002-04-11 Manufacturing method of multilayer electronic component Expired - Fee Related JP3891026B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002109686A JP3891026B2 (en) 2002-04-11 2002-04-11 Manufacturing method of multilayer electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002109686A JP3891026B2 (en) 2002-04-11 2002-04-11 Manufacturing method of multilayer electronic component

Publications (2)

Publication Number Publication Date
JP2003303914A true JP2003303914A (en) 2003-10-24
JP3891026B2 JP3891026B2 (en) 2007-03-07

Family

ID=29393081

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002109686A Expired - Fee Related JP3891026B2 (en) 2002-04-11 2002-04-11 Manufacturing method of multilayer electronic component

Country Status (1)

Country Link
JP (1) JP3891026B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011159705A (en) * 2010-01-29 2011-08-18 Kyocera Kinseki Corp Method of manufacturing element mounting member wafer, and method of manufacturing element mounting member

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011159705A (en) * 2010-01-29 2011-08-18 Kyocera Kinseki Corp Method of manufacturing element mounting member wafer, and method of manufacturing element mounting member

Also Published As

Publication number Publication date
JP3891026B2 (en) 2007-03-07

Similar Documents

Publication Publication Date Title
US9240333B2 (en) Manufacturing method for monolithic ceramic electronic component
US9839135B2 (en) Method of producing electronic components and method of producing substrate-type terminals
JP5971447B2 (en) Manufacturing method of ceramic substrate and module component
WO2007060788A1 (en) Process for producing multilayer ceramic substrate
JP2007095927A (en) Wiring board and its production method
JP2011151281A (en) Method of manufacturing electronic component
JP5282739B2 (en) Electronic component and mounting method thereof
JP2003303914A (en) Method for manufacturing stacked electronic component
JP2008060096A (en) Multiple-patterning wiring board, and manufacturing method thereof
JP6165722B2 (en) Method for manufacturing a printed circuit board and overall panel for a printed circuit board
JP2012089818A (en) Laminate type ceramic electronic component manufacturing method
JPH10200008A (en) Multilayer circuit board and manufacture thereof
JP3211609B2 (en) Multilayer electronic component and method of manufacturing the same
JP2006156502A (en) Rigid flexible printed wiring board and its manufacturing method
JP2007258264A (en) Assembled substrate, and manufacturing method of individual substrate
US20240087813A1 (en) Electronic component and method for manufacturing the same
JP2009188096A (en) Manufacturing method for ceramic laminated wiring board
JP2003273272A (en) Ceramic board and its manufacturing method
JP2007305886A (en) Multipiece substrate
JP2004079945A (en) Ceramic electronic component aggregate
JP2007043061A (en) Multi-pattern wiring board
JP6258679B2 (en) Wiring board and electronic device
JPH04261084A (en) Printed substrate and cutting-off method thereof
JP2005101045A (en) Circuit board and manufacturing method thereof
JP2003273483A (en) Flexible circuit board and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050317

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20061106

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20061114

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20061127

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 3891026

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101215

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101215

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111215

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111215

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121215

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131215

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees