JP2003288795A - Semiconductor memory device post-repair circuit and device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a post-repair circuit and method for a semiconductor device. <P>SOLUTION: The ability to repair defective cells in a memory array by replacing those cells with redundant cells, is improved using a redundant memory line control circuit 25i, 23i that empolys two types of redundancy programming. At least one memory line can be programmed subsequent to device packaging ('post repair') of the semiconductor device using commands that cut electric fuses. The redundant memory lines that are reserved for post repair are selectable among the same redundant memory lines that can be programmed using laser fuses. This allows all redundant memory lines to be available for laser repair, if needed, but also allows a redundant memory line to be selected for post repair after it has been determined that the redundant memory line is defect-free. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair structure and a repair method for a semiconductor memory device, and more particularly to a post repair structure and method.

[0002]

2. Description of the Related Art Semiconductor memory devices such as DRAMs
(Dynamic Random Access Memory) includes a large number of memory cells arranged in a row / column array. Each memory cell normally stores 1 bit of information. The array includes row signal lines (row lines) and column signal lines (column lines) arranged orthogonal to the row signal lines. The memory cell is located at each intersection of the row line and the column line.
A corresponding memory cell is accessed by addressing an array row line and an array column line connected to a specific memory cell.

In a semiconductor memory device, every memory cell, row line, and column line in a memory line must operate normally. In reality, the main memory cell array on a given wafer is not 100% operational. Therefore, most semiconductor devices are designed to have a relatively small number of redundant memory cell arrays that can replace some defective cells.

According to one conventional design method, a redundant array is composed of redundant memory cell columns. According to this method, each of the redundant memory cells is connected to a redundant column line which intersects the main memory cell array row line. Each redundant column line can replace a main memory cell array column that is considered to have one or more defective cells. Each time the main array column is addressed, the redundancy control block compares the column address with the defective column address. Each time a defective column is addressed, the redundancy control block selects the redundant column associated with (or combined with) the defective column instead of the defective column.

Redundancy schemes are also used that replace defective rows with redundant rows. Some semiconductor devices include redundant rows and columns in associated circuitry.

Prior to using the redundancy control block and its associated redundant columns / rows, the defective line address must be programmed into the control block. The redundancy control block includes a fuse block for programming. When the semiconductor memory device is in a wafer state,
Test the main memory array to determine the location of defective cells. Assuming column replacement, redundancy control blocks and redundant columns are selected to replace a given defective column. The address of the defective column is set in the redundancy control block to indicate the column address by selectively cutting the fuse in the fuse block. Fuses are typically physically blown using a laser beam.

Although most memory array defects can be detected during a test process in a wafer state, some defects occur after packaging a semiconductor device. Whether the semiconductor device becomes a good product or a defective product is determined depending on whether the memory array can be repaired (repaired) after packaging for the defect. The repair of the array after packaging is called post repair.

Although post-repair redundancy has the advantage that defects that occur during packaging can be repaired, the post-repair redundancy control block and its associated electrical programming circuits are redundantly controlled by laser blown fuses. Occupies more circuit area than
There is a disadvantage in terms of cost.

[0009]

Therefore, the technical problem to be solved by the present invention is to harmonize the advantages of the fuse programming of the wafer state (for example, laser cutting) and the advantages of the post-repair programming to improve the repair efficiency. A semiconductor memory device including a dual mode redundancy circuit capable of improving

Another technical problem to be solved by the present invention is to combine the advantages of wafer state (for example, laser cutting) fuse programming with the advantages of post repair programming to improve repair efficiency. A method of repairing an apparatus is provided.

[0011]

One aspect of the present invention is a semiconductor memory device including a dual mode redundancy circuit.
The dual mode redundancy circuit includes a plurality of redundant memory lines. Each redundant memory line is associated with one redundant control block. Most of the redundancy control blocks include laser fuse blocks that are programmed only before packaging the semiconductor device. At least one of the redundancy control blocks includes an electrically programmable fuse block that is programmed only after packaging the semiconductor device. The device thus enables a dual-cycle repair method. With the dual-cycle repair method, most repairs are done at the wafer level using more economical laser fuse blocks, and a small number of electrical fuse blocks (e.g., packaging-related defects occur). If used) will be used after packaging in post repair mode.

The repair scheme has some redundant memory lines dedicated to laser repair and some redundant memory lines dedicated to post repair. If the redundant memory line itself dedicated to post repair is defective, post repair is impossible. Post-repair is not possible even if the redundant memory lines for defect-free laser repair remain unused.

Therefore, another aspect of the present invention is a semiconductor memory device including a dual mode redundancy circuit for improving post repair efficiency. The circuit is a wafer state address store (ie, a laser fuse block).
To one redundant line. In the second configuration, the circuit couples post repair address stores (ie, electrical fuse blocks) with the same redundant memory line. Therefore, the semiconductor memory device adopting the dual mode redundancy has a repair degree of freedom. For example, each redundant memory line is associated with a laser fuse block during wafer condition testing. One defect-free redundant memory line is allocated for post repair during testing. The assigned redundant memory line is combined with a post repair address store to enable post repair.

According to such a method, the semiconductor memory device comprises a plurality of redundant memory lines, each of which is coupled to one laser fuse / comparator. The main and redundant memory lines are tested to see if each line is good or bad. For each defective main memory line, the laser fuse / comparator is coupled to one of the defect-free redundant memory lines assigned to replace the defective main memory line. If there is a defect-free redundant memory line after replacement of the defective memory line, the remaining defect-free redundant memory line is allocated for post repair. The redundant memory line for the assigned post repair is coupled with a post repair comparator instead of the laser fuse / comparator coupled with the redundant memory line for the assigned post repair.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS For a full understanding of the present invention and its operational advantages and objectives achieved by the practice of the present invention, the accompanying drawings and accompanying drawings that illustrate preferred embodiments of the invention are shown: You must refer to the contents described in.

Hereinafter, the present invention will be described in detail by explaining preferred embodiments of the present invention with reference to the accompanying drawings. The same reference numbers presented in the figures refer to similar components.

FIG. 1 is a block diagram showing a semiconductor memory device 20 according to one embodiment of the present invention. The semiconductor memory device 20 shown in FIG. 1 is a synchronous DRAM (SDRA).
M). The main cell array 30 and the redundant column cell array 32 are operated by row and column circuit units. The column circuit unit includes a sense amplifier 34 and a column decoder 50. The column decoder 50 uses each column address CA
A column line to which data is written or read is selected. In the column decoder 50, the redundant memory line control circuit 100 determines a redundant column that replaces the main column according to the column address CA and the column selection enable signal CSLEN.

The row circuit section includes a row decoder 40 and a row address multiplexer 42. Row decoder 40
Selects a row (word) line activated for each row address RA. Low select enable signal RSL
EN indicates when RA is valid. Semiconductor memory device 20
Redundant row lines and circuit parts are not shown in FIG.
Redundant row lines and circuit units similar to the redundant column cell array 32 and the redundant memory line control circuit 100 may be provided. The row address multiplexer 42 receives the external row address output from the address register 80 and the refresh row address output from the refresh counter 46 controlled by the refresh controller 44, and sets one of them as a row address RA. Output.

Circuit inputs and outputs are done through three sets of registers. The command word register 70 receives command word signals such as word line activation, read, write, precharge, auto-refresh, and mode register application from the external memory controller through the command word bus CMD. The address register 80 receives the address signal ADD [0: m] from the memory controller through the address bus. The data I / O register is connected to the bidirectional data lines DQ [0: w].

The command word decoder 60 interprets the received command word to generate appropriate control signals for other memory device blocks. Mode register set (Mode Register)
erSet: MRS) 62 is an address bus ADD when a mode register application command is received on the CMD bus.
Through the device setting signal. In general, MRS is SDRA such as burst type, burst length, and latency.
A register used to define the operating parameters of M. In the preferred embodiment, one of the functions of MRS is
ADD if a particular command is received on the CMD bus
Setting the fuse part in the electrical fuse box by the address provided on the bus.

Although the memory device to which the present invention is applicable may have many advanced characteristics, the above-mentioned characteristics are basic characteristics common to most SDRAMs capable of supporting one embodiment of the present invention. Features of the semiconductor memory device 20 that are particularly relevant to embodiments of the present invention are described in detail below.

FIG. 2 is a block diagram of a basic dual mode redundant column control circuit 100 according to the first embodiment of the present invention. Referring to FIG. 2, the dual mode redundant column control circuit 100 includes an electrical fuse box 110,
Address comparator 120, electrical redundancy control block 13
1, laser redundancy control blocks 132 to 13n (n is an integer) and RCSL generator 14i (i = 1 to n).

The redundant column control circuit 100 controls access to n redundant columns in the redundant column cell array (32 in FIG. 1). When the RCSL generator 14i generates the corresponding redundancy column selection signal RCSLi (i = 1 to n), one of the n redundant columns is selected instead of the defective main array column.

Each RCSL generator 14i (i = 1 to n) is activated in response to a corresponding RCSL enable signal RCSLENi (i = 1 to n) output from the redundancy control block. Each RCSL generator 14i (i = 1 to n)
Can be implemented using two inverters (not shown) connected in series.

FIG. 3 shows an electrical redundancy control block 131.
13 is a detailed circuit diagram of the laser redundancy control blocks 132 to 13n. Each laser redundancy control block 132
13n includes a laser fuse box and address comparator, ie, laser fuse / comparator 150. The laser beam blows selected fuses in the laser fuse box during the wafer stage repair operation. Then, the laser fuse / comparator 150 compares the column address CA with the defective column address stored in the laser fuse box to determine the column address C.
If A matches the stored address, OUT is output. NAND with inverter 154 connected in series
Gate 152 ANDs OUT with CSLEN to produce RCSLENi. If RCSLENi is generated, the redundant column i is selected.

The electrical redundancy control block 131 is a NAN.
Inverter 1 connected in series with D gate 160
62, and logical product (AND) of EN and CSLEN
Calculate to produce RCSLEN1. If RCSLEN1 occurs, redundant column 1 is selected.

EN is the output of the address comparator 120 and is generated when CA matches ECA (see FIG. 2). ECA is a defective column address electrically stored in the electrical fuse box 110. Therefore,
The redundant column lines 2 to n are programmed only in the wafer stage repair process, while the redundant column 1 is programmed in any stage, that is, in the post repair process.

4 and 5 show the electrical fuse box 1
10 shows an example. Referring to FIG. 4, the electrical fuse box 110 includes a plurality of electrical fuse parts 31a and 31i (i = 0 to 0) having buffered outputs.
k) is included. Each electric fuse unit stores 1-bit data. The fuse unit 31a stores the OUTa bit. OUTa is buffered into a master access signal MA indicating whether the electrical fuse box 110 has been programmed. Fuse portion 31i (i = 0
~ K) store OUTi. OUTi is buffered into electrical column address signal bits ECAi.

The MRS (62 in FIG. 1) is programmed into the fuse box 110 in response to an external command word.
This produces RSA, MRSCA0 to MRSCAk. Each electrical fuse portion is initially assembled in the first state, eg, to indicate a non-set address bit.
When the MRS programming input is applied, the corresponding electrical fuse portion is set to the second state, that is, to indicate the set address bit. Therefore, to program the fuse box 110, the MRS 62 applies the corresponding column address to MRSCA0-k to program the column address to be repaired, and activates the MRSA to program the master access bit.

FIG. 5 shows an electrical fuse section 31i (i =
It is a detailed circuit diagram which shows one implementation example of a, 0-k). Each of the electric fuse units 31a and 31i (i = 0 to k) has a first
And second fuse elements F1 and F2 and first to fifth NMOSs
The transistors N1 to N5 and the first and second PMOS transistors P1 and P2 are included.

The first and second NMOS transistors N1,
The drain of N2, the drain of the first PMOS transistor P1, the gate of the second PMOS transistor P2, and the third
The gate of the NMOS transistor N3 has a first node 411.
Commonly connected to. The gate of the first PMOS transistor P1, the gate of the second NMOS transistor N2, the drains of the third and fourth transistors N3 and N4, and the drain of the second PMOS transistor P2 are commonly connected to the second node 412. The signal of the second node 412 becomes the output signal OUT. The sources of the NMOS transistors are connected to the ground, and the sources of P1 and P2 are connected to VDD through the fuses F1 and F2, respectively. The drain of N5 is connected to the source of P1.

The fuse portion 31i makes the resistance of the fuse F2 larger than that of the fuse F1. Therefore, if both fuses are not blown, the node 412 is driven in the logic low state and the node 411 is driven in the logic high state when power is supplied to the fuse portion.

First and fourth NMOS transistors N1,
The normal state of the gate of N4 is the logic low state.
The input signal MRS1 is input. First input signal MRS1
Is a signal necessary for checking whether or not the fuse F1 is blown, and will be briefly described later.

The second input signal MRS2 is input to the gate of the fifth NMOS transistor N5. Second input signal M
RS2 is used to electrically disconnect the first fuse element F1. When the second input signal MRS2 goes high, the fifth NMOS transistor N5 is turned on and an overcurrent flows through the first fuse element F1. Therefore, the first
The fuse element F1 burns and is electrically cut. When the first fuse element F1 is cut off, the source of the first PMOS transistor P1 is turned to a low potential by the fifth NMOS transistor N5 which is turned on, and thus
The voltage of node 411 drops. As the voltage of the first node 411 decreases, the second PMOS transistor P2 is turned on and the voltage of the second node 412 increases.
As the voltage of the second node 412 increases, the second NM
The OS transistor N2 is further turned on and the voltage of the first node 411 further decreases. Through this process, the output signal OUT eventually becomes high level.

After programming, the first input signal MRS1
Can be used to determine whether the fuse F1 has been completely blown by the application of the second input signal MRS2. In test mode, MRS1 momentarily goes to a logic high state, causing both nodes 411 and 412 to go to a logic low state. If fuse F1 was not blown, node 411 returns to a high state when MSR1 is restored to a low state.

The repaired address line is tested by application / non-application of MRS1. If the test is unsuccessful, it means that one or more fuses were not completely blown and thus the redundant column could not successfully replace the defective column. In that case, the electrical programming and test process may be repeated to retry the fuse blow.

FIG. 6 is a circuit diagram showing in detail an implementation of the address comparator of FIG. The address comparator 120 is
A large number of comparators 51i (i = 0 to k) and a large number of AND gates 520, 522, 524 are included. Each AND gate is N
It is composed of an AND gate and an inverter.

Each comparator 51i (i = 0 to k) executes a 1-bit XNOR (exclusive-NOR) function. Each comparing unit 51i (i = 0 to k) receives the electrical repair address bit ECAi (i = 0 to k) and the corresponding bit CAi (i = 0 to k) of the external address and compares the bits for comparison. . If both bits are the same, a high level signal is output, and if both bits are different, a low level signal is output.

The signal output from each comparator 51i (i = 0 to k) and the master signal MA are logically ANDed and output as an electrical repair activation signal EN. Therefore, when all the output signals output from the comparison units 51i (i = 0 to k) are at the high level, the electrical repair activation signal EN is activated to the high level.

As shown and described in FIGS. 2-6,
The redundant column control block uses one redundant column for post-repair, and thus improves the repair capability as compared to the laser fuse only redundancy scheme. at the same time,
This embodiment is based on the recognition that most array defects are present and can be detected during the wafer stage repair process.
Most redundant columns are driven by more economical laser fuse control circuits.

According to the embodiment shown in FIG. 2, if a defect occurs in the redundant column associated with the electrical redundancy control block, repair is impossible. That is, if this redundant column is defective, post-repair is impossible even if one or more redundant columns of the redundant columns 2 to n have no defect and are not used. On the other hand, according to the second embodiment, the possibility of carrying out post repair is improved by selecting one of several redundant columns related to the electrical redundancy control signal. Preferably, after wafer assembly, defect-free redundant columns are allocated for post repair. Also preferably, each defect-free redundant column is also assigned to a laser repair.

FIG. 7 is a block diagram showing a redundant column control circuit 200 according to the second embodiment. 2 is similar to FIG. 2 in various aspects, but FIG. 7 shows the post repair control blocks 251 to 25n and the other redundancy control blocks 231 to 2n.
3n, and the control signals are different. Such a difference will be described later with reference to FIGS. Briefly, each redundancy control block 23i has a laser fuse function, but is also configured to respond to the electrical repair activation signal EN. Therefore, there is no redundant column implemented only for post repair, any redundant column may be used for laser repair, and defect-free redundant columns can be assigned to post repair electrical fuse circuits after wafer assembly if necessary. To be Such flexibility allows efficient use of defect-free redundant columns at the wafer and post repair stages.

Similar to the redundant column control circuit of FIG. 2, the control circuit 200 of FIG. 7 includes an electrical fuse box 210 that can be set to a desired post repair column address using MRS. The address comparator 220 compares the address ECA programmed in the electrical fuse box 210 with the column address CA. If the programmed address ECA matches the external address CA, the address comparator 220 receives the electrical repair activation signal EN.
Is activated to a high level.

In FIG. 2, the electrical redundancy control block 13
1 only receives EN from the electrical repair address comparator 120, whereas in FIG. 7, each redundancy control block 2
31 to 23n receive EN from the address comparator 220. Each redundancy control block 23i also receives a column address CA and a control signal CSi from the corresponding post repair control block 25i. The control signal CSi determines whether the redundancy control block 23i responds to EN or uses CA in combination with the laser fuse / comparator.
Typically, one of the post repair control blocks 25i
Only the block fuse will be blown. When the fuse in the post repair control block 25i is blown, the corresponding control signal CSi is activated, which means that the corresponding redundant column can be used for post repair.

FIG. 8 is a drawing showing the redundancy control block in detail. The redundancy control block 23i has a corresponding RC
The redundancy activation signal RC is sent to the SL generator 24i (i = 1 to n).
SLENi (i = 1 to n) is output. Each redundancy control block 23i includes a laser repair processing part 610 for laser repair and a post repair processing part 620 for post repair.

The laser repair processing part 610 includes a laser fuse box 611, an address comparison unit 612 and a first logic unit 613.

Laser fuse box 611 contains a number of laser blown fuses. The laser fuse is an address LC that specifies a column in which a defective cell is generated by being selectively cut by a laser.
Program to A.

The address comparison unit 612 is the address comparator 2
Similar to 20, the output signal OUT that is activated if the address LCA programmed in the laser fuse box 611 and the address CA applied from the outside are the same.
Cause

The first logic unit 613 is the address comparison unit 61.
The output signal OUT output from 2 and the control signal CSi are ORed to output the first logic signal TS1. The control signal CSi is, as described above, the post repair control block 2
The signal is output from 5i, and when it is at the first level (here, high level), post repair is instructed.

The post repair processing part 620 includes an inverter 621 and a second logic unit 622. Inverter 62
1 produces the inverted signal CSi # of CSi. Second logic unit 6
A second logical signal TS 22 performs a logical OR operation on the inverted signal CSi # of the control signal CSi and the electrical repair activation signal EN.
2 is output.

The third logic section 631 is shared by the laser repair processing part 610 and the post repair processing part 620, and the first and second logic signals TS1 and TS.
2 and the column selection signal CSLEN are ANDed and a redundancy activation signal RCSLENi (i = 1 to n) is output.

When a read or write command is received by the semiconductor memory device, the external column address CA is also received. If the main column designated by CA is not repaired, then no repair fuse box contains that address. If the main column designated by CA is replaced in the laser repair process at the wafer stage, the column address is stored in one laser fuse box 611 of the redundancy control block 23i. Then, if the main column designated by CA is replaced in the post repair process, the column address is stored in the electrical fuse box 210. CA is provided not only to the electrical fuse address comparator 220 but also to the address comparator 612 of each redundancy control block 23i. Each address comparator compares CA with its own stored address. That is, the address comparator 612
Compares CA with the laser fuse address LCA, and the address comparator 220 compares CA with the electrical fuse address ECA.
Compare with CA. If the defective main column is repaired, one of the address comparators detects that the CA and the stored address match and outputs the output signal OU.
Activate T or EN. If the main column designated by CA was not repaired, no comparator would activate the output signal.

In the first or main operation mode, each redundancy control circuit 23i responds to the repair address by the laser fuse-program. In this mode, control signal CSi
Are deactivated, TS1 responds to OUT, and TS2 is always deactivated. Therefore, when CA and LCA match and CSLEN is activated, the redundant column selection signal RCSLENi is activated. Otherwise, the redundant column selection signal RCSLENi is maintained in the inactive state.

In the alternative operation mode, each redundancy control circuit 23
i responds to the repair address by the electrical fuse program. In this mode, the control signal CSi is activated, TS1 is always activated, and TS2 responds to EN. Therefore, CA and ECA match and CSLEN
Is activated, the redundant column selection signal RCSLENi
Is activated. Otherwise, the redundant column selection signal RCSLENi is maintained in the inactive state.

In the embodiment of FIG. 7, the redundancy control block 2
At most one of the 3i blocks is set to the alternative operating mode. All other redundancy control blocks are set to the main operating mode. Which control block 23i is set to the alternative operation mode is determined by the state of the post repair control block 25i. Each post repair control block 25i includes a fuse or other configurable element. For example, FIG. 9 illustrates an exemplary implementation of the post repair control block.

In FIG. 9, the post repair control block 25i
Includes a post repair fuse 710. The post repair fuse 710 is preferably a laser-cuttable fuse at the wafer stage. Whether the control signal CSi is activated depends on whether the post repair fuse 710 is cut. That is, when the post repair fuse 710 is not cut, the control signal CS
i is deactivated to a low level, and when the post repair fuse 710 is cut, the control signal CSi is activated to a high level.

The post repair control block 25i includes two PMOS transistors P3 and P3 in addition to the fuse 710.
4, including one NMOS transistor N6 and two inverters 712 and 714. PMOS transistor P
The sources of 3 and P4 are connected to VDD, and the drain thereof is connected to the node 810 at one end of the fuse 710. The NMOS transistor N6 has its source connected to the ground and its drain connected to the other end of the fuse 710.

Node 810 is connected to the input of inverter 712. The node 812 outputs the output of the inverter 712 to the input of the inverter 714 and the PMOS transistor P4.
Connect to the gate. The output of the inverter 714 becomes the control signal CSi.

The input signal of the post repair control block 25i is the power-up signal VCCH. The waveform of the power-up signal VCCH is shown in FIG. The power-up signal VCCH is initially at a low level when the power supply POWER is applied to the semiconductor memory device (T1),
It is a signal that becomes high level when the power supply level becomes a certain level or higher (T2). The power-up signal VCCH is applied to the gates of the transistors P3 and N6.

The operation of the post repair control block 25i is as follows. First, assume that post repair fuse 710 is in a blown state. When the semiconductor memory device is powered on (time T1 in FIG. 10), the power-up signal VCCH is in the low level state and the PMOS transistor P3 is turned on. Since the fuse 710 is blown, the node 810 becomes high level. The node 812 becomes low level and the control signal CSi becomes high level by the inverter 712.

After time T2 in FIG. 8, the power-up signal VC
Even if CH becomes high level and the PMOS transistor P3 is turned off, the signal applied to the gate of the PMOS transistor P4 is low level.
The transistor P4 is turned on, the node 810 is maintained at the high level, and the control signal CSi is also maintained at the high level.

On the other hand, the post repair control fuse 710.
Is not cut by a laser.
If the power-up signal VCCH is input in this state,
When the PMOS transistor P3 is turned on, the node 8
10 is temporarily set to the high level, but when the power-up signal VCCH is set to the high level soon, the NMOS transistor N6 is turned on, the PMOS transistor P3 is turned off, and the node 810 is set to the low level. The node 812 goes high due to the inverter 712, turning off the PMOS transistor P4. The inverter 714 is a low level control signal CSi.
Is output.

In this embodiment, it is desirable that the redundant column line i used for post repair be determined in a wafer state. For example, the redundant column lines are tested to see which redundant columns do not fail. Defect-free redundant memory lines are allocated for post repair. The allocation for the post repair is performed by cutting the fuse 710 of the post repair control block for the memory line.

Also preferably, the selection of redundant memory lines used for post repair is performed in connection with the laser fuse repair operation at the wafer level. For example, main and redundant column lines are tested at the wafer stage to see what lines are bad. A defect-free redundant memory line is designated for each defective main array column line, and the laser fuse box (611 in FIG. 8) for the redundant memory line is programmed with the address of the defective main array column line. If all defective main memory lines have been repaired and the non-defective redundant memory lines remain unspecified, then one of the remaining non-defective redundant memory lines is assigned for post repair. The allocation for the post repair is performed by cutting the fuse 710 of the post repair control block for the memory line.

Then, the semiconductor memory device is packaged, and the second test is performed in the packaged state.

When a defective memory column occurs in the packaged state of the semiconductor memory device, the MRS 260 is used to apply a command to program the electrical fuse box 210 with the defective column address to perform repair. Post repair is enabled if post repair control block 25i is available after laser repair and is assigned for post repair.

Although it is desirable to select a post repair column during wafer stage testing and programming,
Other embodiments are possible. For example, FIG. 11 illustrates an example of another post repair control block 27i that selects a post repair column through the bonding pad 830. In one state, the bonding pad 830 remains unconnected. NMOS transistor N7, N
8 and N9 pull down the node 820 to the low level so that the inverters 720 and 722 output the low-level control signal CSi.

In other states, the bonding pad 830 is connected to VDD. Therefore, the node 820 and the control signal CSi go high. The bonding pad 830 must be wire bonded to the VDD pad during wire bonding in order to set the control signal CSi to the high level and select the redundant column for post repair. Another method for selecting the redundant column for post repair is to use the bonding pad 830 as a VD with a lead wire on a chip carrier outside the semiconductor memory device.
Wire bonding to the lead wire connected to D.

Still another selection method embodiment is shown in FIGS. This example allows the selection of redundant columns for post repair comparator 220 after packaging. In FIG. 12, each post repair control block 28i
(I = 1 to n) are electrically programmable through corresponding control lines MRSPRCi output from MRS 290. Given post repair control block 28
A command is applied to activate control line MRSPRCi to couple i with electrical fuse box address comparator 220. Then, the electrical fuse in the post repair control block 28i is cut off, and the control signal CS
i is activated.

In this example, which redundancy control block 23
i can still be used, and it is difficult to check for defects. To solve this problem, each post repair control block 28i includes a laser fuse that prevents the electrical fuse in the post repair control block 28i from being blown. Therefore, during the wafer stage programming, each redundancy control block 23i is used for laser repair, and the laser fuse in the corresponding post repair control block 28i is also blown to prevent electrical programming of the corresponding post repair control block. To be done. If a given redundant column is found to be defective, the laser fuse in the corresponding post repair control block is also blown to prevent electrical programming of that post repair control block.

Then, during post repair of the defective column,
For the first i, the post repair control block is selected and the electrical fuse is cut. If the defective column has not been repaired after this first selection, then the corresponding post-repair control block is presumed to be disabled. Then, a new i is selected until the repair is completed normally, and the above process is repeated. If the repair is not successful for all i, the post repair has failed.

FIG. 13 is a circuit diagram showing one embodiment of the post repair control block 28i shown in FIG.

The control block 28i controls the control signal C after power-up when the fuse 730 is not cut.
It operates similarly to the control block 25i shown in FIG. 9 in that the control signal CSi goes to the logic high level after power-up when Si goes to the logic low level and the fuse 730 is blown. Fuse 730
In order to blow the current, MRSPRCi is activated to turn on the transistor P7, thereby causing an overcurrent to flow through the fuse 730. This overcurrent is due to fuse 7
It flows through 40. Therefore, the fuse 740 must not be blown, but a current must flow through it.

To prevent programming of control block 28i, fuse 740 is laser blown. If the fuse 740 is blown and the MRSPRCi is activated, no overcurrent flows through the fuse 730.

Although the above-described embodiment performs one post-repair operation, the present invention is not limited to this. That is, the number of redundancy columns for post repair is variable. For example, FIG. 14 shows a repair circuit 9 that can perform a post-repair operation twice.
It is a block diagram showing 00. The repair circuit 900 is similar to the post repair circuit 200 shown in FIG. 7, and includes a redundancy control block 93i (i = 1 to n), an RCSL generator 94i (i = 1 to n), and a post repair control block 9.
5i (i = 1 to n). The difference from the post repair circuit 200 shown in FIG.
This is in that it has two electric fuse boxes 911 and 912 and address comparators 921 and 922.

Two electrical fuse boxes 911, 9
12 is a number of signals MRS output from the MRS 260.
1. First and second electrical column addresses ECA1 and E controlled by MRSCAi to designate defective columns by selectively disconnecting internal electrical fuses.
Each is programmed in CA2. The electrical fuse box can be used to gate one MRS signal to another so that the fuse box can be programmed independently.

The address comparator 921 includes a first electrical column address ECA1 programmed in the first electrical fuse box 911 and an externally applied address CA.
When the two addresses ECA1 and CA match,
The first electrical repair activation signal EN1 is activated. The address comparator 922 includes a second electrical fuse box 912.
Second electrical column address ECA2 programmed to
Is compared with an address CA applied from the outside, and if both addresses ECA2 and CA match, the second electrical repair activation signal EN2 is activated.

First and second electrical repair activation signals EN
1 and EN2 are redundancy control blocks 93i (i = 1 to n)
Entered in.

Redundancy control block 93i (i = 1 to n)
May perform laser repair by the control signal CSi (i = 1 to n) input from the post repair control block 95i (i = 1 to n) and the first and second electrical repair activation signals EN1 and EN2. , Sometimes post repair. In the circuit 900, each control signal CSi is composed of two signal lines, and one signal line CSi_1 is paired with EN1 and the other signal line CSi_2 is paired with EN2. The redundancy control block 93i operates as a laser repair block when both CSi_1 and CSi_2 are at low level. The redundancy control block 93i operates as a post repair block in response to the repair address ECA1 when CSi_1 is at high level and CSi_2 is at low level. The redundancy control block 93i is CSi
When _1 is low level and CSi_2 is high level, it operates as a post repair block in response to the repair address ECA2.

To generate the two control signals, each post repair control block 95i includes two laser fuses and two sets of circuits similar to those shown in FIG.

FIG. 15 shows the repair circuit 2 shown in FIG.
10 is a block diagram of a circuit obtained by partially modifying 00. FIG. This embodiment makes it possible to fix two possible failure cases that are not corrected by the embodiment shown in FIG. The first failure is when the main column is laser repaired, but the repair column for that laser repair is also defective. The second failure case is when the column allocated for post repair proves to be bad after this repair. In both cases, the embodiment shown in FIG. 12 cannot further repair the particular address to other redundant columns.

To cover such a failure case, the embodiment shown in FIG. 15 introduces the concept of overriding the post repair control block. The concept applies between redundancy control blocks. As shown in FIG. 15, the redundancy control block 291 produces an override signal OVR1 in the redundancy control block 292, the redundancy control block 292 produces an override signal OVR2 in the redundancy control block 293, and the pattern is redundant. Continue to control block 29n. When a redundancy control block receives a logic low level override signal, it performs two operations in response. One is an operation of passing a logic low level override signal to the next redundancy control block, and the other is an operation of shutting down RCSLEN of its own so as not to be activated even if an address match occurs. The redundancy control block also activates its own override signal if an address match occurs with its programmed address without interruption.

In fact, in this embodiment, the redundancy control block 29i and the post repair control block 28i can be used starting from the block n and going up to the block 1.
For example, assume that some bad columns are repaired during laser repair. Assume that the last one is repaired by laser programming the redundancy control block 293 with repair address RA3, and the redundancy control blocks 292, 291 are available for post repair. In this case, the post repair control block 28
3 to 28n are disabled during laser repair as described above. In the redundancy control block 293, CA matches RA3, and R is activated each time CSLEN is activated.
Activate CSLEN3.

After that, it is assumed that a defect is detected for the address RA3 during the post repair test after packaging. It is highly possible that a defect has occurred in the redundant column related to the redundant control block 293. However, it is unknown whether this address was repaired once in the post repair test process. Therefore, the address is repaired again. Address RA3 is programmed into electrical fuse box 210. The repair system attempts to program the post repair control block 28n, but the attempt fails because the post repair control block 28n was disabled during laser repair. The repair system attempts to program the next post repair control block 28n-1 and the attempt continues until post repair control block 282. Since the post repair control block 282 is not used for laser repair, it can be used for post repair. When programming is completed, CS2 is activated to high level.

If column RA3 is tested, then C
A and ECA match. Therefore, if both EN and CS2 are activated, control block 292 activates RCSLEN2 to select the corresponding redundant column. At the same time, the redundancy control block 292 sets the override signal OVR2 to the logic low level. The redundancy control block 293 receiving the logic low level OVR2 blocks RCSLEN3 from being activated even when its own internal address comparator detects an address match.

If one step is advanced in the above example, it is possible that the repair column for RCSL2 is defective. Then, despite the electrical post repair, the column RA3
Defects occur when is tested. The post repair system is programmed using another post repair control block 281. Then, both CS1 and CS2 are activated. Each time CA and RA3 match, redundancy control blocks 291, 292, 293 detect an internal address match, but redundancy control block 29
Since the priority of 1 is high, the redundancy control block 292 is blocked from activating RCSLEN2 by using the OVR1 signal. Also, block 292 blocks redundancy control block 293.

FIG. 16 shows an example of the redundancy control block 29i which performs the above functions. The laser fuse box 611 and the address comparator 612 operate similarly to the block shown in FIG. The logic element 613 is OUT
Is ANDed with the control signal CSi to output the first logic signal TS1 #. Logic element 622 is CSi #
And NOR operation with the electrical repair activation signal EN
The logic signal TS2 # is output. NOR gate 641
Is a first logic signal TS1 # and a second logic signal T
S2 # is received to generate a signal input to the logic element 631. The other input of the logic element 631 is CSLEN
And OVR (i-1). The logic element 631 logically ANDs the three signals to generate the column selection enable signal RCSLENi. When OVR (i-1) is at a logic low level, activation of RCSLENi is prevented.

Still another two logic gates are used to generate the output priority signal OVRi. Inverter 64
2 inverts OVR (i-1). NOR gate 643
Receives the output of the NOR gate 641 and the output of the inverter 642 and outputs the output priority signal OVR (i). O
If VR (i-1) is logic low, OVR (i) will also be logic low. OVR (i) also becomes logic low when the redundancy control block 29i detects an address match and both the first and second logic signals TS1 # and TS2 # are at low level.

Although the present invention has been described with reference to an embodiment shown in the drawings, it is merely an example, and those skilled in the art will appreciate various modifications and equivalent other embodiments. Understand that is possible. For example, the relationship between the redundancy control block and the redundancy memory line can be expressed in various configurations. Only some of the redundancy control blocks may have dual mode (laser programming at the wafer level and post repair programming) capability, and the remaining redundancy control blocks may not have dual mode capability. Therefore, the true technical protection scope of the present invention should be determined by the technical idea of the claims.

[0090]

According to the present invention, the redundant line for post repair need not be provided separately from the redundant line for laser repair. Then, by pre-testing a redundant line not used for laser repair and selecting a good non-defective redundant line for post repair, the success rate of post repair is greatly increased.

Therefore, according to the present invention, the repair efficiency is improved and the yield of the semiconductor memory device is greatly increased.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a semiconductor memory device according to example embodiments.

FIG. 2 is a block diagram showing an embodiment of a dual mode repair circuit.

3 is a circuit diagram illustrating in detail the redundancy control block of FIG.

FIG. 4 is a detailed circuit diagram of the electrical fuse block and address comparator of FIG.

5 is a detailed circuit diagram of the electrical fuse block and address comparator of FIG.

FIG. 6 is a detailed circuit diagram of the electrical fuse block and address comparator of FIG.

FIG. 7 is a block diagram illustrating a second embodiment of a dual mode repair circuit having a means for coupling an electrical fuse block to one of a number of redundant columns.

FIG. 8 is a detailed circuit diagram of the redundancy control block of FIG.

9 is a detailed circuit diagram of the post repair control block of FIG.

10 is a waveform diagram of a power-up signal input to the post repair control block of FIG.

11 is a diagram illustrating another implementation example of the post repair control block of FIG.

FIG. 12 is a block diagram showing a third embodiment of a dual mode repair circuit having an electrical fuse post repair block and a circuit diagram of a post repair control block.

FIG. 13 is a block diagram showing a third embodiment of a dual mode repair circuit having an electric fuse post repair block and a circuit diagram of a post repair control block.

FIG. 14 is a block diagram showing a fourth embodiment of a dual mode repair circuit having an electrical fuse block capable of performing a post repair operation twice.

FIG. 15 is a block diagram illustrating a fifth embodiment of a dual mode repair circuit having a redundancy control block that has the ability to override a previous failed repair operation attempt.

16 is an exemplary implementation of the redundancy control block of FIG.

[Explanation of symbols]

210 Electrical Fuse Box 220 Address Comparators 231, 232, 233, 23n Redundancy Control Blocks 241, 242, 243, 24n RCSL Generators 251, 252, 253, 25n Post Repair Control Block 260 Mode Register Set (MRS)

Continued front page    F-term (reference) 5L106 AA01 CC12 CC13 CC17 DD00                       EE07 GG05 GG07                 5M024 AA90 AA91 BB07 BB30 DD63                       DD80 DD85 HH10 MM10 MM13                       MM15 PP01 PP02 PP03 PP07

Claims (51)

[Claims] 1. A set of addressable main memory lines connected to a plurality of corresponding main memory cells, a first redundant memory line connected to a plurality of first redundant memory cells, and an input address selected. A redundant memory line control circuit capable of selecting the first redundant memory line each time it matches the stored memory line address, the redundant memory line control circuit comparing the input address with a first main storage address. A primary mode for selecting the redundant memory line based on a first comparison and an alternative mode for selecting the redundant memory line based on a second comparison comparing the input address with a first alternative storage address, The first alternative storage address may be stored after the memory device is packaged. 2. The redundant memory line control circuit, a first laser fuse box storing the first main storage address, a first post repair address box storing the first alternative storage address, the first comparison A first main address comparator for enabling a first main signal when the first comparison result is true, and a second substitute signal for performing the second comparison when the second comparison result is true. A first post repair address comparator for enabling the redundant memory line in response to the first primary signal in the primary mode, and the first in the alternate mode.
The semiconductor memory device according to claim 1, further comprising: a mode selection circuit that selects the redundant memory line in response to an alternative signal. 3. The semiconductor memory device further comprises a mode register set circuit, the first post repair address box includes a plurality of electrical fuse units storing the first alternative storage address, and the electrical fuse unit. Stores the first alternative storage address in response to a set of mode register set signals generated from the mode register set circuit in response to an external command applied after packaging the semiconductor memory device. The semiconductor memory device according to claim 2. 4. The mode selection circuit includes a post-repair control block including a laser fuse to generate a control signal, and the post-repair control block outputs the control signal when the laser fuse is not cut. When the laser fuse is cut, the control signal is set to the second logic level when the first logic level is set.
The semiconductor memory device of claim 2, wherein the semiconductor memory device is set to a logic level. 5. The power-up signal circuit of the semiconductor memory device, which generates a logic-low power-up signal until the voltage supplied to the semiconductor memory device reaches a predetermined threshold after power-up of the semiconductor memory device. 5. The post-repair control block is further responsive to the power-up signal after the power-up signal is switched to a logic high level.
The semiconductor memory device according to 1. 6. The post repair control block includes a latch responsive to the power up signal, the post repair control block bringing the latch to the first logic level while the power up signal is at a logic low level. The power-up signal is maintained at the first logic level or is converted to the second logic level after the power-up signal is converted to the logic high level. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is a memory device. 7. The mode selection circuit duplicates one of the first main signal and the first alternative signal depending on whether the control signal is set to the first or second logic level. The semiconductor memory device of claim 4, further comprising gate logic. 8. The semiconductor memory device of claim 7, wherein the mode selection circuit further receives a column selection signal, and the redundant memory line is enabled according to a state of the column selection signal. 9. The mode selection circuit includes a post repair control block that includes a bonding pad to generate a control signal, and the post repair control block controls the control when the bonding pad is wired to a reference voltage. 3. The semiconductor memory device of claim 2, wherein the signal is set to a first logic level and the control signal is set to a second logic level when the bonding pad is not wired to the reference voltage. . 10. The post repair control block further comprises a pull-down circuit and a buffer, the pull-down circuit having a pull-down node connected to the buffer input and the bonding pad, the bonding pad being wired to the reference voltage. The buffer input is pulled to a logic low level if not, and the buffer input is substantially maintained at the reference voltage when the bonding pad is wired to the reference voltage. Item 10. The semiconductor memory device according to item 9. 11. The mode selection circuit includes a post repair control block that includes a bonding pad to generate a control signal, and the post repair control block is provided when the bonding pad is wired to a power supply voltage. The semiconductor device according to claim 2, wherein the control signal is set to a first logic level, and the control signal is set to a second logic level when the bonding pad is wired to the ground voltage. Memory device. 12. The semiconductor memory device further comprises a mode register set circuit, the mode selection circuit includes a post repair control block including an electric fuse to generate a control signal, and the post repair control block includes the post repair control block. The control signal is set to a first logic level when the electrical fuse is not blown, and the control signal is set to a second logic level when the electrical fuse is blown; The semiconductor memory device of claim 2, wherein the semiconductor memory device is disconnected in response to an external command applied after packaging the semiconductor memory device in response to a mode register set signal generated from the mode register set. . 13. The semiconductor memory device of claim 12, wherein the post repair control block further includes a laser fuse that prevents a state of the control signal from being changed by electrical programming. 14. The semiconductor memory device may further include a second redundant memory line connected to a plurality of second redundant memory cells, wherein the redundant memory line control circuit stores a second main storage address. A laser fuse box, and a second main address comparator for comparing the input address with the second main storage address and enabling a second main signal when the comparison result is true,
In response to the second main signal in the main mode, the second
3. A redundant memory line is selected.
The semiconductor memory device according to 1. 15. The mode selection circuit according to claim 14, wherein in the alternative mode, the second redundant memory line can be selected in place of the first redundant memory line in response to the first alternative signal. A semiconductor memory device as described. 16. The semiconductor memory device performs a third comparison for comparing the input address with the second alternative address and a second post repair address box for storing a second alternative storage address to perform the third comparison. Second when the result is true
A second post-repair address comparator enabling an alternate signal, wherein the mode selection circuit is capable of selecting the first redundant memory line in response to the second alternate signal in the alternate mode. 14. The semiconductor memory device according to 14. 17. A set of addressable main memory lines each connected to a plurality of corresponding main memory cells, a first redundant memory line connected to a plurality of first redundant memory cells, and a plurality of second redundant memory lines. A second redundant memory line connected to the redundant memory cell, each storing a memory line address, comparing the memory line address with an input address, and enabling an output signal of the comparator when the comparison result is true. First and second laser fuses / comparators, first electrical fuses / comparators, and a first program of the first laser fuses / comparator output signals and the first electrical fuses / comparator output signals. The first redundant memory line can be selected based on selection, and the second laser fuse / comparator has a configuration according to a second program. The semiconductor memory device having a a redundant memory line control circuit that can select the second redundant memory line based on the selection of the force signal and the first electrical fuse / comparator output signal. 18. The semiconductor memory device further comprises a second electrical fuse / comparator similar to the first electrical fuse / comparator, wherein the redundant memory line control circuit is also configured by a third program. 18. The semiconductor memory device of claim 17, wherein the first redundant memory line can be selected based on the selection of the second electrical fuse / comparator output signal. 19. The semiconductor memory device may further include a mode register set circuit capable of receiving an electrical fuse programming signal as a part of an external command, the mode register set circuit having the programming target of the programming signal as the programming target. Detecting the first electrical fuse / comparator or the second electrical fuse / comparator and programming the programming target with a repair address provided as part of the programming signal. Claim 18
The semiconductor memory device according to 1. 20. The semiconductor memory device further comprises a mode register set circuit capable of receiving an electrical fuse programming signal as part of an external command, the mode register set circuit being provided as part of the programming signal. The repair address is the first
18. The semiconductor memory device as claimed in claim 17, wherein the electric fuse / comparator is programmed. 21. The redundant memory line control circuit includes a post repair control block including an electric fuse and generating a control signal used to select the programmed configuration, the post repair control block comprising: The control signal is set to a first logic level when the electrical fuse is not blown, and the control signal is set to a second logic level when the electrical fuse is blown; 21. The semiconductor device of claim 20, wherein the semiconductor memory device is disconnected in response to a mode register set signal generated from the mode register set circuit in response to an external command applied after packaging the semiconductor memory device. Memory device. 22. The semiconductor memory device further includes an override circuit for forcibly selecting the first redundant memory line even if the redundant memory line control circuit selects both the first and second redundant memory lines. 22. The semiconductor memory device according to claim 21, further comprising: 23. The semiconductor memory device further comprises a third redundant memory line and a third laser fuse / comparator similar to the first and second redundant memory lines and the first and second laser fuses / comparators. The redundant memory line control circuit comprises a third program, and the third redundant memory line is selected based on selection of the third laser fuse / comparator output signal or the first electrical fuse / comparator output signal. The override circuit forcibly selects the second redundant memory line even if the redundant memory line control circuit selects both the second and third redundant memory lines,
23. The redundant memory line control circuit forcibly selects the first redundant memory line even if both the first and third redundant memory lines are selected.
The semiconductor memory device according to 1. 24. The post repair control block includes a laser-cuttable fuse, and the electrical fuse is cut in response to a mode register set signal depending on whether the laser-cuttable fuse is cut. 22. The semiconductor memory device as claimed in claim 21, wherein whether or not it is determined. 25. The semiconductor memory device further comprises an override circuit for forcibly selecting the first redundant memory line even if the redundant memory line control circuit selects both the first and second redundant memory lines. 21. The semiconductor memory device according to claim 20, further comprising: 26. One laser fuse / each
In a method of enabling post repair in a semiconductor memory device comprising a plurality of redundant memory lines coupled to a comparator and a set of main memory lines, the redundant memory lines are tested to determine a defective redundant memory line. Assigning a non-defective redundant memory line for post repair, and replacing the laser fuse / comparator coupled with the memory line with the assigned non-defective redundant memory line with a post repair comparator. A post-repair enabling method for a semiconductor memory device, comprising: combining. 27. Each has one laser fuse /
In a method of repairing a semiconductor memory device comprising a set of a plurality of redundant memory lines and a main memory line coupled to a comparator, which line is defective and which one is defective before assembling the semiconductor memory device into a package? Testing the main memory line to determine if the line is not defective, and for each defective main memory line, combining with one of the redundant memory lines assigned to replace the defective main memory line. After the semiconductor memory device is assembled into a package, the externally addressable memory line may be checked to determine whether a defective memory line is present. If there is a defective memory line in the testing stage, the defective memory Method of repairing a semiconductor memory device including a step of electrically allocating redundant memory line in order to replace the line. 28. The method of repairing a semiconductor memory device according to claim 1, wherein the assignment of the redundant memory lines before the assembly is prevented from being electrically assigned after the assembly of the semiconductor memory device. 28. The method of claim 27, further comprising setting a laser-settable fuse coupled to each of the redundant memory lines. 29. The method of repairing a semiconductor memory device, further comprising the step of testing the redundant memory lines to check which redundant memory line is not defective before the assembling. 28. A method for repairing a semiconductor memory device according to item 28. 30. The method of repairing a semiconductor memory device according to claim 1, wherein, before the assembling, each of the assigned redundant memory lines is electrically assigned after the assembling of the semiconductor memory device. 30. The method of claim 29, further comprising setting a laser-configurable fuse associated with each of the redundant memory lines. 31. Electrically assigning a redundant memory line to replace the defective memory line, setting an address associated with the defective memory line in an electrical fuse box, and using available redundant memory. Looping a set of repair addresses for redundant memory lines, attempting to set an electrical fuse for the repair addresses until all lines have been tried or the defective memory line has been replaced; 29. The method of repairing a semiconductor memory device according to claim 28, further comprising the step of testing an address related to the defective memory line to check whether the memory line related to the address is still defective. 32. Looping the set of repair addresses includes arranging the repair addresses in a predetermined order according to an override priority for each of these redundant memory lines, the trailing addresses in the predetermined order. Has a higher override priority, and based on the higher override priority, the redundancy for the repair address with the higher override priority, even if the memory line with the lower priority is already associated with the bad memory line address. 32. The method of repairing a semiconductor memory device according to claim 31, wherein a memory line is selected. 33. The method of repairing a semiconductor memory device according to claim 1, wherein, when one of the redundant memory lines is assigned to replace a defective main memory line before the assembling, a predetermined corresponding to the override priority is given. 33. The method of repairing a semiconductor memory device according to claim 32, further comprising allocating redundant memory lines in the order of. 34. One laser fuse / each
A method of repairing a semiconductor memory device comprising a set of a plurality of redundant memory lines and a main memory line coupled to a comparator, wherein which line is defective and which line is defective before the semiconductor memory device is assembled into a package. A test of the main memory line and the redundant memory line to determine whether the defective main memory line is defective, and for each defective main memory line, the defective redundant memory allocated to replace the defective main memory line. Configuring the laser fuse / comparator coupled with one of the lines, and if the defective redundant memory line remains after replacement of the defective memory line, the remaining defect-free redundancy Allocating a memory line for post repair, said allocated post repair The A redundant memory line,
Connecting the post-repair comparator in place of the laser fuse / comparator coupled to the assigned redundant memory line for post-repair, and repairing the semiconductor memory device. 35. The method of repairing a semiconductor memory device, further comprising testing the main memory line again to check which of the main memory lines is defective after the semiconductor memory device is assembled in a package. If one of the main memory lines is determined to be defective during the retesting process, a post repair combined with the assigned post repair redundant memory line to replace the defective main memory line. The method of repairing a semiconductor memory device according to claim 34, further comprising the step of configuring a comparator. 36. The step of coupling the assigned post-repair redundant memory line with the post-repair comparator comprises: blowing a fuse so that the post-repair comparator has the assigned post-repair redundant memory line. Configuring a select logic to be coupled to the laser fuse / comparator coupled to the assigned redundant memory line for post repair. 34. A method for repairing a semiconductor memory device according to 34. 37. The method of repairing a semiconductor memory device according to claim 36, wherein the cutting of the fuse is performed by an external command after packaging of the semiconductor memory device. 38. A redundant line that can replace a defective main memory line, a first defective address storage that can be programmed only before packaging and assembling a semiconductor memory device, and a first defective address that can be programmed only after packaging and assembling a semiconductor memory device. A semiconductor memory device comprising: two defective address storage units; and means for coupling the first or second defective address storage unit with the redundant line. 39. The semiconductor memory device further comprises first and second address comparators for comparing an input address with an address stored in the first and second defective address storage units, respectively, and the combining means. 39. The semiconductor memory device of claim 38, further comprising a programmable post repair control block that enables the first address comparator in one programmable mode and the second address comparator in another programmable mode. 40. N (N is a number greater than 2) redundant lines, each of which can replace a defective main memory line, and each redundant line are combined with one redundant line to program only before packaging and assembling of a semiconductor memory device. M first (M is a number larger than N / 2) first defective address storage units, each of which is connected to one redundancy line, and can be programmed only after packaging and assembling a semiconductor memory device. A semiconductor memory device having a second defective address storage unit. 41. In a semiconductor memory device including a plurality of normal memory cells arranged in a matrix structure of rows and columns, two or more redundancy lines that can replace defective lines of the normal memory cells and laser cutting. A laser repair for selecting a corresponding redundant line in place of the defective line is performed by selectively cutting a plurality of laser fuses, and the defective line is replaced in place of the defective line in response to a predetermined control signal and an electrical repair activation signal. Each of the redundancy control blocks provided corresponding to each of the redundancy lines for performing post-repair for selecting the corresponding redundancy line, and at least two of the redundancy control blocks among the redundancy control blocks. One by one corresponding to the above, the redundancy control corresponding to the specified redundancy line. A semiconductor memory device comprising a post repair control block that outputs the control signal of a predetermined level as a control block. 42. The semiconductor memory device includes a plurality of electrically fuses that can be electrically cut, and one of the defective lines is designated by a combination of the electrically fuses that are selectively cut. And an address comparator that activates the electrical repair activation signal when the programmed address and the external address match. Item 4
1. The semiconductor memory device according to 1. 43. The semiconductor memory device further comprises a mode register set for receiving a large number of command signals and a large number of address signals from the outside, wherein the electrical fuse box is responsive to the external signals to store the mode registers. The semiconductor memory device of claim 42, wherein the semiconductor memory device is controlled by a signal output from the set. 44. The address comparator receives 1 bit of an address programmed in the electrical fuse box and 1 bit of the external address, respectively, and receives the first bit if the received two bits match.
43. The method according to claim 42, further comprising a plurality of comparators each outputting a logic level signal, wherein the electrical repair activation signal is activated when the output signals of the comparators are all at the first logic level. The semiconductor memory device according to 1. 45. Each of the redundancy control blocks includes a laser repair processing part for performing the laser repair, wherein the repair processing part includes the defective line due to a combination of the laser fuses that are selectively cut. A laser fuse box programmed with an address designating any one of them, and an address comparison unit that produces an output signal that is activated if the address programmed in the laser fuse box and the external address are the same. 43. The semiconductor memory device according to claim 42, comprising: 46. The semiconductor memory device of claim 42, wherein one post repair control block is provided for each of the redundancy control blocks. 47. Each of the post-repair control blocks includes a post-repair control fuse that can be cut by a laser, and the control signal output from the post-repair control block disconnects the post-repair control fuse. 43. The semiconductor memory device of claim 42, wherein the logic level is different depending on whether or not it is. 48. The semiconductor memory according to claim 47, wherein the cutting of the post repair control fuse is performed in a wafer state of the semiconductor device, and the post repair is performed in a package state of the semiconductor device. apparatus. 49. A semiconductor memory device comprising: a plurality of normal memory cells arranged in a matrix structure of rows and columns; and two or more redundancy lines that can replace defective lines of the normal memory cells. In the repair method for replacing a line with the redundancy line, (a) performing a laser repair using a laser in a wafer state of the semiconductor device; and (b) a step of (a) of the redundancy lines. Testing a redundant line not used for laser repair, and (c) selecting at least one of the redundant lines certified as non-defective in the test of (b) above as an electrical repair line. (D) a step of testing the semiconductor device in a package state, and (e) a defect line generated in the step (d). Post repair method characterized by comprising the step of repairing the electrical repair line. 50. The method of claim 49, wherein the step (a) includes the step of selectively cutting a number of laser fuses capable of being cut by a laser to program an address for designating the defective line. Post repair method described. 51. The step (e) includes the step of selectively cutting a plurality of electrically disconnectable electric fuses to program an address designating a defective line generated in the step (d). 50. The post repair method according to claim 49, wherein: