JPH01108736A - Manufacture of integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to fuse cut a fuse at the address of 9 defective memory cell only to a necessary memory circuit out of a plurality of pieces of memory circuits by a method wherein an address signal to specify the detected defective memory cell is fed to each of a plurality of pieces of the memory circuits individually and simultaneously. CONSTITUTION:A performance test is conducted for each of a plurality of pieces of memory circuits on one sheet of a wafer by a detecting means (detecting process) 10 and after the compare check of known write data and read out data is performed to detect a defective memory cell, the address signal of the defective memory cell is fed to the memory circuits by an address signal input process 11. This process 11 makes first and second signals led out by a driver 3 feed respectively to first and second selecting means 14 and 15. Here, as one of the signals is selected by a control means 16, the address signal is inputted at a different value in every memory circuit individually and simultaneously.

Description

[Detailed Description of the Invention] (Summary) Regarding a method for manufacturing an integrated circuit in which a plurality of memory circuits each having a redundant cell are formed on a single chip, a defective memory cell in a plurality of memory circuit sections is provided. The purpose is to quickly blow out the fuse for determining redundant use of memory cells even if the addresses of the memory cells are different. A method for manufacturing an integrated circuit in which a plurality of memory circuits configured to use redundant cells are formed on a single I-C, a detection step of detecting a defective memory cell in the plurality of memory circuits; an address signal input step for separately and simultaneously supplying address signals specifying the defective memory cell; and blowing the redundant use determination fuse for the plurality of memory circuits to which the address signals are input. and a blowing step of blowing out the fuse by applying a signal to the address signal input terminal, and the address signal input step applies first and second signals having different logical values to each address signal input terminal in parallel. I-control the driver for outputting, the first selection means for selectively outputting the first signal, the second selection means for selectively outputting the second signal, and the first and second selection means. The address signal is input using the llllll means.

(Industrial Application Field) The present invention relates to a method of manufacturing an integrated circuit, and more particularly to a method of manufacturing an integrated circuit in which a plurality of memory circuits each having redundant cells are formed on a single wafer.

A large-scale integrated circuit (LSI) is tested for operation, and if a memory cell is determined to be defective, the pre-installed fuse for determining redundant use of the memory cell is blown, and an address corresponding to the defective memory cell is input. Sometimes, redundant cells are used to repair defects.

When forming a large number of such LSIs on a single I-C, it is necessary to blow out the fuses quickly in terms of manufacturing efficiency.

[Conventional technology]

FIG. 8 shows a circuit system diagram of an example of main steps in a conventional integrated circuit manufacturing method. In the same figure, 1 is a tester, and redundant cells are used in place of defective memory cells for devices under test 5 to 54, which will be described later, after the operation test is completed, so they are used redundantly at addresses corresponding to the defective memory cells. In order to blow out the determination fuse, an address signal designating the address is output.

The tester 1 includes drivers 21 to 2m and buffers 3u to 3+, which are provided in response to address signals of m pits.
m s 321~32 m, 331~3s m *
34 turtle ~ 34w +, driver relay 4n ~ 4I frost.

42+~4z tn* 431~41 tn, 44~4
It is composed of 4 tn and so on.

The drivers 21 to 2m selectively output either a high level or a low level based on input data.

Buffers 3n to 34m each receive output signals from drivers 21 to 2yn as input signals, buffer and amplify the signals, and supply the buffered signals to driver relays 4n to 44T11. Driver relays 411 to 44m are energized (make) or de-energized (
The signal from the buffer corresponding to that driver relay is selected only at the time of make.

Driver relays 4n-4am are connected to pads (address signal input terminals) 6n-641Tl of devices under test 51-54 via tester bins.

Above driver 21~2m, buffer 3o~3am
The circuit section consisting of the m driver relays 4n to 44Tn is provided in parallel in the number of pads of each of the devices under test 51 to 54, for example.

The devices under test 51 to 54 have the same configuration.
In SI, these are memory circuits (e.g., random φ access, memory (RAM)) that are provided with fuses for determining redundant use of memory cells, and are configured to use redundant cells when an address corresponding to a blown fuse is input. Also, these are mounted on the same single board. On this second wafer, a large number of LSIs having the same configuration as the devices to be measured 51 to 54 are mounted. A large number of LS on this one I-C
After performing an operation test on I (device under test), fuses at predetermined locations of the device under test determined to be defective are blown.

- As an example, as a result of an operation test in which known data is actually written and read out, and the read data is compared with input data, the memory of each of the devices under test 5I and 52 of the devices under test 51 to 54 at the same address Assuming that there is a defect in the cell, the drivers 21 and 22 (
However, 22 is not indicated), a higher level signal is continuously taken out, and driver relays 4n to 41W
I and 421-42 are respectively made or broken so as to output an m-pit address signal specifying the same address as the address of the defective memory cell, and driver relays 431-4gm and 4a-44W1 are broken, respectively. .

As a result, each pad 6 of the devices under test 5I and 52
The same address signal is input to n-6IWI and 621-62Wl, and in this state, the voltage V1. By applying V21 to Va, the redundant use determination fuse is blown at the same address as the defective memory cell, as will be described later.

When this fuse for determining redundant use is blown, when the LSI is actually used after shipment, when an address signal that matches the address programmed in the blown fuse for determining redundant use is input, The redundant decoder circuit is activated, the normal decoder circuit is prohibited from operating, and the redundant cell is used in place of the defective memory cell. Therefore, defective memory cells can be repaired.

In this way, using the tester 1, it is possible to remedy the defective states of the devices under test 5 and 52 at the same time.

(Problem to be Solved by the Invention) However, although the devices under test 51 to 54 have the same configuration, the address values of the defective memory cells are not always the same, and the defective memory cells have different addresses. There are also devices under test that have no defective memory cells.

However, with conventional testers, the driver relays connected to each address signal input pad of the device under test that has a defective part are all appropriately configured to output the same address signal. The configuration was such that all driver relays connected to each address signal input pad of a non-defective device under test were broken.

For this reason, conventionally, when repairing defects in the devices under test 51 to 54, which have different defective locations as described above,
It is not possible to blow fuses all at once, so it is recommended to set the conditions for one device under test and then blow the fuses.
The process was repeated for all devices under test that had defective parts.

Therefore, it has been conventionally said that in the above case, the measurement efficiency (fuse blowing efficiency) decreases significantly! There was 1 IWA point.

The present invention was created in view of the above points, and is an integrated circuit that can quickly blow out a fuse for determining redundant use of a memory cell even if the address of a defective memory cell differs in a plurality of memory circuits. The purpose is to provide a manufacturing method.

[Means for Solving the Problems] FIG. 1 shows a block diagram of the principle of the present invention. In the figure, 10 is a detection process, and 11 is an address signal input process.

12 indicates a fusing process.

In the detection step 10, a plurality of memory circuits are tested as devices under test to detect defective memory cells.

The address signal input step 11 separately and simultaneously supplies address signals specifying the detected defective memory cells for each of the plurality of memory circuits.

In the blowing step 12, a signal for blowing out the redundant use determination fuse is applied at the address corresponding to the defective memory cell to blow the fuse.

Here, the address signal input step 11 includes a driver 13, a first selection means 14. Second selection means 15° control means 16
Accordingly, the control means 16 sets only one of the first and second selection means 14 and 15 to a selective output state, or both of them are set to a signal passage blocking state. These drivers13. First and second selection means 14 and 15.1
The address signal is input using the 11111 means 16.

[Effect]

In a method for manufacturing an integrated circuit in which a plurality of memory circuits are formed on a single wafer, in which fuses for determining redundant use of memory are provided, and a redundant cell is used when an address corresponding to a blown fuse is input. An operation test was performed on a plurality of memory circuits on each of the two sheets of I-C by the detection means 10, and defective memory cells were detected by comparing the known data read out with the data read out. Thereafter, in an address signal input step 11, the address signal of the defective memory cell is supplied to the memory circuit.

In this address signal input step 11, the first and second signals taken out from the driver 13 are supplied to the first and second selection means 14 and 15, respectively, and one of them is selected by the control means 16 here. Therefore, address signals with different values can be input to each memory circuit separately and simultaneously.

Furthermore, the control means 16 can selectively output neither the first nor second signals, and in this case, the fuse can be prevented from blowing in the next blowing step 12.

Therefore, even if the addresses of defective memory cells of multiple memory circuits mounted on one I-C are different from each other, or even if defective memory circuits and good memory circuits are mixed together, , different address signals can be supplied separately at the same time, or address signals can not be supplied to non-defective memory circuits.

(Example〕 FIG. 2 shows a circuit system diagram of an embodiment of the main part of the present invention.

In the figure, the same components as in FIG. 8 are denoted by the same reference numerals, and the explanation thereof will be omitted as appropriate. FIG. 2 shows an example of the configuration of the tester 17 used in the address signal input step 11, and the drivers 181 to 18m in the tester 17 respectively output a first signal and a second signal in parallel, which are opposite in phase to each other. It has two output terminals that can output to. - The first signal of the first and second signals taken out from the driver 18+ is sent to the buffer 311.321°3s+, .
Driver relay 4m via 3a in parallel.

421, 431 #44+, and the second signal is passed through buffers 19n, 1921.193 and 1941 in parallel to driver relays 20n and 2021.20.
31°2041. Driver relay 4 n
+421.

431.44 Blindness and 20n, 2021.2031.20
a are controlled by separate control signals, and when driver relay 4fl is made and outputs the first signal, driver relay 2On is in the break state, and when driver relay 20n outputs the second signal, driver relay 2On is in the break state. Driver relay 4n is set to break state (driver relay 42
1-441. The same applies to 2021-204I). Further, driver relays 4n to 441 and 10n to 104I may both be in a broken state.

In this way, the tester pins 211-214 are supplied with the first signal or the second signal (in some cases, no signal is supplied). The tester bins 211-214 are connected to pads 61-64 which are the first bit input terminals of the m-bit address signal input terminals of the devices under test 51-54.

The tester 17 has the above drivers 18+1. buffer 3n
~341,19TI~1941. Driver relay 4n~
As shown in FIG. 2, a total of m circuit sections consisting of circuit sections 441, 201 to 2041 are provided in parallel in correspondence with address signals of m pits.

Note that the drivers 181 to 18m include the device under test 5.
During the operation tests 1 to 54, an operation test signal is supplied.

As described above, each of the devices under test 51 to 54 is a memory circuit having the same configuration, for example, a 256-bit dynamic random access memory (DRAM) having the configuration shown in FIG. be.

In FIG. 3, 25 is a memory cell with 262.144 pits, and two systems of redundant cells 26a are provided on the row side.

26b, and one system of redundant cells 27 is provided on the column side.

Redundant circuits 28a, 2 correspond to redundant cells 26a, 26b.
8b is provided, and a redundant circuit 29 is provided corresponding to the redundant cell 27.

Ao to A8 are 9-pit address signals, are these address buffers? 30 and 31, respectively. Also, a pulse generator 32 for RAS and CAS beams.
CAS is also supplied to the address counter 34 via the refresh control circuit 33. The output signal of the address counter 34 is sent to the address buffer 30.
and 31, respectively.

The output signal of the address buffer y30 is supplied as a row address signal to the redundant circuits 29a, 28k, respectively, and also to the row decoder 35.

Also, address buffer? The output signal of 31 is supplied to redundancy circuit 29 and column decoder 36 as a column address signal. Further, the CAS is supplied to the address buffer y30 and the 0 decoder 35, respectively, and the redundant circuit 2
Redundant sense amplifier I10 gate 3 with output signal of 9
7.

The column address decoded by the column decoder 36 is supplied to the memory cell 25 via the sense amplifier/I10 gate 38.

Further, 39 is a gate circuit, 40 is a clock generator, and 41 is a light clock generator.

42 is a data input buffer 7, 43 is a data output buffer, and 44 is a substrate bias generator.

A write enable pulse WE is supplied to the write clock generator 41, and from this, at the falling edge of CAS, W
When E is at a low level, a write state is entered, and input data DIN is supplied to the sense amplifier/I10 gate 38 through the data input buffer 42. Further, when WE is at a high level at the falling edge of CAS, the data manual buffer 42 enters a signal passage blocking state and a read operation is performed.

At the end of the bit line of the memory cell 25, there is a sense amplifier I.
10 gates 38 are connected, and when reading, the stored information at the specified address of the memory cell 25 is sent to the sense amplifier.
It is detected and amplified by the sense amplifier of the I10 gate 3B, and becomes output data 000 through the data output buffer 43.

At the time of writing, the I10 gate of the sense amplifier/I10 gate 38 is driven based on the data DIN inputted through the data manual buffer 42, and the data is written into the memory cell 25 at the designated address via the pit line.

Here, the row address is normally specified by the row decoder 35, but when the redundant cells 26a, 26b are used, it is specified by either of the redundant circuits 28a, 28b, and the column address is usually specified by the column decoder 36. However, when the redundant cell 27 is used, it is specified by the redundant circuit 29.

Here, the redundant circuits 28a and 28b have the same configuration, and the redundant circuit 29 also has the same configuration, for example, as shown in FIG.

In the figure, 46o to 461 are address signals Ao to Ay,
Ao ~Ay and electric EEVt, Vz (Vz Gt
As shown in FIG. 3 <V21. V22. There is V21,
The fuse determination circuit 1111.47 to which a negative voltage (indicated here) is supplied is a fuse determination circuit for redundant use.゛Moreover, the MO8 type field effect transistors (hereinafter referred to as transistors) 022 to Qa are all N-channel s
Qm and Qys constitute a flip 70 tube.

Each of the first fuse determination circuits 46o to 467 and the redundant use fuse determination circuit 47 is constructed by calculating the logical product of two redundant program circuits shown in FIG. 5(A) and those two redundant program circuits. The AND circuit shown in (B),
It is composed of a determination circuit shown in FIG. 5(C). In addition, in the fuse determination circuit 47 for redundant use, as shown in FIG.
, Vss is applied instead of the signal A1 shown in (C), and A
The configuration is such that φ^CTIVε is applied instead of n.

The above-mentioned fuse is arranged as shown at 50a in the redundant program circuit shown in FIG. 5(A). Figure 5 (A
) to (C), transistors QI to Q21 are all N-channel, and transistor Q2 in FIG. 5(A)
The address signal of one corresponding pit among Ao to A7 is input to the gate of transistor Q3, and the address signal A8 is supplied to the gate of transistor Q3.

Here, the gate input address signal A of transistor Q2
When η is "O" (that is, low level) and the gate input of Q3 is also low level, when the signal φ1 shown by the - dotted chain in FIG. 6(A) is high level, the transistor Q+
is on and Q2 and Q3 are each off, so the node ◎ becomes high level, and the signal applied to the gate of transistor Qs through the drain and source of transistor Q4 becomes high level.

The node (i@(gate of Qs) becomes high level.

and transistor Qs is turned on. Further, at this time, the transistor Q7 is turned on because the signal φ1 is at a high level, and the potential of the node @ is at a high level.

Thereafter, as shown in FIG. 6, φ1 goes to low level, turning off transistor Q7, and while node α potential is at low level and transistor Q9 is off, gate input signal φ2 of transistor Qn goes to O-level. , the input voltage v2 at one end of the fuse 50a becomes a high voltage, and a few Is later, when a high voltage V+ is applied to the drain of the transistor Qs, the transistor Q9 is turned on, the node potential becomes low level, and a current flows through the fuse 50a. The flow causes the fuse 50a to blow.

At this time, another system fuse 50b (not shown)
Since the gate input of the transistor corresponding to Q3 is A8, the transistor Q9 is off and the fuse 50
k) is not fused. That is, there are two fuses 50
Which of a and 50b is to be blown out is determined by address signal A8.

Incidentally, the gate input voltage φ2 of the transistor Qm becomes an intermediate level and is clamped so that the node @ does not become a high level after blowing out the fuse 50a.

When the fuse 50a or 50bS is blown, the address signal A1 is at a low level (logic "O"), and when it is at a high level (logic "1"), it is not blown, contrary to the above.

Each potential of the node @O' of the two redundant program circuits is the transistor Q* of the AND circuit shown in FIG. 5(B),
Since it is applied to each gate of Go, the potential of the lead O becomes Q only when the fuse 50a or 50b#C is blown.
+ or Q10 is off, it becomes high level, and transistor Q+s turns on. As a result, transistor Q1
The potential at the connection point of 4IQI5 becomes low level.

In this way, the address corresponding to the defective memory cell is determined by the tester 17 from pad 6 to 6m (here m-9).
), and by making the voltage V2 (V21 to V23) high and then making V1 a high voltage, the fuse of the logic "0" pit among 80 to A7 is blown, and the logic "1" is blown.
The fuse of the bit is not blown. By the combination of blown and unblown fuses, the address of the defective memory cell can be determined during actual use by the user, which will be described later.
By using redundant cells 26a, 26b, or 27 instead, defect relief can be achieved.

Note that the redundant use fuse determination circuit 47 distinguishes between a case where the address that uses the redundant cell has a value that does not blow all the fuses in the fuse determination circuits 46o to 477 and a case where the fuses are not blown because of a non-defective product. To enable differentiation in such cases, the fuse is blown when redundant cells are used.

Although not directly related to the present invention, the following describes an LSI equipped with a DRAM whose fuse has been blown as described above.
We will explain how to select redundancy when actually used by a user.

When using the product, the voltage V1 shown in Figures 4 and 5 (A)
is set to the level at which the voltage Vss becomes the voltage v2.

Therefore, in the redundant use fuse determination circuit 47, if the fuse is not blown, the potentials of the node O and the corresponding node @' of the other system shown in FIG. 5(A) are at a high level, respectively. , transistors Qw and Qts
are respectively turned on. Therefore, the potential of the node @ shown in FIG. 5(B) is at a low level, and the potential at the node C is at a high level because the transistor Qvs is off.

At this time, the input signal φ^1:TIVE of the redundant use determination circuit shown in FIG. is on, transistors Q+s, Qss, and Q21 are off, so transistor Qt9 is on, and transistor Qw
The potential at the connection point O of both drains of Qss and Qss becomes low level.

Conversely, in the redundant use fuse determination circuit 47, if the fuse is ms, transistor QI2. O
Since n is cut off, node @ is at high level, and node O is at low level, transistor Q4 remains cut off.

Similarly, in each of the fuse determination circuits 46o to 477, when the fuse is not blown (that is, when the address Am-"1" is programmed by the fuse), when the address A1-"0" is input, The node [phase] potential shown in FIGS. 5(B) and (C) is at a low level, the α potential is at a high level, and the 551st (C)
When η is “1” (
In other words, it becomes high level), so the transistor Q+s
turns on, and the node @ goes to low level.

Also, when the fuse is blown (that is, when address A1-“O” is programmed by the fuse), if address A1==-“1” is input,
The node is high level, the node @ is low level, and the drain of transistor QII5 is A? Since l becomes a high level, the transistor Qva turns on, and the potential of the transistor Qva becomes a low level.

In this way 1. If the fuse-programmed address and the input address are different, the potential of node O becomes low level.

On the other hand, if the address programmed into the fuse and the input address match, the node O becomes high level. For example, when the fuse is blown (when address A1-“0” is programmed), address A? If l-“0” is input, node @ and Am
is at a high level and node O≧A1 is at a low level, so transistors Qm and Q10 shown in FIG. 5(C) are both cut off, and node C is at a high level.

In addition, the fuse determination circuit 4 in which the fuse is not blown
Also when address Ay+='1'' is input to 6o to 46A, node Q Kamubi λτ is low level, nodes @ and A1
Since is at a high level, both transistors Qm and Qts are cut off.

In this way, the fuses in the redundant use fuse determination circuit 47 are blown, and the fuse determination circuits 46o--
Only when the input address 81 that matches the address programmed by the combination of fuse blowing and non-blowing by 467 is applied, the node @ shown in FIGS. 4 and 5(C) is applied.
becomes high level as shown in FIG.

In this state, when the pulse φ1 is at a high level, the transistor Q22. Q24 is turned on, but since the pulse φ^CTfVE' is at a low level at this time, the transistor Qys is off, and the high level potential of the node ■ and node ψ in FIG.
It is charged up through.

In this state, when pulse φ1 becomes low level,
As shown in FIG. 7, the pulse φA CT I V E' becomes high level, and the potential of node 6) becomes high level, turning on transistor Q25 shown in FIG. 4, so that the source of transistor Qδ and Qa As shown in FIG. 7, the potential at the connection point (■) with the drain of φ becomes a high level, and the transistor Q28, whose gate is applied with this potential of Φ, turns on, and the potential of the node σp goes to a low level. drop down.

When the potential of the node m becomes high level, the decoder circuit of the redundant cell 26a, 26b or 27 is activated,
Redundant cells 26a, 26b, or 27 are used in place of the defective memory cell corresponding to the input address in memory cell 25, and normal decoder circuit operation is inhibited to prevent multiple selection.

Note that since the potential of the node O is normally at the 0-level, the potential of the node 19 is also at the low level, and the normal decoder circuit is of course activated.

(Effects of the Invention) - As described above, according to the present invention, even if the defective memory cells of a plurality of memory circuits (devices under test) mounted on one wafer are different from each other, Even if memory circuits and non-defective memory circuits coexist, different address signals can be supplied separately at the same time, or address signals can not be supplied to non-defective memory circuits. This method has the advantage that the fuse can be blown at the address of a defective memory cell only for memory circuits that are defective, and that work efficiency in the manufacturing process can be greatly improved compared to the conventional method.

[Brief explanation of the drawing]

Fig. 1 is a WAN block diagram of the present invention, Fig. 2 is a circuit system diagram of an embodiment of the main part of the present invention, Fig. 3 is a block diagram of an example of the device under test shown in Fig. 2, and Fig. 4 is a block diagram of an example of the device under test in Fig. Fig. 3 is a circuit diagram of an example of the main parts, Fig. 5 is a circuit diagram of each main part of Fig. 4, Fig. 6 is a signal waveform diagram for explaining operation when a fuse blows,
- FIG. 7 is a signal waveform diagram for explaining the operation when redundancy is selected, and FIG. 8 is a circuit system diagram of an example of the conventional system. In the figure, 10 is a detection process, 11 is an address signal input process, 12 is a fusing process, 13 is a driver, 14 is a first selection means, 15 is a second selection means, 16 is an iqm means, 26a, 26b, 27 are redundant cells, 28a, 28b, 29Lt redundant circuits, and 50a is a fuse. (♀Full voice fif>Principle f5ko y7! E㇉1 figure 〒Wall-17 @2 figure 115f!1 Figure 6 7th cause

Claims (1)

[Claims] A memory circuit is provided with a fuse for determining redundant use of a memory cell, and is configured to use a redundant cell when an address corresponding to a programmed address is input based on a combination of whether or not the fuse is blown. A method for manufacturing a plurality of integrated circuits formed on one wafer, comprising: a detection step (10) of testing the operation of the plurality of memory circuits as devices under test to detect defective memory cells; an address signal input step (11) for separately and simultaneously supplying an address signal specifying the detected defective memory cell to each of the memory circuits; and to the plurality of memory circuits to which the address signal is input. and a blowing step (12) of applying a signal to blow the fuse for redundant use determination to blow the fuse, and the address signal input step (11) applies a signal to each of the address signal input terminals. , a driver (13) that outputs first and second signals having different logical values in parallel; a first selection means (14) that selectively outputs the first signal from the driver (13); a second selection means (15) for selectively outputting the second signal from the driver (13); and one of the first and second selection means (14, 15) is set to a selective output state, and the other is set to a selective output state. control to block signal passage, or
or the manufacture of an integrated circuit characterized in that the address signal is input using a control means (16) that controls both the first and second selection means (14, 15) to a signal passage blocking state. Method.