WO2014046103A1

WO2014046103A1 - Semiconductor device having dual rescue detection circuit

Info

Publication number: WO2014046103A1
Application number: PCT/JP2013/075087
Authority: WO
Inventors: 独伸野口
Original assignee: ピーエスフォールクスコエスエイアールエル
Priority date: 2012-09-21
Filing date: 2013-09-18
Publication date: 2014-03-27

Abstract

A semiconductor device includes a plurality of first rescue determination circuits having electric fuse circuits, each of which is used for holding first rescue address information; and a dual rescue detection circuit that detects whether or not identical pieces of information exist in a plurality of pieces of the first rescue address information that are respectively held by the first rescue determination circuits.

Description

[Title of Invention Determined by ISA Based on Rule 37.2] Semiconductor Device with Double Relief Detection Circuit

The present invention relates to a device, and more particularly, to a semiconductor memory device that employs a redundancy relief method.

Patent Document 1 discloses an example of a semiconductor device including a plurality of electric fuse circuits.

JP 2005-259890 A

A plurality of electrical fuse circuits included in a semiconductor device are used as a storage unit for storing a defective address detected by a good / defective inspection performed after the semiconductor device is assembled.

The inspection after the assembly includes a plurality of different tests such as a high temperature test and a low temperature test.

Normally, a defective address detected in each test in the plurality of different tests is written in one of the plurality of electric fuse circuits immediately after each test. For this reason, the defective address detected in the first test and written in the first electrical fuse circuit is identical to the defective address detected in the second test and written in the second electrical fuse circuit. There is a possibility of doing (double relief).

Such double remedy has a problem that it prevents normal operation of the semiconductor device.

A semiconductor device according to an embodiment of the present invention includes a plurality of first relief determination circuits each having an electric fuse circuit used for holding first relief address information, and the plurality of first relief determination circuits. And a double relief detection circuit for detecting whether or not the same information is present in the plurality of first relief address information held by.

According to the present invention, there is provided a double relief detection circuit for detecting whether or not the same information exists in the plurality of first relief address information held by the plurality of first relief judgment circuits. By providing, it is possible to confirm whether double relief has occurred.

1 is a block diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a block diagram illustrating an internal configuration of a repair determination circuit included in a determination circuit used in the semiconductor device of FIG. 1. FIG. 2 is a logic circuit diagram showing an internal configuration of a double relief detection circuit used in the semiconductor device of FIG. 1. 2 is a flowchart for explaining a manufacturing process of the semiconductor device of FIG. 1; It is a logic circuit diagram which shows the internal structure of the double relief detection circuit used for the semiconductor device which concerns on the 2nd Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Here, a DRAM (Dynamic Random Access Memory) is exemplified as a semiconductor device, but the present invention is not limited to this, and the present invention is not limited to this, but other semiconductor devices adopting a redundancy relief method, for example, SRAM (Static Random Access Memory), PRAM ( Phase change (Random Access memory), flash memory, etc.

FIG. 1 shows a block diagram of a semiconductor device (DRAM chip) 10 according to a first embodiment of the present invention.

The illustrated semiconductor device 10 includes a command input circuit 101, an address input circuit 102, an internal clock generation circuit 103, a command decoder 104, a determination circuit 105, a row predecoder 106, a double relief detection circuit 107, a row decoder 108, and a column decoder 109. A memory cell array 110, a data amplifier circuit 111, and a data input / output circuit 112.

The command input circuit 101 receives a command signal (/ CS, / RAS, / CAS, / WE (“/” indicates low active)) input to the command input terminal, and outputs it to the command decoder 104.

The address input circuit 102 receives an address signal (ADD0 to ADD13) input to the address input terminal and outputs it to each unit.

The internal clock generation circuit 103 receives an external clock CLK supplied from the outside, generates an internal clock ICLK, and supplies it to each unit.

The command decoder 104 receives a command signal from the command input circuit 101, decodes the command signal, and supplies an internal command to each unit.

The determination circuit 105 includes a plurality of relief determination circuits. As will be described later, when the address indicated by the information stored therein matches the address indicated by the address signal from the address input circuit 102, the plurality of relief determination circuits output a match (HIT) signal.

The row predecoder 106 outputs a prerow address for selecting the word line WL based on the row address signal that is a part of the address signal from the address input circuit 102. When the HIT signal from the determination circuit 105 is input, a redundant address corresponding to the HIT signal is output regardless of the row address signal from the address input circuit 102.

The double relief detection circuit 107 outputs a simultaneous selection negate signal to the column decoder 109 when two or more HIT signals are simultaneously output from the determination circuit 105.

The row decoder 108 selectively drives one of the plurality of word lines WL based on the internal command from the command decoder 104 and the pre-row address from the row pre-decoder 106.

The column decoder 109 is a switch element connected between each of the plurality of bit lines BL and a local IO line (not shown) in response to a column address signal that is a part of an address signal from the address input circuit 102. A Y switch (YS) signal for controlling is output. When the simultaneous selection negate signal from the double relief detection circuit 107 is input, the YS signal is not output.

The memory cell array 110 is connected to a plurality of word lines WL, a plurality of bit lines BL, a plurality of memory cells MC arranged to be connected to the word lines WL and the bit lines BL, and each bit line. And a sense amplifier array including a plurality of sense amplifiers SA. The memory cell array 110 writes information inputted from the outside to the memory cell MC selected by the row decoder 108 and the column decoder 109, reads the information written in the memory cell MC, and outputs it to the outside.

The data amplifier circuit 111 amplifies data exchanged between the memory cell array 110 and the data input / output circuit 112.

The data input / output circuit 112 receives the data DQ0 to DQn input to the data terminals in the write mode and outputs them to the data amplifier circuit 111. The data input / output circuit 112 outputs data read from the memory cell array 110 and amplified by the data amplifier circuit 111 to the data terminal in the read mode.

In the semiconductor device 10 configured as described above, the present invention particularly relates to the determination circuit 105 and the double relief detection circuit 107. Other configurations are the same as those of a known semiconductor device. The double relief detection circuit 107 operates significantly in a test (double relief detection test described later) included in the semiconductor manufacturing process. In the normal mode, the double relief detection circuit 107 operates so as not to hinder the same operation as a known semiconductor device.

Hereinafter, the determination circuit 105 and the double relief detection circuit 107 will be described in detail.

The plurality of repair determination circuits included in the determination circuit 105 are configured as shown in FIG. That is, the repair determination circuit 20 includes a fuse circuit 201 and a comparison circuit 202. The fuse circuit 201 has a plurality of fuse elements 203.

The fuse circuit 201 stores information, that is, relief address information (code or number) by cutting / not cutting the plurality of fuse elements 203. As the fuse element 203, an electric fuse (or antifuse) element that can be electrically cut (or conducted) or a laser fuse element that can be cut by laser trimming can be used. The semiconductor device 10 of FIG. 1 uses two repair determination circuits EFUSE 1 and 2 (first repair determination circuit) using an electrical fuse circuit including an electrical fuse element, and a laser fuse circuit 1 including a laser fuse element. Individual repair determination circuits LASER (second repair determination circuits).

The relief determination circuits EFUSE1 and EFUSE1 and EFUSE2 can be used, for example, to store a (first) relief address detected by a test performed after the semiconductor device 10 is assembled. On the other hand, the repair determination circuit LASER can be used, for example, to store a (second) repair address detected by a test performed before the semiconductor device 10 is assembled.

The comparison circuit 202 compares the repair address stored in the fuse circuit 201 with the row address input to the repair determination circuit 20, and outputs a HIT signal if they match.

FIG. 3 shows the internal configuration of the double relief detection circuit 107.

As shown in FIG. 3, the double relief detection circuit 107 includes a first detection circuit 301, a second detection circuit 302, and a third detection circuit 303.

The first detection circuit 301 includes a first AND circuit that calculates a logical product of the outputs of the two relief determination circuits EFUSE 1 and EFUSE 1. The first detection circuit 301 outputs a first detection signal when the HIT signals A and B are simultaneously output from the two relief determination circuits EFUSE1 and EFUSE1. This first detection signal indicates that the same repair address information is written in the repair determination circuits EFUSE 1 and EFUSE 2. That is, the first detection circuit 301 detects whether or not the same relief address information is written in the relief determination circuits EFUSE1 and EFUSE1.

The second detection circuit 302 calculates the logical product of the first OR circuit that calculates the logical sum of the outputs of the two repair determination circuits EFUSE1 and EFUSE1, and the output of the first OR circuit and the output of the repair determination circuit LASER. Second AND circuit. When the HIT signal C is output from the repair determination circuit LASER, the second detection circuit 302 outputs the second signal when the hit signal A and / or B is output from at least one of the two repair determination circuits EFUSE1,2. A detection signal is output. The second detection signal indicates that the same repair address as the repair address information written in the repair determination circuit LASER is written in at least one of the repair determination circuits EFUSE1 and EFUSE1. That is, the second detection circuit 302 detects whether or not the same relief address information as the relief address information written in the relief determination circuit LASER is written in either of the relief determination circuits EFUSE1 and EFUSE1.

The third detection circuit 303 outputs a simultaneous selection negate signal when at least one of the first detection signal from the first detection circuit 301 and the second detection signal from the second detection circuit 302 is output. To do.

Next, the non-defective / defective product selection process included in the manufacturing process of the semiconductor device 10 will be described, and the operation of the semiconductor device 10 at the time of the test, in particular, the double relief detection circuit 107 will be described.

FIG. 4 is a flowchart of a non-defective / defective product selection process included in the manufacturing process of the semiconductor device 10. Writing of the repair address to the repair determination circuit included in the determination circuit 105 is performed in this selection step.

First, a pre-assembly test is performed on the wafer-state semiconductor device 10 obtained by the previous process (wafer process) (step S401) (step S402). Multiple tests are included in the pre-assembly test. These plural types of tests are continuously performed using a single tester (PW tester), and each result (defective address information) is passed on to the next test. Based on the test results obtained after all the tests are completed, the defective dress information is written as the repair address information in the repair determination circuit LASER using the laser trimming apparatus (step S403). In this embodiment, since there is one repair determination circuit LASER provided with a laser fuse element, defective address information detected first is written as repair address information. FIG. 4 shows an example in which the row address “1111h” is written.

Note that the semiconductor device 10 may include a plurality of repair determination circuits LASER. In that case, the same relief address is not written to two or more relief judgment circuits LASER. In other words, the relief address information written in each of the plurality of relief judgment circuits LASER is different from each other, and there is no possibility that double relief occurs. This is because in the pre-assembly test, the result of each test is taken over by the next test, so that the same address is not duplicated and detected as a defective address.

Note that the above description does not mean that a plurality of relief determination circuits including laser fuse elements cannot be used for holding a plurality of independent test results. In other words, a plurality of test results independent of each other can be held in a plurality of relief determination circuits including laser fuse elements. In that case, occurrence of double relief can be detected by using a circuit similar to the first detection circuit 301.

Next, a post-process is performed to package the semiconductor device 10 (step S404). This makes it impossible to write information to the repair determination circuit LASER using the laser trimming apparatus. Therefore, the defective address information detected by the test included in the subsequent post-assembly sorting process is written in the repair determination circuit EFUSE having an electric fuse.

In the post-assembly sorting process, a test is performed using a tester for package memory.

First, a high temperature test is performed (step S405). Then, the first defective address detected by the high temperature test is written as a repair address in the repair determination circuit EFUSE1 (step S406). When a plurality of defective addresses are detected, if the repair determination circuit EFUSE2 is not assigned for a later low temperature test, the second detected defective address is written in the repair determination circuit EFUSE2. Here, it is assumed that the row address “0000h” is written in the repair determination circuit EFUSE1.

Next, a stress test is performed (step S407), followed by a low temperature test (step S408). Then, the defective address first obtained by the low-temperature test is written in the relief determination circuit EFUSE2 as a relief address (step S409).

Here, the tester for package memory is not configured to take over the result of each test to the next test. Therefore, the results of each test are independent, and the same defective address may be detected in different tests. As a result, the relief address written in the relief determination circuit EFUSE1 based on the result of the high temperature test may coincide with the relief address written in the relief determination circuit EFUSE2 based on the result of the low temperature test. For example, the row address “0000h” is written in the relief determination circuit EFUSE2 under the above assumption.

Also, there is a possibility that the relief address written in the relief judgment circuits EFUSE 1 and EFUSE 2 matches the relief address written in the relief judgment circuit LASER.

As described above, if there are those holding the same relief address among the plurality of relief determination circuits LASER, EFUSE1, and 2, when two redundant word lines are simultaneously selected when trying to access the defective address. A double remedy occurs.

Therefore, in the present embodiment, as described above, the double relief detection circuit 107 is provided in the semiconductor device 10 so that it can be confirmed whether or not double relief has occurred. Then, using this configuration, a double relief detection test is performed (step S410).

Here, referring to FIG. 3 again. It is assumed that the row address “0000h” is written in the relief determination circuits EFUSE 1 and EFUSE 2. In the double relief detection test, access to all addresses (write → read) is sequentially performed. In other words, the determination circuit 105 receives an address signal that sequentially designates all addresses. For example, if the address information is 4 bits, address information of 0000h to 1111h is generated by the tester and sequentially input to the determination circuit 105 through the address input circuit 102.

Since the row address “0000h” is written in the repair determination circuits EFUSE 1 and EFUSE 2, the HIT signals A and B are activated when the address “0000 h” is received from the address input circuit 102.

The first detection circuit 301 of the double repair detection circuit 107 detects that both the HIT signals A and B from the repair determination circuits EFUSE1 and EFUSE are activated, and outputs a first detection signal. The first detection signal is supplied to the column decoder 109 through the third detection circuit 303 as a simultaneous selection negate signal.

The column decoder 109 masks the YS signal at the time of reading according to the simultaneous selection negate signal. As a result, the read data is not output to the data amplifier circuit 111, and the tester cannot perform the data read, so that it is possible to recognize that double relief has occurred.

When the repair address written in the repair determination circuit LASER and the repair address written in one of the repair determination circuits EFUSE1 and EFUSE2 match, the second detection circuit 302 detects the HIT signal C and the HIT signal. It detects that at least one of A and B is activated, and outputs a second detection signal. The second detection signal is supplied as a simultaneous selection negate signal to the column decoder 109 through the third detection circuit 303. As a result, the tester can recognize that double relief has occurred.

The double relief detection circuit 107 operates even during normal operation, but different relief addresses are written in a plurality of relief determination circuits included in the determination circuit 105 of the semiconductor device 10 determined to be non-defective. Therefore, the simultaneous selection negate signal is not output. Therefore, the semiconductor device 10 operates normally.

Referring back to FIG. 4, if it is confirmed that double relief has occurred in the double relief test, the semiconductor device 10 is discarded (step S420). Alternatively, one or both of the repair determination circuits EFUSE1 and EFUSE2 may be disabled, and the state where the same repair address is written in two or more repair determination circuits may be eliminated. Further, in the state where the same repair address is written in the repair determination circuits EFUSE1 and EFUSE3 and there is an unused repair determination circuit EFUSE3, both the repair determination circuits EFUSE1 and 2 are disabled, The relief address information that has been written to may be rewritten to the relief judgment circuit EFUSE3.

On the other hand, when it is confirmed by the double relief test that no double relief has occurred, a high temperature test and a room temperature test (operation confirmation test) are performed on the semiconductor device 10 (steps S411 and S412). If these tests are passed, the semiconductor device 10 is determined to be a good product and shipped as a product (step S413).

With the above configuration, the double relief detection circuit 107 outputs a simultaneous selection negate signal when the same relief address is written in a plurality of relief judgment circuits included in the judgment circuit 105. As a result, output of data read from the memory cell array 110 to the data amplifier circuit 111 is blocked. As a result, the tester cannot read data and can confirm that double relief has occurred.

As described above, the semiconductor device 10 according to the present embodiment can confirm the occurrence of double relief.

Next, a second embodiment of the present invention will be described.

The semiconductor device according to the present embodiment is different from the determination circuit 105 and the double relief detection circuit 107 of the semiconductor device 10 according to the first embodiment in that a decision circuit 105-1 and a double relief detection circuit shown in FIG. The difference is that 107-1 is provided. Since the other configuration is the same as that of the first embodiment, the description thereof is omitted.

As shown in FIG. 5, the determination circuit 105-1 includes two repair determination circuits LASER1 and 2 each including a laser fuse element, and two repair determination circuits EFUSE1 and 2 each including an electric fuse element. Including. Corresponding to this, in addition to the configuration of the double relief detection circuit 107, the double relief detection circuit 107-1 further includes a (second) OR circuit for calculating the logical sum of the outputs of the relief determination circuits LASER1 and LASER2. is doing.

According to the above configuration, when the repair address information written in the repair determination circuits EFUSE 1 and EFUSE 2 is the same, the HIT signals A and B are activated. As a result, a detection signal is output from the first detection circuit 301, and a simultaneous selection negate signal is output from the third detection circuit 303 to the column decoder 109.

In the example of FIG. 5, since the row address “0000h” is written in the relief determination circuits EFUSE 1 and EFUSE 2, the HIT signals A and B are activated when the address is “0000 h” from the address input circuit 102. As a result, a detection signal is output from the first detection circuit, and a simultaneous selection negate signal is output from the third detection circuit 303.

If the relief address information written in one of the relief determination circuits LASER 1 and 2 is the same as the relief address information written in either the relief judgment circuit EFUSE 1 or 2, either of the HIT signals A and B is used. One or both of them and either one of the HIT signals C1 and C2 are activated. As a result, a detection signal is output from the second detection circuit 302, and a simultaneous selection negate signal is output from the third detection circuit 303 to the column decoder 109.

In the example of FIG. 5, since the row address “0000h” is written in the repair determination circuit LASER1, the HIT signal C1 is activated when the address is “0000h” from the address input circuit 102. At this time, since the HIT signals A and B are also activated, a detection signal is output from the second detection circuit, and a simultaneous selection negate signal is output from the third detection circuit 303. Note that it is apparent from the configuration that if one of the HIT signals A and B is activated, a detection signal is output from the second detection circuit.

As described above, even in the semiconductor device according to the present embodiment, occurrence of double relief can be confirmed.

As mentioned above, although this invention was demonstrated according to some embodiment, this invention is not limited to the said embodiment, A various deformation | transformation and change are possible in the range which does not deviate from the meaning of invention. For example, in the above embodiment, the example in which the determination circuit includes both the repair determination circuit EFUSE including the electrical fuse element and the repair determination circuit LASER including the laser fuse element has been described. However, the determination circuit includes any one repair determination circuit. It may be a thing. In the above embodiment, the number of relief determination circuits including laser fuse elements is 1 or 2, but may be 3 or more. Similarly, the number of relief determination circuits including electrical fuse elements may be three or more. The configuration of the double relief detection circuit becomes complicated depending on the number of relief judgment circuits, but can be easily realized by a combination of an AND circuit and an OR circuit.

This application claims priority based on Japanese Patent Application No. 2012-207835 filed on September 21, 2012, the entire disclosure of which is incorporated herein.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 101 Command input circuit 102 Address input circuit 103 Internal clock generation circuit 104 Command decoder 105, 105-1 decision circuit 106 Row predecoder 107, 107-1 Double relief detection circuit 108 Row decoder 109 Column decoder 110 Memory cell array 111 Data amplifier circuit 112 Data input / output circuit 20 Relief determination circuit 201 Fuse circuit 202 Comparison circuit 203 Fuse element 301 First detection circuit 302 Second detection circuit 303 Third detection circuit

Claims

A plurality of first relief determination circuits each having an electrical fuse circuit used to hold first relief address information;
A double relief detection circuit for detecting whether or not the same information is present in the plurality of first relief address information held by the plurality of first relief judgment circuits. apparatus.
Further comprising at least one second relief determination circuit having a laser fuse circuit used for holding second relief address information;
The double relief detection circuit includes the second relief address information held by the second relief determination circuit in the plurality of first relief address information held by the plurality of first relief judgment circuits. The apparatus according to claim 1, further detecting whether there is matching information.
Each of the plurality of first relief determination circuits and the at least one second relief judgment circuit is inputted with the first relief address information or the second relief address information held by each from the outside Outputs a match signal when the address information matches,
The double relief detection circuit outputs a detection signal when two or more coincidence signals are simultaneously inputted from the plurality of first relief judgment circuits and the at least one second relief judgment circuit;
The apparatus according to claim 2.
4. The detection signal masks a control signal for controlling a switch provided in a signal path of an output signal to be output from the semiconductor device in response to an input of the input address information. Equipment.
The apparatus according to claim 4, comprising a plurality of memory cells specified by the input address information.
A plurality of bit lines connected to the plurality of memory cells;
A plurality of IO lines respectively corresponding to the plurality of bit lines;
6. The apparatus of claim 5, wherein the switch is connected between the plurality of bit lines and the plurality of IO lines.
Three or more relief determination circuits each capable of holding relief address information;
A double relief detection circuit for detecting whether or not the same information is present in the relief address information held in the three or more relief determination circuits;
A device comprising:
8. The apparatus according to claim 7, wherein each of the relief determination circuits includes a fuse circuit used for holding relief address information.
9. The apparatus according to claim 8, wherein at least two of the three or more repair determination circuits include an electric fuse in the fuse circuit.
10. The apparatus according to claim 9, wherein at least one of the three or more repair determination circuits includes a laser fuse in the fuse circuit.