CN110827869A - Memory device and majority detector thereof - Google Patents
Memory device and majority detector thereof Download PDFInfo
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- CN110827869A CN110827869A CN201810921723.3A CN201810921723A CN110827869A CN 110827869 A CN110827869 A CN 110827869A CN 201810921723 A CN201810921723 A CN 201810921723A CN 110827869 A CN110827869 A CN 110827869A
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
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- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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- G—PHYSICS
- G11—INFORMATION STORAGE
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
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Abstract
The invention provides a memory device and a plurality of detectors thereof. The plurality of detectors include a pull-up circuit, a first switch, a second switch, a plurality of first transistors, a plurality of second transistors, and a sense amplifier circuit. The pull-up circuit provides a first voltage to the first node and the second node according to a control signal before a sensing period. The first switch and the second switch respectively provide a second voltage to the first node and the second node according to the control signal during the sensing period. The control terminals of the first transistors respectively receive one of a plurality of values of the data signal. The control ends of the second transistors respectively receive the inverted value of one of the values. The sensing amplifying circuit generates a sensing result according to a voltage difference between the first node and the second node during sensing, and the sensing result indicates a majority value of the values.
Description
Technical Field
The present invention relates to a memory device and a plurality of detectors thereof, and more particularly, to a memory device with a Data Bus Inversion (DBI) function and a plurality of detectors thereof.
Background
In the field of dynamic memory technology, the interface based on the transmitted data signal is terminated at the reference ground voltage, and therefore, the more bits of a data signal transmitted at a logic high level, the more power consumption. In order to reduce power consumption, a conventional dynamic memory employs a Data Bus Inversion (DBI) technique to invert the logic level of each bit of a Data signal for transmission when the number of bits of a logic high level is a majority (for example, when more than half of 8 values of a Byte (Byte) is 1).
In the detection operation of determining whether the number of bits of the logic high level is the majority, most of the detectors proposed in the prior art usually require more transistors and occupy a larger layout area, thereby causing more power consumption of the memory device, reducing the working efficiency and increasing the production cost. Therefore, how to reduce the power consumption of many detectors, the required number of transistors and the layout area is an important issue for designers in the field.
Disclosure of Invention
The invention provides a memory device and a majority detector thereof, which are used for indicating a majority value in a data signal. A data bus inversion circuit of the memory device outputs an inverted data signal according to a sensing result generated by the plurality of detectors.
The plurality of detectors of the present invention include a pull-up circuit, a first switch, a second switch, a plurality of first transistors, a plurality of second transistors, and a sense amplifier circuit. The pull-up circuit is configured to provide a first voltage to the first node and a second node according to a control signal prior to a sensing period. The first switch is coupled between a second voltage and the first node, and is configured to provide the second voltage to the first node according to the control signal during the sensing period, and the second voltage is greater than the first voltage. The second switch is coupled between a second voltage and a second node and is configured to provide the second voltage to the second node according to the control signal during sensing. The first transistor is coupled between a first node and a third node, and a control terminal of the first transistor respectively receives one of a plurality of values of the data signal, wherein the third node is coupled to a third voltage during the sensing period, and the third voltage is smaller than the first voltage. The second transistor is coupled between the second node and the third node. The control ends of the second transistors respectively receive the inverted value of one of the values. The sensing amplifying circuit is coupled to the first node and the second node, and generates a sensing result according to a voltage difference between the first node and the second node during sensing, wherein the sensing result indicates a majority value of the values.
The memory device of the present invention includes a plurality of detectors as described above and a data bus inversion circuit that outputs an inverted data signal composed of inverted values of the values according to the sensing result generated by the plurality of detectors.
In view of the above, the present invention provides a plurality of detectors including a plurality of first transistors coupled between a first node and a third node and a plurality of second transistors coupled between a second node and the third node, wherein the first node and the second node are pulled up to a first voltage smaller than a second voltage before a sensing period through a pull-up circuit, the first node and the second node are coupled to the second voltage and the third node is coupled to a third voltage smaller than the first voltage during the sensing period, and a sensing result is generated according to a voltage difference between the first node and the second node through a sensing amplifier circuit. Therefore, on the premise of not using a large number of transistors, the power consumption required by a plurality of detectors can be reduced, the detection speed of the plurality of detectors is increased, and the working efficiency of the memory device is effectively improved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 shows a schematic diagram of a plurality of detectors according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a sense amplifier circuit according to an embodiment of the invention;
FIG. 3 is a timing diagram of signals during a read operation of a detector according to an embodiment of the present invention;
FIG. 4 shows a schematic diagram of a plurality of detectors according to another embodiment of the present invention;
FIG. 5 is a schematic diagram of the sense amplifier circuit of FIG. 4 according to the present invention;
FIG. 6A and FIG. 6B are schematic diagrams of memory devices according to different embodiments of the invention.
The reference numbers illustrate:
100. 400, 611 to 61N, 621 to 62N: majority detector
130: pull-up circuit
140. 440, a step of: sensing amplifying circuit
210: transmission circuit
220. 510: comparison and amplification circuit
230. 520, the method comprises the following steps: latch circuit
601. 602: memory device
NAND1, NOR 1: logic gate
IDQij, DQj: data signal
QP 1: first switch
QP 2: second switch
QN 1-QN 27, QP 3-QP 8, QN 51-QN 52, QP 51-QP 52: transistor with a metal gate electrode
QP61, QN 61: transistor with a metal gate electrode
IDQ0 i-IDQ 7i, IDQj 1-IDQj 16: value of data signal
SN: third node
SB: first node
ST: second node
INV1 to INV14, INV51 to INV52, INV 61: reverser
A0i, A01-A016: the result of the detection
DE 0B: control signal
DE1, DE2, DSAN, DSAP: enabling signal
HFVDD: half of the operating voltage
VDD: operating voltage
VSS: reference ground voltage
T1-T4: point in time
CLK: clock signal
DMI: data mask reverse signal
Detailed Description
Referring to fig. 1, a schematic diagram of a plurality of detectors according to an embodiment of the invention is shown. Most of the detectors 100 can be disposed in a memory device having a data bus inversion circuit and adapted to provide sensing results to the data bus inversion circuit. The Memory device may be a dynamic Random Access Memory device, such as a Fourth Generation Low voltage Double Data Rate synchronous dynamic Random Access Memory (LPDDR 4). The majority detector 100 includes first transistors QN 1-QN 8, inverters INV 1-INV 8, second transistors QN 9-QN 16, a pull-up circuit 130, a sense amplifier circuit 140, a first switch QP1, a second switch QP2, a third switch QN18 and a third transistor QN 17. The first transistors QN 1-QN 8 have first terminals commonly coupled to the first node SB, second terminals commonly coupled to the third node SN, and control terminals respectively receiving one of the values IDQ0 i-IDQ 7i of the data signal IDQji. In addition, the first terminals of the second transistors QN 9-QN 16 are commonly coupled to the second node ST, the second terminals are commonly coupled to the third node SN, and the control terminals are respectively coupled to the output terminals of the inverters INV 1-INV 8. The inputs of the inverters INV 1-INV 8 receive the multiple IDQ0 i-IDQ 7i values of the data signal IDQji, and the output generates the inverted values of the IDQ0 i-IDQ 7 i.
According to the number of logic high levels (1) in the values IDQ0 i-IDQ 7i, the number of the first transistors QN 1-QN 8 turned on can be determined, and the equivalent impedance between the third node SN and the first node SB can be further determined. Similarly, the number of the second transistors QN9 to QN16 turned on can be determined according to the number of logic low levels (0) in the values IDQ0i to IDQ7i, thereby determining the equivalent impedance between the third node SN and the second node ST.
The pull-up circuit 130 is configured to pull up the voltages on the first node SB and the second node ST to the first voltage according to the control signal DE0B before the sensing period. The first switch QP1 is coupled between the second voltage and the first node SB, and the second switch QP2 is coupled between the second voltage and the second node ST. The first switch QP1 and the second switch QP2 are configured to be turned on simultaneously according to the control signal DE0B during the sensing period, such that the voltages at the first node SB and the second node ST are pulled up from the first voltage to the second voltage. The first voltage is less than the second voltage. In an embodiment of the invention, the first voltage may be half of the second voltage. The second voltage may be an operating voltage VDD, and the first voltage may be half HFVDD of the operating voltage. The pull-up circuit 130 of the present invention can reduce the time required for the pull-up to the second voltage during the sensing period, thereby increasing the sensing speed. Furthermore, since the first node SB and the second node ST only need to be maintained at the first voltage during the non-sensing period, power consumption of the memory device can be reduced.
The pull-up circuit 130 includes transistors QN 19-QN 21, whose control terminals all receive a control signal DE 0B. The transistor QN19 is connected in series between the first node SB and the first voltage, the transistor QN20 is connected in series between the second node ST and the first voltage, and the transistor QN21 is connected in series between the first node SB and the second node ST.
The transistors QN 19-QN 21 are all N-type transistors, and the first switch QP1 and the second switch QP2 are all P-type transistors. Based on the transistors QN 19-QN 21, the first switch QP1 and the second switch QP2 controlled by the same control signal DE0B, when the transistors QN 19-QN 21 are turned on, the first switch QP1 and the second switch QP2 are turned off; on the other hand, when the transistors QN19 to QN21 are turned off, the first switch QP1 and the second switch QP2 are turned on. Thus, the voltage pull-up operations of the first switch QP1 and the second switch QP2 do not occur simultaneously with the voltage pull-up operation of the pull-up circuit 130.
The sense amplifier circuit 140 is coupled to the first node SB and the second node ST, and generates a sensing result A0i according to a voltage difference between the first node SB and the second node ST during sensing, wherein the sensing result A0i indicates a majority of the values IDQ1i through IDQ7 i. The data bus inversion circuit receives the sensing result A0i, and determines whether to output an inverted data signal composed of the inverted values of IDQ1 i-IDQ 7i according to the sensing result A0 i. The operation time of the sense amplifier circuit 140 is determined according to the enable signals DE1 and DE 2.
The third switch QN18 is coupled between the third node SN and the third voltage, and is configured to be turned on during sensing. In one embodiment, the third switch QN18 is controlled by the inverse of the control signal DE 0B. In the present embodiment, the inverter INV9 receives the control signal DE0B, and provides an inverted signal of the control signal DE0B to the control terminal of the third switch QN 18. The third voltage is smaller than the first voltage, and in the embodiment, the third voltage may be a reference ground voltage VSS.
The third transistor QN17 is connected in parallel with one of the second transistors QN 16. The first transistors QN 1-QN 8, the second transistors QN 9-QN 16 and the third transistor QN17 may all be the same N-type transistors. The control terminal of the third transistor QN17 receives the operating voltage VDD and is constantly turned on, which is configured to provide a bypass (bypass) path coupled to the third voltage for the second transistors QN 9-QN 16 during sensing. Thus, when the number of the logic high levels (1) in the values IDQ1 i-IDQ 7i is half, the voltage drop amplitude of the second node ST is larger than that of the first node SB, i.e., the voltage at the first node SB is higher than that at the second node ST, so that the sense amplifying circuit 140 generates the sensing result A0i equal to the logic low level.
In the embodiment, the current driving capability of the transistors QN 1-QN 17 can be the same, and the N-type transistor constituting the third switch QN18 has a relatively large current driving capability.
In a variation not shown based on this embodiment, the third transistor QN17 is not provided in most of the detectors, and the current driving capability of the second transistor is greater than that of the first transistor. For example, the current driving capability of the second transistor may be 1.2 times that of the first transistor. Thus, when 4 of the IDQ1 i-IDQ 7i are logic high, the voltage at the first node SB can still be higher than the voltage at the second node ST, so that the sense amplifying circuit 140 generates the sensing result A0i equal to logic low.
Fig. 2 is a schematic diagram of a sense amplifier circuit according to an embodiment of the invention. The sense amplifier circuit 140 includes a transmission circuit 210, a comparison and amplification circuit 220, and a latch circuit 230. The transmission circuit 210 includes a first transmission gate formed by transistors QP3 and QN22, a second transmission gate formed by transistors QP4 and QN23, and inverters INV10 and INV 11. The inverters INV10 and INV11 are connected in series, and generate control signals for the transistors QP3, QN22, QP4, QN23 according to the enable signal DE 1. The first transmission gate and the second transmission gate can be turned on or turned off at the same time. The first transmission gate and the second transmission gate are configured to be turned on during the sensing period, so that the voltages at the first node SB and the second node ST can be transmitted to two input terminals of the comparing and amplifying circuit 220.
The compare and amplify circuit 220 includes two cross-coupled transistor pairs. The transistors QP6 and QP7 form a first cross-coupled transistor pair by cross-coupled connection, and the transistors QN24 and QN25 form a second cross-coupled transistor pair by cross-coupled connection. The transistor QP6 is coupled between the operating voltage VDD and the first node SB, and the transistor QP7 is coupled between the operating voltage VDD and the second node ST and receives the operating voltage VDD through the turned-on fourth switch QP 5. The transistor QN24 is coupled between the ground reference voltage VSS and the first node SB, and the transistor QN25 is coupled between the ground reference voltage VSS and the second node ST and coupled to the ground reference voltage VSS through the turned-on fifth switch QN 26.
In the embodiment, the control terminal of the fourth switch QP5 is coupled to the output of the inverter INV10 and is controlled by the inverted signal of the enable signal DE1, and the fifth switch QN26 is controlled by the enable signal DE 1. Thus, when the enable signal DE1 is at a logic high level, the fourth switch QP5 and the fifth switch QN26 are both turned on, and the voltage difference between the first node SB and the second node ST is compared and amplified by the comparing and amplifying circuit 220 to generate a sensing value.
The sensing value generated by the comparing and amplifying circuit 220 is transmitted to the latch circuit 230. In the embodiment, the latch circuit 230 includes a logic circuit implemented by logic gates NAND1 and NOR1, an inverter circuit implemented by transistors QP8 and QN27, and a latch implemented by inverters INV13 and INV 14. The NAND gate 1 is a NAND gate (nandcate) that receives the sensing value and the enable signal DE2 and generates an operation result as the control signal of the transistor QP 8. The logic gate NOR1 is an inverse or gate (NOR gate) that receives the sensing value and an inverse signal of the enable signal DE2 (generated by the inverter INV 12) and generates an operation result as a control signal of the transistor QN 27. With the logic circuit, when the enable signal DE2 is at a logic high level, the inverter circuit can generate the sensing result A0i at the same logic level as the sensing value.
An input end of the inverter INV14 receives the sensing result A0i, an output end of the inverter INV14 is coupled to an input end of the inverter INV13, and an output end of the inverter INV13 is coupled to an input end of the inverter INV 14. As a result, the sensing result A0i can be effectively latched in the latch.
Referring to fig. 1 and fig. 3, fig. 3 shows a timing diagram of signals of a plurality of detectors during a read operation according to an embodiment of the invention. In fig. 3, a clock signal CLK is a base clock signal. Before the time point T1, which includes the precharge period of the majority detector 100, the control signal DE0B is at a logic high level, so that the transistors QN19 to QN21 in the pull-up circuit 130 are turned on, and the first switch QP1 and the second switch QP2 are turned off, so as to pull up the first node SB and the second node ST to the first voltage. At time T1, when the majority of the detectors 100 enter the sensing period, the control signal DE0B is at a logic low level, such that the first switch QP1, the second switch QP2 and the third switch QN18 are turned on, and the transistors QN19 to QN21 in the pull-up circuit 130 are turned off, so as to pull up the first node SB and the second node ST from the first voltage to the second voltage. The values of the data signal IDQji are respectively transmitted to the control terminals of the first transistors, and the inverted values of the values are respectively transmitted to the control terminals of the second transistors. The number of the first transistors and the second transistors that are turned on is determined according to the number of logic high levels in the values, and thus the degree to which the voltages on the first node SB and the second node ST are pulled down is determined. In the present embodiment, when the number of logic high levels in the values IDQ1i through IDQ7i is greater than or equal to 5, the voltage at the first node SB is lower than the voltage at the second node ST. In contrast, when the number of logic high levels among these values IDQ1i through IDQ7i is less than 5, the voltage on the first node SB is higher than the voltage on the second node ST. At time T2, the enable signal DE1 is at a logic high level, and the sense amplifier circuit 140 is activated to compare and amplify the voltage difference between the first node SB and the second node ST to generate a sensing value. At a time point T3, the sense amplifying circuit 140 latches the sensing result A0 i. At a time point T4, the sense amplifying circuit 140 outputs a sensing result A0 i. In the present embodiment, when the number of logic high levels in the values IDQ1 i-IDQ 7i is greater than or equal to 5, the sensing result A0i is logic high. Conversely, when the number of logic high levels among these values IDQ1i through IDQ7i is less than 5, the sensing result A0i is a logic low level.
Based on the sensing result A0i, the memory device can determine whether to enable the data bus inversion circuit to generate the data signal DQj for output. When the detection result A0i is equal to a logic high level, the data bus inversion circuit is enabled to invert these values IDQji of the data signal to generate the data signal DQj for output. In addition, a Data Mask Inversion (DMI) signal DMI of a logic high level is also generated. In contrast, when the detection result A0i is equal to the logic low level, the data bus inversion circuit is not enabled and outputs the data signals DQj equal to the values IDQji of the data signals and generates the data mask inversion signal DMI of the logic low level.
It should be noted that the terminal based on the data transmission interface in the memory device is connected to the reference ground voltage VSS, and thus, current is consumed only when a logic high level value is outputted. In the embodiment, taking the data signal with eight bits (values) as an example, when the values greater than or equal to 5 in the input data signal are logic high, the data bus inversion circuit of the memory device can be enabled, so that the inverted value of the values of the input data signal is used as the output data signal. Therefore, the value of the logic high level in the output data signal is less than half, and the current consumption can be reduced. At this time, the data mask inversion signal DMI is used to notify whether or not the logic level inversion of the data signal occurs.
Referring to fig. 4, fig. 4 is a schematic diagram of a plurality of detectors according to another embodiment of the invention. The same or similar parts of the plurality of detectors 400 and the plurality of detectors 100 are denoted by the same symbols and are not described in detail herein. The portions of the plurality of detectors 400 of the present embodiment that differ from the portions of the plurality of detectors 100 of the previous embodiments are described below. The sense amplifier circuit 440 of the majority detector 400 of the present embodiment receives the enable signals DSAP, DSAN and DE2, and is activated according to the enable signals DSAP, DSAN and DE2 to sense the voltage difference between the first node SB and the second node ST and generate a sensing result A0 i. As shown in fig. 6B, the enable signals DSAP and DSAN are generated according to the enable signal DE1 in the foregoing embodiment. In response to the enabled time interval of the enabling signal DE1, the enabling signals DSAP and DSAN respectively provide the operating voltage and the reference ground voltage to the sense amplifier circuit 440, so that the sense amplifier circuit 440 can operate normally. By such an arrangement, the number of transistors required in the sense amplifier circuit 440 can be reduced, and the cost of the circuit can be reduced.
In a variation, the transistor QN17 can be omitted, and the current driving capability of the second transistor QN9 QN16 is greater than that of the first transistor QN1 QN 8. Thus, during sensing, when 4 of the 8 values IDQ0 i-IDQ 7i of the data signal are at logic high level, the voltage at the second node ST may be slightly lower than the voltage at the first node SB, so that the sense amplifying circuit 440 generates a sensing result A0i equal to logic low level.
For details of the sense amplifier circuit 440 of fig. 4, please refer to the schematic diagram of the sense amplifier circuit shown in fig. 5. In fig. 5, the sense amplifying circuit 440 includes an inverter INV51, an inverter INV52, a comparing and amplifying circuit 510, and a latch circuit 520. Compared to the comparison and amplification circuit 210 of fig. 2, the comparison and amplification circuit 510 includes only the cross-coupled transistors QP51 and QP52 and the cross-coupled transistors QN51 and QN 52. The transistors QP51 and QP52 directly receive the enable signal DSAP, the transistors QN51 and QN52 are directly coupled to the enable signal DSAN, and the enable signal DSAP is equal to the operating voltage VDD and the enable signal DSAN is equal to the reference ground voltage VSS during the sensing period, so as to enable the comparing and amplifying circuit 510. Incidentally, when the comparing and amplifying circuit 510 is disabled from performing the action, at least one of the enabling signals DSAP and DSAN may be a high impedance (high impedance) signal. The latch circuit 520 is similar to the latch circuit 230 in the previous embodiment, and is not repeated herein. The inverter INV51 receives the enable signal DE2, the inverter INV52 receives the output of the inverter INV51, and the logic gate NAND1 receives the sensing value and the output of the inverter INV52, and generates an operation result as the control signal of the transistor QN 8.
Referring to fig. 6A and 6B, fig. 6A and 6B respectively show schematic diagrams of memory devices according to different embodiments of the invention. In FIG. 6A, a memory device 601 includes a plurality of majority detectors 611-61N. The plurality of detectors 611 to 61N commonly receive the enable signals DE1 and DE2 and the control signal DE0B, respectively receive the data signals IDQj1 and IDQj16, and respectively generate the detection results A01 to A016. In the present embodiment, the memory device 601 can be configured with 16 pluralities of detectors 611-61N, and can simultaneously determine the 0, 1 states of 16 sets of 8-bit data signals when the memory device 601 operates in a burst mode.
Of course, as can be seen from the above description, the number of the plurality of detectors provided in the memory device 601 may be changed according to the setting of the burst mode provided by the memory device 601, and is not limited to be fixed.
On the other hand, the plurality of detectors 611-61N of the present embodiment can be implemented according to the plurality of detectors 100 of the embodiment of FIG. 1 of the present invention.
In FIG. 6B, the memory device 602 includes a plurality of detectors 621-62N, transistors QP61, QN61 and inverter INV 61. The plurality of detectors 621-62N commonly receive the enable signal DE1, DSAP, DSAN, DE2 and the control signal DE0B, respectively receive the data signals IDQj 1-IDQj 16, and respectively generate the detection results A01-A016. In the present embodiment, the transistor QP61 receives the operating voltage VDD and the inverted signal of the enable signal DE 1. The transistor QP61 is turned on or off according to the inverse signal of the enable signal DE1, and the plurality of detectors 621-62N receive the enable signal DSAP equal to the operating voltage VDD under the condition that the transistor QP61 is turned on. The inverter INV61 receives the enable signal DE1, and outputs an inverted signal of the enable signal DE1 to the control terminal of the transistor QP 61. The transistor QN61 is turned on or off according to the enabling signal DE1, and the plurality of detectors 621-62N are coupled to the enabling signal DSAN equal to the ground reference voltage VSS under the condition that the transistor QN61 is turned on.
In the present embodiment, the transistor QN61 is an N-type transistor, and the transistor QP61 is a P-type transistor. Thus, transistors QN61 and QP61 can be turned on (or off) at the same time. When the enabling signals DSAP and DSAN are equal to the operating voltage VDD and the ground reference voltage VSS, respectively, the plurality of detectors 621 to 62N can be enabled to sense the voltage difference between the first node SB and the second node ST, and correspondingly, when the enabling signals DSAP and DSAN are both in a high impedance state, the plurality of detectors 621 to 62N are disabled.
In summary, the majority of the present invention comprises a plurality of first transistors coupled between the first node and the third node and a plurality of second transistors coupled between the second node and the third node, wherein the first node and the second node are pulled up to a first voltage smaller than the second voltage before the sensing period by the pull-up circuit. Therefore, the time for pulling the first node and the second node to the second voltage during the sensing period is accelerated. During the sensing period, the third node is coupled to a third voltage smaller than the first voltage, so that the first node and the second node respectively generate voltage drops with corresponding degrees according to the data signal and the inverted data signal, and the voltage difference between the first node and the second node is sensed to indicate the majority value in the data signal. Therefore, on the premise of not using a large number of transistors, the power consumption required by a plurality of detectors can be effectively reduced, the detection speed is increased, and the overall efficiency of the memory device is improved.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (14)
1. A majority detector, comprising:
a pull-up circuit configured to provide a first voltage to the first node and a second node according to the control signal before the sensing period;
a first switch coupled between a second voltage and the first node and configured to provide the second voltage to the first node according to the control signal during the sensing, and the second voltage is greater than the first voltage;
a second switch coupled between the second voltage and the second node and configured to provide the second voltage to the second node according to the control signal during the sensing;
a plurality of first transistors coupled between the first node and a third node, and having control terminals respectively receiving one of a plurality of values of a data signal, wherein the third node is coupled to a third voltage during the sensing period, and the third voltage is less than the first voltage;
a plurality of second transistors coupled between the second node and the third node, control terminals of the plurality of second transistors respectively receiving an inverted value of one of the plurality of values; and
the sense amplifying circuit is coupled to the first node and the second node, and generates a sensing result according to a voltage difference between the first node and the second node during the sensing period, wherein the sensing result indicates a majority value of the plurality of values.
2. The majority detector of claim 1, further comprising:
a third switch coupled between the third node and the third voltage and configured to be turned on during the sensing,
wherein the first transistors and the second transistors are all composed of the same N-type transistor, and the current driving capability of the third switch is greater than the current driving capability of any one of the first transistors and the second transistors.
3. The majority detector of claim 1, further comprising:
a third transistor coupled between the second node and the third node in parallel with one of the plurality of second transistors, and a control terminal of the third transistor receives an operating voltage.
4. The majority detector of claim 3, wherein the pull-up circuit comprises:
a fourth transistor coupled between the first voltage and the first node, and a control terminal of the fourth transistor receiving the control signal;
a fifth transistor coupled between the first voltage and the second node, a control terminal of the fifth transistor receiving the control signal; and
a sixth transistor coupled between the first node and the second node, and having a control terminal receiving the control signal,
the fourth transistor, the fifth transistor and the sixth transistor are all N-type transistors, and the first switch and the second switch are P-type transistors.
5. The majority detector as set forth in claim 2, wherein the sense amplification circuit comprises:
a comparison and amplification circuit for comparing and amplifying the voltage difference between the first node and the second node to generate a sensing value;
and the latch circuit is coupled with the comparison and amplification circuit and used for receiving and latching the sensing value to generate the sensing result.
6. The majority detector according to claim 5, wherein the sense amplification circuit further comprises:
and the transmission circuit receives and determines whether to transmit the voltages on the first node and the second node to the comparison and amplification circuit according to a first enable signal.
7. The majority detector of claim 6, wherein the transmission circuit comprises:
a first transmission gate coupled between the first terminal and the first input terminal of the comparison and amplification circuit, and turned on or off according to the first enable signal; and
a second transmission gate coupled between the second terminal and the second input terminal of the comparison and amplification circuit, and turned on or off according to the first enable signal,
wherein the first transmission gate and the second transmission gate are simultaneously turned on during the sensing to transmit the voltages on the first node and the second node to the comparing and amplifying circuit.
8. The majority detector according to claim 6, wherein the comparison and amplification circuit comprises:
a first cross-coupled transistor pair, one of the first cross-coupled transistor pair being coupled between an operating voltage and the first node, the other of the first cross-coupled transistor pair being coupled between the operating voltage and the second node; and
a second cross-coupled transistor pair, one of the second cross-coupled transistor pair being coupled between a ground reference voltage and the first node, the other of the second cross-coupled transistor pair being coupled between the ground reference voltage and the second node.
9. The majority detector according to claim 8, wherein the compare and amplify circuit further comprises:
a fourth switch, connected in series on a path where the first cross-coupled transistor pair is coupled to the operating voltage, and turned on or off according to the first enable signal; and
a fifth switch connected in series on a path of the second cross-coupled transistor pair coupled to the ground reference voltage and turned on or off according to the first enable signal,
wherein the fourth switch and the fifth switch have the same on or off state.
10. The majority detector according to claim 5, wherein the latch circuit comprises:
the logic circuit is coupled with the comparison and amplification circuit, receives the sensing value and the second enabling signal and generates an operation result;
an inverter circuit, a control terminal of which is coupled to the logic circuit, receives the operation result and generates the sensing result;
a latch configured to be coupled to an output of the inverter circuit to latch the sensing result.
11. The majority detector according to claim 1, wherein the first voltage is half the second voltage.
12. The majority detector according to claim 1, wherein the second voltage is an operating voltage and the third voltage is a ground reference voltage.
13. The majority detector according to claim 1, wherein the current drive capability of each of the second transistors is greater than the current drive capability of each of the first transistors.
14. A memory device, comprising:
a plurality of majority detectors as claimed in claim 1; and
and a data bus inversion circuit outputting an inverted data signal composed of inverted values of the plurality of values according to the sensing results generated by the plurality of detectors.
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