TW579525B - Semiconductor memory device post-repair circuit and method - Google Patents

Abstract

The ability to repair defective cells in a memory array, by replacing those cells with redundant cells, is improved using a redundant memory line control circuit that employs two types of redundancy programming. Most, or all, redundant memory lines can be programmed while the memory array is in a wafer state by, e.g., cutting laser fuses. But at least one memory line can be programmed subsequent to device packaging (""post repair"") using, e.g., commands that cut electric fuses. Preferably, the redundant memory line(s) that are reserved for post repair are selectable among the same redundant memory lines that can be programmed using laser fuses. This allows all redundant memory lines to be available for laser repair, if needed, but also allows a redundant memory line to be selected for post repair after it has been determined that that redundant memory line is defect-free. This increases the likelihood that a device will be repairable, and yet does not unnecessarily waste redundant memory lines by pre-dedicating them to laser or post repair.

Description

579525 V. Description of the invention (1) Technical field to which the invention belongs The present invention relates to a semiconductor memory element repair structure and a repair method, and more particularly, to a post-stage repair structure and method. In the prior art, semiconductor memory devices, such as dynamic random access memory (DR A M) devices, include a plurality of memory cells arranged in a row / row (r 0 w / c 1 u m η) array. Each memory cell typically stores one bit of information. The array includes column signal lines and row signal lines arranged perpendicular to the column lines. The memory cell is placed at each intersection of the row line and the column line. At the same time, the array line and the array line connected to a specific memory unit can access the memory unit. Most applications of semiconductor memory elements require 100% of the memory cells, column lines, and row lines to be operable. In practice, many (or even most) main memory cell arrays on a known wafer (waf e r) may not achieve 100% usability. Therefore, most of the component designs incorporate a relatively small redundant array of memory cells, where the above-mentioned memory cells can replace a limited number of defective cells. In a general design, the redundant array is composed of redundant rows of memory cells, where each cell is connected to a redundant row of lines that crosses the main memory cell array column lines. Each redundant line can thus replace a main memory cell array line that is found to have one or more failed cells. Each time a row of the main array is addressed, a redundant control block will compare the row address (c ο 1 u m n a d d r e s s) with the above

10559pif. Ptd Page 7 579525 V. Description of the invention (2) The address of the faulty line. When the faulty row is addressed, the redundant control block will select a redundant row related to the faulty row address to replace it. A redundant design in which redundant columns are replaced by redundant columns is also used. Some components include circuitry related to redundant columns and redundant rows. Before a redundant control block and its associated redundant rows / columns can be used, the above fault line address must be programmed in the above control block. To simplify programming, the redundant control block includes a fuse block. When the semiconductor memory element is in a wafer state, the main memory array is tested and a faulty cell is located. Considering, for example, row replacement, a redundant control block and a redundant row will be selected to replace a known failing row. The address of the faulty row is set in the redundant control block by selectively cutting the fuse in the fuse block to indicate the row address. Laser beams are usually used to physically cut each fuse to be cut and program the fuses. Issues to be addressed Although most memory array failures are detectable during wafer condition testing, some failures may occur or become apparent for the first time after a memory element package. For such a failure, whether the memory array can be repaired after packaging may affect it as a saleable unit or an obsolete unit. Repairing array failures after encapsulation is called a back-end repair capability. Laser cut-off fuses do not have the ability to repair at the back end because the packaging material prevents laser targeting and fuse-cutting. In contrast, the illustrated embodiments all include an ability to repair the back end of an electrically programmable fuse block.

10559pif.ptd Page 8 579525 V. Description of the invention (3) This type of fuse block can be programmed after the component is packaged by using special programming instruction signals applied to the normal package contacts of the above components. Although the post-repair verbosity is attractive because it allows correction of failures that occur during packaging, this verbosity has disadvantages. The above-mentioned redundant redundant control block and its related electrical programming circuit system require more circuit area than a laser cut-off fuse redundant control block. Therefore, in terms of wafer surface area, the increased cost of using electrical cut-off fuses compared to laser cut-off fuses may outweigh the benefits of later repair capabilities. SUMMARY In a first aspect of the present description, a semiconductor memory device is disclosed. The above memory element includes a dual-mode redundant circuit of a mixed wafer state (such as laser cut) with the advantages of fuse program design and the advantages of post-stage repair program design. Such a circuit includes a plurality of redundant memory circuits (for example, additional row or column circuits, each of which addresses a redundant unit). Each redundant memory circuit is combined with an attached redundant control block. Most redundant control blocks contain laser fuse blocks and can only be programmed before assembly of the above-mentioned memory components. However, at least one of the redundant control blocks includes an electrically programmable silk block, and can be programmed after the assembly of the memory element is packaged. Therefore, this type of component allows a two-cycle repair method: most component repairs are done in a wafer state with a more economical laser fuse block; however, if, for example, a package-related failure occurs in a later repair mode, then A few electrical fuse blocks are available and can be used after package assembly

10559pi f.ptd Page 9 579525 V. Description of Invention (4) Addressed. The above design allows some redundant memory circuits to be used for laser repair, and some redundant memory circuits to be used for later repair. If a redundant memory line used for repair at the back end is itself faulty, the repair at the back end becomes impossible. In fact, although good redundant laser repair memory circuits are still unused, those circuits cannot be used for later repair. Therefore, in the second point of view, a dual mode redundant circuit including a circuit system that is more likely to perform post-stage repair is disclosed. Generally speaking, this circuit system allows a wafer state address storage unit (such as a laser fuse block) to be combined with a redundant circuit. In the second configuration, this circuit system allows a back-end repair address storage unit (such as an electrical fuse block) to be combined with the same redundant circuit. As such, using this dual mode redundant semiconductor memory element allows for additional repair flexibility. For example, during wafer state testing, each redundant line may be combined with a laser fuse block. During the test, a trouble-free redundant memory circuit was designated for later repair. The above redundant memory circuit is combined with the above-mentioned post-stage repair address storage unit, so that it can be used for post-stage repair. In a related method, the semiconductor device has multiple redundant memory circuits, and each of the redundant memory circuits is combined with a laser fuse / comparator. Test the main and redundant memory circuits to determine which circuits are faulty and which circuits are fault-free. For each faulty main memory circuit, a fault-free redundant memory circuit is designated, and a laser fuse / comparator related to the redundant memory circuit is organized to replace the faulty main memory circuit. After this step there is still at least one trouble-free redundant

10559pif.ptd Page 10 579525 V. Description of the invention (5) When the memory circuit is not specified, at least one remaining fault-free redundant memory circuit will be designated for later repair. The redundant memory circuit specified in the above-mentioned post-stage repair is combined with a post-stage repair comparator to replace its associated laser fuse / comparator, and then used for post-stage repair. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Implementation mode: FIG. 1 shows as The block diagram of the semiconductor memory device 20 described in the first embodiment is a synchronous DRAM (SDRAM) in this example. In short, the main cell array 30 and the redundant row cell array 32 are servoed by a column and row circuit system. The above-mentioned row circuit system includes a sense amplifier 34 and a row decoder 50. For each row address CA, the row decoder 50 selects the row (bit) line to be read / written. In the row decoder 50, the redundant memory circuit control circuit 100 determines when a redundant row is to be used for a main row according to the row address CA and the row selection enable signal CSLEN. The above column circuit system includes a column decoder 40 and a column address multiplexer 42. For each column address R A, the column decoder 40 selects which ij (word) line will be activated. The column selection enable signal RS L EN indicates when R A is active. Although redundant column lines and circuits are not shown in element 20, these may exist and are similar to redundant array 32 and control circuit 100. Note that RA has two sources and is gated by the multiplexer 42: the external column address provided by the address register 80; and the one provided by the update counter 46 under the control of the update controller 44. Update the column address.

10559pif. Ptd Page 11 W9525

^, Input and output are generated through three register setting circuits. Refers to 'J: job by, for example-external memory controller (not ^ in ^ order bus 棑 CMD command signals, such as start word line, rV1St, pre-charge, automatic update, load mode register (-heart receive Wait. The address register ⑼ is connected to the address signal ADD [0: m] on the address bus via the memory controller. The data input / output register 90 is connected to the bidirectional data line DQ. [〇: w]. Make the decoder 60 interpret the received instructions directly and generate appropriate control blocks ^ ^ Other memory element blocks. Mode register when %% input mode is temporarily stored as instruction on the CMD bus. The setting circuit (MR s) 6 2 can = receive the component settings on the address bus ADD. Generally speaking, the above uses ^ to define the operating parameters of the SDRAM, such as the burst type, burst length ^ a waiting time, etc. Etc. In a preferred embodiment, when one of the functions of the MRS mentioned above receives a special instruction on the CMD bus, it sets an electrical fuse ... fuse unit of the cover to the address provided on an ADD bus. Return to, but more advanced features exist in many applications of the present invention = 4 & First, the above-mentioned common basic characteristics for most SDRAM elements 1 can support one embodiment of the present invention. Among the characteristics of the element 20, the above-mentioned parties are involved; the embodiment of the present invention will be described in more detail To explore 0 ^ Figure 2 is a block diagram of the basic dual mode ^% line control circuit as described in the first embodiment of the present invention. Referring to Figure 2, redundant line control = circuit 1 0 0 has power Fuse box 1 1 0, address comparator 1 2 0, electrical redundancy control block 1 3 1, laser redundancy control block 1 3 2 to 1 3 η, and redundant line selection

10559pi f.ptd Page 12 579525 V. Description of the invention (7) Selective signal (RCS L) generator 1 4 1 to 1 4 η. The redundant line control circuit 1 0 0 controls the access of redundant lines in n rows in the redundant cell array 3 2 (FIG. 1). When a corresponding redundant row selection signal (RCSLi, i ~ 1 ~ η) is generated by an RCSL generator I4i, one of the above redundant rows will be selected to replace a failed main array row. Each R c s L generator is activated in response to an RCSL start signal (RCSLENi, i = η) corresponding to one of a redundant control block. Each RCSL generator 14i (i = l to η) can be implemented using two series inverters (not shown). Fig. 3 shows the detailed circuit diagrams of the laser redundant control blocks 3 2 to 1 3 η and the electrical redundant control blocks 1 3 1. Each laser redundant control block includes a laser fuse box and an address comparator (ie, a laser fuse / comparison) 1 50. The laser beam can cut the fuse selected in the above-mentioned laser box during the wafer stage repair operation. Thereafter, the laser melting wire / comparator 150 compares the row address C A with the faulty row address stored in the above-mentioned laser fuse box, and generates 0 υ τ when C A matches the stored address. Reverse gate 5 2 together with the serial inverter 1 5 4 generates R cs LE ni according to π and π operations. When OUT and CSLEN (row selection start signal) are generated at the same time, RCSLENi will also be generated, so the selection will be redundant. Line i. The electrical redundant control block 1 3 1 includes a reverse AND gate 160 and a serial inverter 162 ′ for generating RCSLEN1 according to the “and” operation. When EN and CSLEN are generated at the same time, RCSLEN1 will also be generated, so Select redundant line 1. EN is the output of one of the address comparators 120, and is generated when the CA meets ^^ 8 (Figure 2). ECA is an electrical storage from the electrical melting box 1 1 〇 Fault row address. So redundant row lines 2 to η can only be at the wafer level

1 0559pif. Ptd Page 13 579525 V. Description of the invention (8) The period of repair is programmed, but the redundant line 1 can be programmed at any time, for example, during a subsequent repair operation. Figures 4 and 5 show an embodiment of the electrical fuse block 1 110. First referring to FIG. 4, the electrical fuse block 1 1 0 includes a plurality of electrical fuse units (3 1 a, 3 1 i, i = 0 ~ k) with buffered outputs. One bit of metadata is maintained for each electrical fuse unit. The fuse unit 3 1 a holds bit 0 U T a, and 0 U T a after buffering becomes a main access signal M A to indicate whether the above-mentioned electrical fuse box has been programmed. The fuse unit 3 1 i, i = 0 ~ k, maintains 0 UT i, and 0 UT i becomes an electrical row address signal bit ECAi ° mode register setting circuit (MRS) 6 2 (No. Figure 1) Generate programming input (MRSA, MRSCAO to MRSCAk) to fuse box 110 in response to an external command. Initially, each electrical fuse unit is made into a first state, for example, it represents an unset address bit. If a known M R S programming input is generated, the corresponding electrical fuse unit is set to a second state, for example, it represents a set address bit. Therefore, in order to program the fuse box 110, M R S 62 places the repaired row address at M R S C A 0 ~ k to program this address, and generates M R S A to program the above-mentioned main access bit. FIG. 5 is a detailed circuit diagram of an embodiment of an electrical fuse unit 3 1 i (i 2a, 0 ~ k). Each electrical fuse unit 3 1 i has first and second fuses (FI, F2), first to fifth NMOS transistors (N1 to N5), and first and second PMOS transistors (PI, P2). ). The drains of the NMOS transistor N1 and N2, the drain of the PMOS transistor P1, the gate of the PMOS transistor P2, and the gate of the NMOS transistor N3 are all connected to the first node 41 1. Gate of PMOS transistor P1

10559pif. Ptd Page 14 V. Description of the invention (w --------- Cai, NM Π Q + and PMOS thunder gate N2, NMOS transistor N3 and N4 gate The two poles of the second ^ f body 1 " 2 are all connected to the second node 412. The signal appearing on the upper crystal: the Z point also forms an output signal (OUT). Each NMOS electric element F 1 I, the pole are Ground ', and the sources of 1 and 1 " 2 are connected to VDD via fuses and the drain of N5 is connected to the source of P1. Electrical port of fuse ρ 1—Since both fuses remain intact, when power is transmitted to the above fuse == day: drive node 412 (also connected to ουτ) to a logic low level and drive Lang point 4 1 1 to a logic high level. MMMM inputs two first input signals (MRS1), which are usually at a low level, to the gate of the transistor and N4. The input signal MRS1 is used to test whether fuse 1 has been cut off. These will be explained later. ≫ Turn a second input signal (MRS2) to the gate of the transistor ... Input =, MRS2 is used to electrically cut the fuse F1. If the input signal mrs2 is set to High logic level turns on transistor N5 and causes a transient current large enough to blow fuse F 1 to flow through fuse F. When the fuse is cut off, transistor N 5 Also lower the level of the source at the transistor? 丨 and also lower the level at node 4 1 1. When the voltage at node 4 丨 1 decreases, the transistor P2 will be turned on and the transistor N3 will be turned off, so Increasing the voltage at node 4 1 2. This successively promotes the conduction of the crystal N 2, which further decreases the decreasing voltage at point 4 1 1 and further increases the increasing voltage at node 4 丨 2 to 〇U Τ Switch to a high logic level.

After programming, the input signal MRs can be used to determine whether the fuse F 1 is completely cut off due to the generation of the input signal MR S 2. In-test

10559pif.ptd Page 15 579525 V. Description of the invention (ίο) In the test mode, make MR S 1 reach a high level instantly to pull both node 4 1 1 and node 4 1 2 to a low level. If fuse F 1 has been cut off, node 4 1 2 will return to a high level when M R S 1 returns to a low level. If fuse F 1 has not been cut off, node 4 1 1 will return to a high level when M R S 1 returns to a low level. As M R S 1 is generated / disappeared, the repaired address line will be tested. If the above test is unsuccessful, it may be assumed that one or more fuses have not been completely cut off, and thus the redundant line was not successfully used for the failed line. In this case, the above electrical programming and testing steps may be repeated in order to try to cut the fuse again. Fig. 6 is a detailed circuit diagram of an embodiment of the address comparator 12 of Fig. 2. The address comparator 1 2 0 has a plurality of comparison units (5 1 i, i = 0 ~ k), and a plurality of AND gates (A N D) logic gates (the logic gates 520, 522, and 524 are shown). Each AND gate is composed of an inverse AND gate having an inverter at its output. Each comparison unit 51i (i = 0 ~ k) performs a one-bit exclusive OR operation (X N 0 R). The comparison unit 5 1 i receives an electrical comparison address bit (ECA i, i 2 0 ~ k) and a corresponding external part address bit (CA i, i 2 0 ~ k), and compares the two bits. yuan. If the two bits are at the same logic level, the comparison unit 5 1 i outputs a high logic level signal. If the two bits are different, the comparison unit 5 1 i outputs a low logic level signal. An output signal (i = 0 ~ k) of each of the above-mentioned comparison units 51i and the above-mentioned main access signal (M A) will perform an AND operation (A N D) and output as an electrical repair start signal (E N). Therefore, when all comparison units 5 1 0 to 5 1 k

10559pif. Ptd Page 16 579525 V. Description of the invention (11) When the signals output are all high logic levels and the main access signal is also high logic levels, the electrical repair start signal (EN) will be activated. The redundant line control circuits shown in Figs. 2 to 6 and described above, because a redundant line is reserved for subsequent repairs, it provides more enhanced repair capabilities than the redundant structure of the laser fuse . At the same time, by driving most of the redundant rows with a more economical laser fuse control circuit system, this embodiment benefits from the fact that most of the array failures can be detected during wafer stage repair and can be detected. A situation that cannot be corrected in the embodiment of Fig. 2 is a failure of a redundant line related to the electrical redundant control block 1 31. If this redundant line is faulty, even if one or more of redundant lines 2 to η are fault-free and unused, the subsequent stage repair cannot be implemented. Conversely, by allowing one of several redundant rows to be possible to be combined with the electrical redundant control signal, the second embodiment increases the possibility of repair at the later stage. It is preferable that after the wafer is manufactured, a trouble-free redundant line can be designated as a post-stage repair. Similarly, it is better to be able to designate each trouble-free redundant line for laser repair relatively. FIG. 7 shows a redundant row control circuit 2 0 0 of the second embodiment. Although it is similar to Figure 2 in some respects, Figure 7 contains post-repair control blocks 2 51 to 2 5 η, different redundant control blocks 2 3 1 to 2 3 η, and differences in control signals. These differences will be discussed further with reference to Figures 7 to 10. In short, each redundant control block 2 3 i has a laser fuse function, but can be organized to respond to an electrical repair start signal (EN). Therefore, no redundant lines are made unconditionally for later repairs, if necessary

10559pi f.ptd Page 17 579525 V. Description of the invention (12) All redundant lines can be used for laser fuse repair, and after wafer manufacturing, a fault-free redundant line can be used to repair the electrical properties in the above-mentioned later stages. Fuse circuit system combined. This flexibility can provide effective utilization of trouble-free redundant memory circuits during mixed wafer stage and post-repair operations. Similar to the redundant row control circuit 100 in FIG. 2 and the control circuit 200 in FIG. 7 has an electrical property that can be set by using a mode register setting circuit related to the required subsequent repair line address. Fuse box 2 1 0. The address comparator 2 2 0 compares the address ECA from the electrical fuse box 210 with the row address CA and generates EN when the ECA and CA match (and the main access signal MA indicates that the ECA is valid). In Fig. 2, only the electrical redundant control block 1 3 1 receives EN from the electrical repair address comparator 1 2 0. However, in Fig. 7, each redundant control block 2 3 1 to 2 3 n Receive EN from address comparator. Each redundant control block 2 3 i also receives a row address CA and a control signal CSi from a corresponding subsequent repair control block 25 i. CSi decides whether redundant control block 2 3 1 responds to E N or uses CA together with a laser fuse / comparator within redundant control block 2 3 1 to perform redundant line selection. In a typical application, a fuse will be cut in a (and only) back-end repair control block 2 5 i to generate a corresponding CS i signal line (if necessary) to indicate that it will be used in the back-end Redundant lines to fix. FIG. 8 shows the internal circuit system of a redundant control block 2 3 i. Each redundant control block 2 3 i (i = 1 ~ η) outputs a redundant start signal (RCSLENi, i = 1 ~ η) to a corresponding RCSL generator 24i (i = 1 ~ η, Figure 7) ). Each redundant control block 2 3 i has a laser for laser repair

10559pi f.ptd Page 18 579525 V. Description of the invention (13) The radio-repair processing element 6 1 0 and the post-repair processing element 6 2 0 are used. The laser repair processing element 6 1 0 includes a laser fuse box 6 1 1, an address comparator 6 1 2, and a first logic unit 6 1 3. The laser fuse box 6 1 1 has a plurality of fuses that can be cut by a laser beam. By selectively cutting the laser melting wire with a laser, the laser and the valley box can be programmed to generate an address L C A which is used to indicate the main queue of the faulty unit. Similar to the address comparator 2 2 0, when the LCA matches an external address CA, the address comparator 6 1 2 will generate an output signal 0 u T. The logic unit 6 1 3 performs an OR operation on OUT and the control signal CSi to generate a first logic signal T S 1. Therefore, if the control block 2 5 i in the subsequent stage has not generated C S i (meaning that the redundant control block 2 3 i has not been selected for subsequent stage repair), then TS1 copies OUT. However, if CSi is generated, indicating that this is a post-repair block, it will exceed 0 U T and T S 1 will be generated regardless of the state of 0 u T. The post-stage repair processing element 6 2 0 includes an inverter 6 2 1 and a second logic unit 622. The inverter 621 generates CSi #, which is an inverted CSi. The second logic unit 6 2 2 performs an OR operation on CS i # with the electrical repair start signal EN from the electrical fuse address comparator 2 2 0 to generate a second logic signal TS 2. > Therefore, if the back-end repair control block 2 5 i has generated c S i, indicating that this is a back-end repair block, TS2 duplicates EN. However, if ± CSi has not been produced, EN will be exceeded and TS2 will be generated regardless of the state of EN. So obviously, the redundant control block 2 3 i will only respond to the output signal of the comparator 6 12

10559pi f.ptd Page 19 579525 V. Description of the invention (14) One of the sexual repair start signals EN is selected according to the state of C S i. The third logic unit 6 31 is shared by the laser repair processing element 610 and the post-stage repair processing element 620. The third logic unit 631 calculates the first and second logic signals (TS1, TS2) together with the row selection signals CSLNE and (AND), and then outputs redundant start signals (RCSLENi, i2 1 ~ η). When the semiconductor memory element receives a read or write command, an external row address C A (used to designate the main array row to be accessed) will accompany the command. When the main line designated by CA has not been repaired, no repair fuse box (laser or electrical) will contain the above address. When the main line designated by the CA has been replaced by a redundant line during the laser fuse repair at the wafer stage, the laser fuse box 6 having the above line address stored in one of the redundant control blocks 2 3 i 1 1. When the main line designated by CA has been replaced with a redundant line during the subsequent repair period, the above-mentioned line address will be stored in the electrical fuse box 2 10. CA is provided to the address comparator 6 1 2 of each redundant control block 23 i, and is also provided to the electrical fuse address comparator 2 2 0 (FIG. 7). Each address comparator compares CA with its stored address (laser fuse address LCA of comparator 6 1 2 and electrical fuse address ECA of comparator 2 2 0). For a faulty but repaired main line, one of the above address comparators will detect compliance with CA and will generate its output signal (OUT of comparator 6 12 and E N of comparator 2 2 0). If the main line specified by C A has not been repaired, Beij will have no comparator to generate its output signal. The first or main operation mode of each redundant control circuit 2 3 i responds to a laser fuse programming repair address. In this mode, C S i is not generated,

10559pi f.ptd Page 20 579525 V. Description of the invention (15) TS1 responds to OUT and always generates TS2. Thus, when CA and LCA match and a CSLEN is generated to indicate an appropriate row selection output, a redundant row selection signal RCSLENi will be generated. Otherwise, RCSLENi will not be generated. The alternate operation mode of the redundant control circuit 2 3 i responds to the above-mentioned electrical fuse programming repair address. In this mode, C S i is generated, TS1 is always generated, and TS2 responds to EN. Thus, when CA and ECA are found to be in agreement with each other by the address comparator 220 and a CSLEN is generated to indicate an appropriate row selection output, a redundant row selection signal RCSLENi will be generated. Otherwise, RCSLENi will not be generated. In the embodiment of Fig. 7, at most one redundant control block 2 3 i is set to the above-mentioned alternative operation mode. All other redundant control blocks are set to the main operating modes described above. Which control block 2 3 i is set to the above-mentioned replacement operation mode depends on the state of the repair control block 2 5 i in the subsequent stage. Basically, each rear stage repair control block 2 5 i includes a fuse or other configurable element. For example, Fig. 9 is a circuit diagram of an embodiment of a back-end repair control block. In FIG. 9, the post-stage repair control block 2 5 i includes a post-stage repair fuse 7 1 0. The post-stage repair fuse 7 1 0 is a laser fuse that can be cut to change the state of the control signal C S i during the wafer stage test. That is, when the back-end repair fuse 7 1 0 remains intact, C S i will be maintained at a low logic level, and when the back-end repair fuse 7 10 is cut off, C S i will reach a high logic level. In addition to the fuse 7 1 0, the rear repair control block 2 5 i also contains two PM0S transistors P3 and P4, one NM0S transistor N6, and two inverters.

10559pif. Ptd Page 21 579525 V. Description of the Invention (16)

Each of the 712 and 714 ° PMOS transistors P3 and P4 has a source connected to VDD and a drain connected to one of the terminals of the fuse 7 10 (node 8 丨). The N M 0 S transistor N 6 has its source grounded and its drain connected to the reverse terminal of fuse 7 j 〇. Node 8 1 0 is also connected to the input of inverter 7 1 2. Node 8 1 2 is connected to the output of the reverse phase 712, and also connected to the input of the inverter 7 丨 4 and the gate of the pMOS transistor P4. The output of the inverter 714 is set to 1 as a control signal. The last 4 repaired the input signal of the control block 2 5 i to be the power-on signal v [c Η. The waveform of the power-on signal VCCH is shown in Figure 10. When the power is initially supplied to the semiconductor memory device (time T1), the power-on signal% "level is set, and once the power-on level reaches a predetermined level (time τ2), it will transition to a high logic level. It is mentioned the gate of N6. The operation method of the repairing control block 2 5 i at the rear end of the sun and the sun is as follows. The first is the control party of the repair control fuse 7 丨 0 that has been cut off at the later stage. When the body element is initially powered on (time A, picture), the VCCH remains at a low logic level, and thus the crystal p3 is turned on. Because the fuse 710 has been cut off, the node 810 is charged to Vdd: the ugly 712 will eventually sense The node 810 is detected to be a logic high level S bit ° inverted to 812 to a low level and drive CSi to a high logic. At time T2 in FIG. 10, the power-on signal VCCH switches to one / bit. Set VCCH to a high logic level and turn off the question p3, ί is 2 "= 2! The logic level has been turned on PM0: the electric ugly crystal, so the Lang point 81 remains at the logic level 'and the control signal ⑶

Page 22 579525 V. Description of the invention (17) Hold high logic level. Now consider the case where the rear-end repair control fuse 7 1 0 remains intact when the power is turned on. In this case, the node 8 10 initially reaches a high logic level, as in the case where the fuse 7 10 has been cut. However, when the power-on signal VCCH is switched to a high logic level, the transistor N6 is turned on, the transistor P 3 is turned off, and the node 8 10 is discharged to the ground potential. The inverter 7 1 2 senses that the node 8 1 0 is at a low logic level and brings the node 8 1 2 to a high logic level, thereby turning off the transistor P4. The inverter 7 1 4 outputs a control signal CS i with a low logic level. For this embodiment, it is preferable to select the redundant line i to be used for the subsequent repair when the above-mentioned components are in the wafer state. For example, the redundant line can be tested to determine whether it is a fault-free redundant memory line. The above non-faulty redundant memory circuit will be designated for later repair. The designated memory circuit is combined with the latter-stage repair address comparator 2 2 0 by cutting off the laser fuse 7 1 0 of the subsequent-stage repair control block associated with the above-mentioned memory circuit. Similarly, the selection of redundant memory circuits used in the later stage repair can best be done together with the wafer stage laser fuse repair operation. For example, the above main and redundant lines can be tested at the wafer stage to determine which lines are faulty and which lines are fault-free. For each failed main array line, a fault-free redundant memory line will be designated, and the laser fuse box related to the redundant memory line will be programmed with the address of the above-mentioned failed main array line 1 1 (Figure 8). Then, when all faulty main memory lines have been repaired and the fault-free redundant memory lines have not been assigned, those remaining fault-free redundant memory will be assigned

10559pif.ptd Page 23 579525 V. Description of the invention (18) The line is used for the repair of the rear section. The designated redundant memory circuit is cut by cutting the laser fuse of the subsequent-stage repair control block associated with the above-mentioned memory circuit 7 1 0 = combined with the latter-stage repair address comparator 2 2 0. The " package " is used to package the above memory element and enter a second test. If the memory line is found to be faulty in the package, it will issue a command to set the mode register setting circuit 2 6 〇 to set the electrical spinning box 2 ^ 1 G at the address of the fault line. Come and try to fix it. If a back-end repair block 2 5 i is available after laser repair and is designated for back-end repair, the back-end repair should be completed. ^ Although it is best to select the post-repair line during wafer stage testing and programming, other embodiments are possible. For example, the drawing i i does not allow the selection of another back stage repair control circuit embodiment 27 i for the back stage repair via the solder pad 8 3 0. In one case, the pad 830 remains unconnected. The NMOS transistors N7, N8, and N9 pull the node 8 γ 0 to a low level, so that the inverters 7 2 0 and 7 2 2 set c s} to a low logic level ^, ^. In another case, the pads 83 are connected to the top 1), so 0 and 点 Lang point 820 and CSi are one-horse logic level. In order to set csi to a high level and select a known redundant line for subsequent repairs, the solder joint 8 = 0 may be connected to the —VDD solder joint during wire bonding. Or, the bonding pad 8 300 may be connected to a lead on a chip carrier, and the lead may be connected to the VDD externally connected to the above components, so as to select a corresponding redundant line for the subsequent repair. ~ Other alternative embodiments are shown in Figures 2 and 3. This embodiment allows selection to be combined with the post-segment repair comparator 2 2 0 after packaging.

l〇559pif.ptd Page 24 579525 V. Description of the invention (19) Redundant lines. In Fig. 12, through each control circuit MRSPRCi corresponding to one of the mode register setting circuits 2 9 0, electrical programming of each subsequent stage repairs the control block 2 8 i (i =: 1 ~ η). In order to combine a known back-end repair control block 2 8 i with an electrical fuse box address comparator 2 2 0, a command is issued at the same time as an address that generates the above-mentioned control line MRSPRC i, so the back-end repair control block is cut off. 2 8 i is an electric fuse and generates a control signal CSi. In this embodiment, there may be a difficulty in determining which redundant control block 2 3 i (and the corresponding traveling line) is still usable and trouble-free. In order to solve this problem, each back-end repair control block 2 8 1 includes a laser fuse which will be used to avoid the electric fuse of the back-end repair control block 2 8 i being cut off. In this way, during the wafer stage programming, because each redundant control block 2 3 i is used for laser repair, the laser fuse corresponding to the subsequent repair control block 2 8 i is also cut to avoid the above. Electrical programming of the control block for the later repair. When a known redundant line fault is found, the laser fuse corresponding to the subsequent repair control block 2 8 i may also be cut to avoid the electrical program design of the latter repair control block. Then, during the subsequent repair of a fault line, the selection of the rear repair control block 2 8 i and the electric fuse cut-off will be attempted for the first value of i. After this first choice, if the above faulty row has not been repaired, then it can be assumed that the above-mentioned post repair control block 2 8 i is invalid. Then select a new i-value and repeat the above steps until a successful repair is completed, or all i-values have failed the trial, and at this time it cannot be repaired later.

10559pif.ptd Page 25 579525 V. Description of the Invention (20) Figure 13 shows a circuit that may be used as a post-repair control block 2 8 i. The fuse 7 3 0 is an electrical fuse. Control block 2 8 i operates similarly to control block 2 5 i (Figure 9), where for the case where fuse 7 30 remains intact, CS i is at a low logic level after power-on, and for fuse 7 In the case of 30 burnout, CS i is at a high logic level after power-on. In order to cut the fuse 7 3 0, M R S P R C i is generated, thereby energizing the crystal P 7 and causing a large transient current to flow through the fuse 7 3 0. Note that this current also flows through fuse 7 4 0. Therefore, fuse 7 4 0 should be designed to operate this current without causing it to blow out first. In order to prevent the programming of the control block 2 8 i from reaching a high logic level, the laser cut-off fuse 7 4 0 is used. When fuse 7 4 0 is cut off, when M R S P R C i is generated, no transient current will flow through fuse 7 3 0. Although the above embodiment has shown a circuit that allows a single back-end repair operation, the present invention is not limited to this. For example, Fig. 14 is a block diagram of a 900 embodiment of a repair circuit capable of performing a double back-end repair operation. The repair circuit 9 0 0 has a redundant control block 9 3 1 to 9 3 η, an RCSL generator 9 4 1 to 9 4 η, and a rear-end repair control block 9 5 1 to 9 5 η, similar to the latter section shown in FIG. 7 Repair the circuit 2 0 0. However, the repair circuit 900 has two electrical fuse boxes 9 1 1 and 9 1 2 and two address comparators 9 2 1 and 9 2 2, which are different from the latter repair circuit 200. Through the mode register setting signals MRS 1 and MRSCAi, the two electric fuse units 9 1 1 and 9 1 2 can be programmed respectively. Note that the above-mentioned electrical fuse unit can use one mode register setting signal to strobe the remaining mode registers.

10559pif.ptd Page 26 579525 V. Description of the invention (21) The register setting signal enables each electrical fuse unit to be programmed independently. The fuse unit 9 1 1 generates a first electrical row address £ c A 1, and the fuse unit 9 1 2 generates a second electrical row address ECA2. The address comparator 92 1 compares with E C A 1 and generates a first enable signal e n 1 when a match is detected. The address comparator 9 2 2 compares CA and ECA2 and generates a second enable signal EN2 when the two are detected. The first and second start signals (EN1, EN2) of Fu Ri Shou Chan are input to the gamma teaching blocks 9 3 1 to 9 3 η. The control party redundantly controls the control blocks 9 31 to 9 3η according to the control signals (08 丨, bu1 ~ 1] from Houqiaobu 951 to 95! 1, and repairs the start signal (ΕΝ1, ΕΝ2) with 3 ^ repair control block Possibly perform laser == and second electrical complex. However, in the circuit 900, each control circuit is provided with a circuit or a rear circuit: a signal line CSi-1 with EN1, and Csi includes two signals with EN2. When both CSi-1 and cSi_2 are hostile to the signal line, the redundant control block 9 3 i will be used as a laser to repair the low logic level 1 ~ 2 at a high logic level and CSi-2 at a high level. Low trend, square. When the CSi i block 9 3 1 will be used as a post-repair controller ± Gui Guang level, the redundant treasure ECA1. And when CSi — 1 is at a low logic level foot / response repair address second level, the redundant control block 9 3 i will be located at ~ 1 ~ 2 — high $ in response to the repair address ECA2. In order to generate two control signals for the segment repair control, each ~ block contains two laser fuses and two sets of repair circuits similar to those shown in Fig. 9. Fig. I 5 is the repair circuit of Fig. I 2 of the second embodiment. The circuit block 9 5 i system. Deformation of the cube

I0559pif.ptd Page 27 579525 V. Description of the invention (22) Figure. This embodiment allows the correction of possible fault conditions which cannot be corrected by the two Fig. 12 embodiments. The first fault condition is that one line has been repaired by the laser, but the repair line related to the above laser repair has subsequently failed. The second fault condition is that one row has been designated as a back-end repair line, but after this repair attempt, the specified back-end repair line is found to be faulty. Regardless of the above situation, the embodiment in FIG. 12 cannot further repair the specific address with a different redundant line, because this can only be achieved if the above address can start two different repair lines. . In order to solve these fault conditions, the embodiment in FIG. 15 expands the concept of post-repair control block transcendence. The above concepts are further applied between redundant control blocks. As shown in the figure, the redundant control block 2 9 1 generates the overrun signal 0VR1 to the redundant control block 2 9 2 and the redundant control block 2 92 generates the overrun signal 0VR2 to the redundant control block 2 9 3, and this method is repeated. Go to the redundant control block 2 9 η. Any redundant control block that receives a low logic level at its input override signal will perform two actions in response: first, it will pass the low logic level to the override signal generated by the next redundant control block itself; Second, it will prevent the generation of the RCSLEN signal itself, even if there is an address compliance situation that would originally generate the above RCSLEN signal. A redundant control block will generate its own override signal if it is not blocked and the address matches its programmed address. In practice, for this embodiment, the redundant control block 2 9 i and the subsequent repair control block 2 8 i may be used from the block n, and continue to go up to the block 1. For example, suppose that during laser repair, several faults are repaired

10559pif. Ptd Page 28 579525 5. Description of the invention (23) line, and the last one is repaired by laser programming with a known repair address RA3 to redundant control block 2 9 3 to make redundant control block 2 92 and 2 9 1 can be used for rear-end repair (as mentioned above, so the rear-end repair control block 2 8 3 to 28η is closed during laser repair). The redundant control block 2 9 3 generates RCSLEN3 whenever CA is equal to RA3 and CSLEN is activated. Then, a failure was detected at the address R A 3 after packaging and during the post-repair test. This most likely means that redundant lines related to redundant control blocks 2 9 3 have failed. However, the above-mentioned post-repair test cannot tell that this address has been repaired once, so it will try to repair the above address again. First, program the address RA3 to the electrical fuse box 2 1 0. Then the above repair system tried to program the rear repair control block 2 8 η, but this block was closed during the laser repair, so the above attempt failed. Prior to successfully programming a control block to repair the latter stage, the above repair system attempts to program control block 2 8 (η-1) and so on until control block 282. Once programming is complete CS2 will transition to a logic high level. CA is now ECA compliant when testing line RA3. Therefore, both EN and CS2 are generated, and control block 2 9 2 generates RCSLEN2 to select its related redundant rows. At the same time, the redundant control block changes its overshoot signal 0VR2 to a low logic level. Redundant control block 2 9 3, because it is sensed that 0VR2 is now at a low logic level, even if its internal address comparator detects a match, it still prevents RCSLEN3 from being generated. Take this example to further explain that the repair line related to RCSL2 may also be faulty. In this way, no matter how the electrical rear repair, when the test line R A 3

10559pif.ptd Page 29 579525 V. Description of the invention (24) A fault still occurs (perhaps a different fault). The above-mentioned post repair system has an extra post repair control block 2 8 1 available, so the post repair repair block 2 8 1 is programmed. Both c S 1 and C S 2 are now produced. When CA is equal to RA3, the redundant control blocks 291, 292, and 293 sense an internal address matching condition. However, block 291 with priority due to its 0 V R 1 signal prevents redundant control block 2 9 2 from generating RCSLEN2 (block 292 then blocks redundant control block 293). Figure 16 shows an example of a redundant control block 2 9 i that can achieve the function just described. The operation of the laser fuse box 6 1 1 and the address comparator 6 1 2 is the same as that described above with reference to FIG. 8. The logic unit 6 1 3 performs an inverse OR (NOR) operation on 0 U T and the control signal CSi to generate a first logic signal TS1 #. The second logic unit 6 2 2 performs an inverse OR operation on the CSi # and the electrical repair start signal εν to generate a second logic signal TS2 #. The inverse OR gate (641) takes TS1 # and TS2 # as inputs' and generates one of the inputs of the third logic unit 631. The other inputs of logic unit 631 are CSLEN and VR (i-1). The logic unit 6 3 1 performs an AND operation (a N D) on the three signals simultaneously to generate a row selection start signal R C S L E N i. Note that when 0 V R (i-1) is at a logic low level, it effectively prevents the generation of R C S L E N i. Two additional logic gates are used to generate the output override signal OV R 丨. The inverter 6 4 2 inverts 0 V R (i-1). N 0 R gate 6 4 3 receives the output of N 0 R gate 6 4 1 and the output of inverter 642 (as its input). The output of the n〇R gate 643 becomes the output override signal OVRi. During operation, OVR (i-1) will be forced to the low level whenever OV (i-1) is at the low level. If both TS1 # and TS2 # are low level ’means that the redundant control block 2 9 i has detected a bit address compliance,

10559pif.ptd Page 30 579525 V. The description of the invention (25) will also force 0 V R i to a low level. The illustrated embodiment may have many variations. For example, the combination of redundant control blocks and redundant memory circuits may have multiple configurations. It is possible that only some redundant control blocks have dual-mode (wafer stage laser fuse and post-repair programming) capabilities, and this capability does not need to be extended to all redundant control blocks. Similarly, there may also be two post-fix repair addressing / comparison units, in which one of the above addressing / comparison units can be programmed in a part of the redundant control block, and another unit can be programmed in another part, Reduces the need for multiple fuse back-end repair control blocks and multiple CS i signal lines. The post-repair control block does not need to have a 1: 1 correspondence with the redundant control block. For example, the decoding logic may use three fuses to generate seven separate C S i signals (and an unselected condition). The above redundant lines may be redundant rows arranged in a row direction, redundant rows arranged in a column direction, or both. If the redundant line is a redundant line, the fault line is replaced, and if the redundant line is a redundant line, the fault line is replaced. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

10559pi f.ptd Page 31 579525 Brief Description of Drawings Figure 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention; Figure 2 is a block diagram of a first embodiment of a dual-mode repair circuit Figure 3 shows the detailed circuit diagram of the redundant control block of Figure 2; Figure 4, Figure 5 and Figure 6 show the detailed circuit diagram of the electrical fuse block and address comparator of Figure 2; FIG. 7 is a block diagram of a second embodiment of the dual-mode repair circuit, wherein the above embodiment uses a method combining an electrical fuse box with one of a number of redundant lines; FIG. 8 shows the redundancy of FIG. 7 The detailed circuit diagram of the control block; Fig. 9 shows the detailed circuit diagram of the repair control block in the subsequent stage of Fig. 7; Fig. 10 shows the waveform diagram of the power-on signal input to the repair control block in the subsequent stage of Fig. 9, Fig. 11 Another embodiment of the repair control block in the latter stage of FIG. 4 is shown. FIG. 12 and FIG. 13 are the repair circuit block diagram and the repair control block circuit diagram of the third embodiment of the dual-mode repair circuit. Electrical fuse Segment repair block; Figure 14 is a block diagram of a fourth embodiment of a dual-mode repair circuit, where the above embodiment has two separate back-end repair electrical fuse blocks, and either of the two can be combined with any Redundant memory circuit; FIG. 15 is a block diagram of a fifth embodiment of a dual-mode repair circuit, wherein the above embodiment has a redundant control block capable of overriding a previous repair attempt that has failed; and FIG. 6 illustrates an embodiment of the redundant control block of FIG. 15.

10559pif.ptd Page 32 579525 Schematic descriptions Schematic descriptions: 20 Semiconductor memory elements 30 Main unit array 32 Redundant unit array 34 Sense amplifier 40 Column decoder 42 Column address multiplexer 44 Update controller 46 Update counter 50 line decoder 60 instruction decoder 62 mode register setting circuit 70 instruction register 80 address register 90 data input / output register 1 00 redundant line control circuit 110 electrical fuse box 1 20 Address Comparator 13 1 Electrical redundancy control block 132 Laser redundancy control block 133 Laser redundancy control block 1 3 i Laser redundancy control block 13η Laser redundancy control block

10559pif.ptd Page 33 579525

Schematic description 14 1 Redundant row selection signal (RCSL) generator 142 Redundant row selection signal (RCSL) generator 143 Redundant row selection signal (RCSL) generator 14η Redundant row selection signal (RCSL) generator 1 50 Laser fuse box / address comparator 1 52 Inverter 1 54 Inverter 1 60 Inverter 1 62 Inverter 200 Redundant row control circuit 2 10 Electrical fuse box 220 Address comparator 23 1 Redundant control block 232 Redundant control block 233 Redundant control block 23 1 Redundant control block 2 3η Redundant control block 241 Redundant row selection signal (RCSL) generator 242 Redundant row selection signal (RCSL) generator 243 Redundant line selection signal (RCSL) generator 24η Redundant line selection signal (RCSL) generator 25 1 Back-end repair control block 252 Back-end repair control block 253 Back-end repair control block 10559pif.pt d p. 34 579525

Brief description of the drawing 25 1 Back-end repair control block 25η Back-end repair control block 260 Mode register setting circuit 27 i Back-end repair control circuit 28 1 Back-end repair control block 282 Back-end repair control block 283 Back-end repair control block 28 1 Back-end repair control block 28 1 28η Back-end repair control block 290 Mode register-j-ru 5 and set circuit 29 1 Redundant control block 292 Redundant control block 293 Redundant control block 29 i Redundant control block 29η Redundant control block 3 1a Electrical fuse Fuse unit 3 10 Electrical fuse unit 31 1 Electrical fuse unit 3 1 1 Electrical fuse unit 3 1k Electrical fuse unit 41 1 First / r / r ie point 41 2 Second / r / r ie Point 5 10 comparison unit 5 11 comparison unit 10559pif.ptd page 35 579525 simple illustration of the diagram 5 1k comparison unit 5 2 0 π and π logic gate 5 2 2 " and " logic gate 5 2 4 π and "logic gate 6 10 Laser repair processing element 6 11 Laser fuse box 6 12 Address comparator 6 13 First logic unit 6 2 0 Back-end repair processing element 62 1 Inverter 6 2 2 Second logic unit 63 1 Third logic unit 641 OR gate 6 4 2 Inverter 6 4 3 Invertor 7 7 Back-end repair fuse 7 12 Inverter 714 Inverter 7 2 0 Inverter 7 2 2 Inverter 7 3 0 Electrical fuse 7 4 0 Laser fuse Silk 8 12 node 8 2 0 node

10559pi f.ptd p. 36 579525

Schematic description of 830 Welding pad 900 Repair circuit for double rear repair operation 9 11 Electrical fuse box 9 12 Electrical fuse box 92 1 Address comparator 922 Address comparator 93 1 Redundant control block 932 Redundant control Block 933 Redundant control block 93η Redundant control block 94 1 Redundant row selection signal (RCSL) generator 942 Redundant row selection signal (RCSL) generator 943 Redundant row selection signal (RCSL) generator 94η Redundant row selection Signal (RCSL) generator 95 1 Back-end repair control block 952 Back-end repair control block 953 Back-end repair control block 95η Back-end repair control block ADD Address bus CA Row address CAO External address bit CA1 External address bit CAk External Address Bit CMD Instruction Bus 10559pif.ptd Page 37 579525 The diagram briefly explains CS1 control signal CS2 control signal CS3 control signal CS1_1 1 signal line CS2_1 signal line CS3_1 signal line SCN1 signal line CSn_1 signal line CS1_2 signal line EN2 signal line CS2_2 signal line CS2_2 of EN 2 Signal line CSn_2 of EN 2 Signal line CS2 of EN 2 CSi Control signal CSi # Inverted control signal CSn Control signal CSLEN Row selection start signal ECA Electrical fuse address ECAO Electrical repair address bit ECA1 --Electrical line address ECA2 22nd Electrical line address ECAk Electrical repair address bit EN Electrical repair start signal EN1 First start signal EN2 Second start signal FI Section--Fuse

10559pif.ptd Page 38 579525 Brief description of the diagram F 2 Second fuse LCA Laser fuse address M A Main access signal MRS mode register setting circuit MRS1 First input signal MRS2 Second input signal MRSA Weight Temporary programming as 'setting circuit' input MRSCAO mode register setting circuit programming input MRSCA1 mode register setting circuit programming input MRSCAi mode register setting circuit programming input MRSCAk mode register setting circuit Programming input MRSPRC 1 control line MRSPRC i control line MRSPRCn control line N1NM0S transistor N2NM0S transistor N3NM0S transistor N4NM0S transistor N5NM0S transistor N6NM0S transistor N7NM0S transistor N8NM0S transistor N9NM0S transistor OUT output signal

10559pif.ptd Page 39 579525 Brief description of the diagram 0VR1 Override signal 0VR2 Override signal 0VR3 Override signal 〇VR (1-1) Override signal OVR 1 Override signal 〇VR (η-1) Override signal PI PMOS Transistor P2PM0S Transistor P3PM0S Transistor P4PM0S Transistor P5PM0S Transistor P6PM0S Transistor P7PM0S Transistor RA Column Address RCSL1 Redundant row selection signal RCSL2 Redundant row selection signal RCSL 3 Redundant row selection signal RCSLn Redundant row selection signal RCSLEN1 Redundant row selection (RCSL ) Startup signal RCSLEN2 Redundant row selection (RCSL) Startup signal RCSLEN3 Redundant row selection (RCSL) Startup signal RCSLENi Redundant row selection (RCSL) Startup signal RCSLENn Redundant row selection (RCSL) Startup signal RSLEN Column selection start signal

10559pi f. Ptd p. 40 579525

10559pi f.ptd Page 41

Claims (1)

579525 6. Scope of patent application 1. A semiconductor memory device includes: a set of nominally addressable main memory circuits, each of which is connected to a corresponding plurality of main memory units; a first redundant memory circuit Connected to a plurality of first redundant memory units; and a redundant memory circuit control circuit, the first redundant memory circuit can be selected whenever an input address matches a selected memory circuit address The redundant memory circuit control circuit has a main and replaceable settable mode. The main mode selects the redundant memory circuit according to a first comparison of the input address to a first primary storage address. The replacement The mode selects the redundant memory circuit according to a second comparison of the input address to a first replacement storage address, wherein the first replacement storage address can be stored after packaging the memory element. 2. The memory element according to item 1 of the patent application scope, wherein the redundant memory circuit control circuit comprises: a first laser fuse box for storing the first main storage address; a first The post-repair address box is used to store the first replacement storage address; a first main address comparator is used to perform the first comparison and activate a first main signal when the first comparison is evaluated as true A first post-segment repair address comparator for performing the second comparison and activating a first replacement signal when the second comparison is evaluated as true; and a mode selection circuit system for using the main mode based on the The first main signal to select the redundant memory circuit and the 10559pif.ptd Page 42 579525 6. Scope of Patent Application The first replacement signal selects the redundant memory circuit. 3. The memory element as described in item 2 of the scope of patent application, further comprising a mode register setting circuit, wherein the post-repair address box includes a plurality of electrical fuse units to store the first replacement storage address. The electrical fuse units store the first replacement storage address in response to a set of mode register setting signals generated by the mode register setting circuit in response to an external command issued after the component is packaged. 4. The memory element according to item 2 of the scope of the patent application, wherein the mode selection circuit system includes a back-end repair control block having a laser fuse and generating a control signal, and the back-end repair control block acts as the laser. When the fuse is complete, the control signal is set to a first logic level, and if the laser fuse is cut off, the control signal is set to a second logic level. 5. The memory element according to item 4 of the scope of the patent application has a boot signal circuit to generate a boot signal, and the boot signal is maintained at a temporarily low logic level during the boot process of the component until the voltage of the component is provided After reaching a predetermined critical value, the boot signal is switched to a high logic level, and the rear repair control block responds to the boot signal. 6. The memory element according to item 5 of the scope of the patent application, wherein the rear-end repair control block has a latch that responds to the boot signal, and the rear-end repair control block is set when the boot signal is maintained at a low logic level. The latch is a first logic level, and after the start-up signal is switched to a high logic level, the rear-end repair control block can decide to remain in the first logic according to whether the laser fuse has been cut Level or 10559pi f.ptd Page 43 579525 6. Scope of patent application Switch to a second logic level. 7. The memory element as described in item 4 of the scope of patent application, wherein the mode selection circuit system further includes gating logic, which can be determined according to whether the control signal is set to the first or second logic level Copy the first main signal or the first replacement signal as a redundant memory circuit start signal. 8. The memory element as described in item 7 of the scope of patent application, further comprising a row of selection signals as an input of the mode selection circuit system, wherein the redundant memory circuit is activated according to the state of the row of selection signals. 9. The memory element according to item 2 of the scope of the patent application, wherein the mode selection circuit system includes a back-end repair control block having a solder pad and generating a control signal, and the back-end repair control block is connected when the solder pad is connected When the reference voltage is reached, the control signal is set to a first logic level, and when the welding pad is not connected to the reference voltage, the control signal is set to a second logic level. 10. The memory element according to item 9 of the scope of the patent application, wherein the rear-end repair control block further includes a pull-down circuit and a buffer, and the pull-down circuit has a buffer input and the solder connected to the buffer input simultaneously. Pull-down node of the pad, so when the solder pad is not connected to the reference voltage, the pull-down circuit pulls down the buffer input to a low logic level, and when the solder pad is connected to the reference voltage, the buffer The converter input is held substantially at this reference voltage. 1 1. The memory device according to item 2 of the scope of the patent application, wherein the mode selection circuit system includes a solder pad and a control signal 10559pi f.ptd Page 44 579525 6. The repair control block at the back of the patent application number. The repair control block at the back set the control signal to a first logic level when the welding pad is connected to a power supply voltage, and when When the welding pad is connected to a ground voltage, the control signal is set to a second logic level. 12. The memory device according to item 2 of the scope of patent application, further comprising a mode register setting circuit, wherein the mode selection circuit system includes a post-repair control having an electrical fuse and generating a control signal. Block, the latter repair control block sets the control signal to a first logic level when the electrical fuse is complete and sets the control signal to a second logic level when the electrical fuse is cut, The electrical fuse is cut off according to a mode register setting signal generated by the mode register setting circuit in response to an external command issued after the component is packaged. 13. The memory element as described in item 12 of the scope of the patent application, wherein the rear-end repair control block further includes a laser fuse, and the laser fuse has a state to prevent the control signal from being electrically programmed. The changed state. 14. The memory element according to item 2 of the scope of patent application, further comprising a second redundant memory circuit connected to the plurality of second redundant memory units, and the redundant memory circuit control circuit is more It includes: a second laser fuse box for storing a second main storage address; and a second main address comparator for comparing the input address with the second main storage address and when the A second main signal is activated when the comparison evaluates to true; 10559pi f.ptd Page 45 579525 6. Scope of Patent Application The redundant memory circuit control circuit can select the second redundant memory circuit according to the second main signal of the main mode. 15. The memory element described in item 14 of the scope of patent application, wherein the mode selection circuit system can select the second redundant memory circuit according to the first replacement signal of the replacement mode to replace the first redundant memory circuit. Redundant memory lines. 16. The memory element according to item 14 of the scope of the patent application further comprises: a second back-end repair address box for storing a second replacement storage address; and a second back-end repair address comparator To perform a third comparison between the input address and the second replacement storage address, and start a second replacement signal when the third comparison is evaluated as true; wherein the mode selection circuit system can perform the replacement according to the replacement. Mode of the second replacement signal to select the second redundant memory circuit. 17. A semiconductor memory device includes: a set of nominally addressable main memory circuits, each of which is connected to a corresponding plurality of main memory units; a first redundant memory circuit connected to a plurality of A first redundant memory unit and a second redundant memory circuit connected to a plurality of second redundant memory units; a first and a second laser fuse / comparator and a first electrical Fuse / comparator, each of which can store a memory circuit address, compare the memory circuit address with an input address, and activate a comparator output when the comparison is true Signals; and 10559pi f.ptd Page 46 579525 6. Scope of patent application Redundant memory circuit control circuit, which can select the first laser fuse / comparator output signal or the first circuit according to a first programming configuration. One of the two fuses / comparator output signals to select the first redundant memory circuit, and the second laser fuse / comparator output signal or the first One of the electrical fuse / comparator output signals is used to select the second redundant memory circuit. 18. The memory element described in item 17 of the scope of patent application, further comprising a second electrical fuse / comparator similar to the first electrical fuse / comparator, and the redundant memory The circuit control circuit can also select the first redundant memory circuit according to the output signal of the second electrical fuse / comparator selected by a third programming configuration. 19. The memory device described in item 18 of the scope of patent application, further includes a mode register setting circuit capable of receiving an electrical fuse programming signal as part of an external command. The mode register setting The circuit can detect that the first electrical fuse / comparator or the second electrical fuse / comparator is a programming target of one of the programming signals, and can use one as a part of the programming signals Fix the address to program the programming target. 2 0. The memory element described in item 17 of the scope of the patent application, further includes a mode register setting circuit capable of receiving an electrical fuse programming signal as part of an external instruction, and the mode register setting The circuit can program the first electrical fuse / comparator with a repair address as part of the programming signals. 2 1. The memory element according to item 20 of the scope of patent application, wherein the 10559pi f.ptd Page 47 579525 VI. Patent application scope Redundant memory line control circuit includes a repair block after the electric block which has an electrical fuse and generates a control signal for selecting one of the programming configurations. Repair the control block to set the control signal to a first logic level when the electrical fuse is complete and to set the control signal to a second logic level when the electrical fuse has been cut off, where the electrical The fuse is cut off according to a mode register setting signal generated by the mode register setting circuit in response to an external pointer issued after the component is packaged. 2 As described in item 21 of the scope of patent application The memory element further includes a transcend circuit for forcibly selecting the first redundant memory circuit when the redundant memory circuit control circuit is selecting one of the first and second redundant memory circuits. 2 3. The memory element described in item 22 of the scope of the patent application further includes a third redundant memory similar to one of the first and second redundant memory circuits and the laser fuse / comparator. Circuit and a third laser fuse / comparator, the redundant memory circuit control circuit can select a third laser fuse / comparator output signal or the first electrical configuration according to a third program design configuration One of the fuse / comparator output signals to select the third redundant memory circuit. The overrunning circuit can select the second and third redundant memory circuits when the redundant memory circuit control circuit is selecting the second redundant memory circuit. The second redundant memory circuit is forcibly selected when one of them is selected, and the first redundant memory circuit can be forcibly selected when the redundant memory circuit control circuit is selecting one of the first and third redundant memory circuits. Memory circuit. 2 4. The memory element as described in item 21 of the scope of patent application, the latter paragraph 10559pif.ptd Page 48 579525 Six. Patent application scope The repair control block has a laser cut-off fuse, where the laser cut-off fuse is cut off determines whether it can be switched according to a mode register setting signal Disconnect the electrical fuse. 2 5. The memory element as described in item 20 of the scope of patent application, further comprising a circuit for selecting one of the first and second redundant memory circuits when the redundant memory circuit control circuit is selecting the redundant memory circuit. The overriding circuit of the first redundant memory circuit is forcibly selected. 2 6. A method for performing a post-stage repair on a semiconductor memory element having multiple redundant memory circuits and a set of main memory circuits, wherein each of the redundant memory circuits is combined with a laser fuse / comparator, The method includes: testing the redundant memory circuits to determine a fault-free redundant memory circuit; designating the fault-free redundant memory circuit for subsequent repair; and combining the specified fault-free redundant memory circuit The circuit and a back-end repair comparator replace the laser fuse / comparator associated with the memory circuit. 27. —A method for repairing a semiconductor memory element having multiple redundant memory circuits and a set of main memory circuits, wherein each of the redundant memory circuits is combined with a laser fuse / comparator, and the method includes : Before final assembly of the memory element, test the main memory circuits to determine which circuits are faulty and which circuits are fault-free. For each of the faulty main memory circuits, specify the redundant memory. One of the body circuits and organizes the laser fusion associated with the redundant memory circuit 10559pif.ptd Page 49 579525 6. Apply for a patent scope wire / comparator to replace the faulty main memory circuit; and after packaging the assembly of the memory element, test the externally addressable memory circuit to determine if a fault exists A memory circuit, and when a faulty memory circuit exists, a redundant memory circuit is electrically designated to replace the faulty memory circuit. 28. The method as described in item 27 of the scope of patent application, further comprising setting a laser setting fuse associated with each of the redundant memory circuits specified before final assembly to avoid the redundant The memory circuit is electrically designated after assembly of the memory element. 29. The method as described in item 28 of the scope of patent application, further comprising testing the redundant memory circuits before final assembly to determine that the redundant memory circuits are fault-free. 30. The method as described in item 29 of the scope of patent application, further comprising setting a laser setting fuse associated with each of the faulty redundant memory circuits before final assembly to avoid the redundant memory The circuit is electrically designated after assembly of the packaged memory element. 31. The method as described in item 28 of the scope of patent application, wherein electrically designating a redundant memory circuit to replace the faulty memory circuit includes: setting an address associated with the faulty memory circuit in a power circuit Sex fuse box; and loop through a set of repair addresses associated with the redundant memory circuits until all available circuits have been tried or until the failed memory circuit has been selectively replaced, and for each such repair Address 10559pi f.ptd Page 50 579525 6. Scope of Patent Application Attempt to set an electrical fuse related to the repair address and test the address related to the faulty memory circuit to determine the address related to the address Whether the memory circuit is still malfunctioning. 32. The method as described in item 31 of the scope of patent application, wherein cycling the set of repair addresses includes arranging the repair bits in a predefined order corresponding to one of each of the redundant memory circuits' overriding priorities. Address, the address behind the predefined order has a higher override priority, and one of the higher override priorities will select the redundant memory circuit and a known faulty memory circuit location associated with the repair address Address sharing, even if a memory circuit with a lower priority has been combined with the address of the faulty memory circuit in advance. 3 3. The method as described in item 32 of the scope of patent application, further comprising before the final assembly, when one of the redundant memory circuits is designated to be used instead of a faulty main memory circuit, the corresponding The predefined order of priorities specifies the redundant memory circuits. 3 4. —A method for repairing a semiconductor memory element having multiple redundant memory circuits and a set of main memory circuits, wherein each of the redundant memory circuits is combined with a laser fuse / comparator, and the method includes : Before the final assembly of the memory element, test the main memory circuits and the redundant memory circuits to determine which circuits are faulty and which circuits are fault-free, and for each of the faulty main memories Body circuit, designating one of the non-faulty redundant memory circuits and organizing the laser fuse / comparator associated with the redundant memory circuit to replace the faulty main memory circuit; 10559pi f.ptd Page 51 579525 6. Scope of patent application When a fault-free redundant memory circuit has not been specified after the step of replacing a faulty main memory circuit, the remaining fault-free redundant memory circuit will be designated Used for back-end repair; and combining the back-end repair redundant memory circuit specified with a back-end repair comparator to replace the laser fuse / comparator associated with the memory circuit. 35. The method described in item 34 of the scope of patent application, further comprising, after the final assembly of the memory element, testing the main memory circuits to determine which circuits are faulty and which circuits are faultless And when a main memory circuit is determined to be faulty during the retest, the post-stage repair comparator related to the designated post-stage repair redundant memory circuit is organized to replace the faulty main-memory circuit. 36. The method as described in item 34 of the scope of patent application, wherein at least one of the specified post-stage repair redundant memory lines and a post-stage repair comparator include cutting a molten wire, thereby forming the gating logic It is used to combine the back-end repair comparator and the redundant memory circuit and prevent the redundant memory circuit from being combined with its associated laser fuse / comparator. 37. The method according to item 36 of the scope of patent application, wherein cutting the fuse is performed by an external instruction after the memory element is packaged. 38. A semiconductor memory element includes: a redundant circuit that can replace a faulty main memory circuit; a first faulty address storage unit that can only be programmed before assembly of the memory element; The second fault address storage unit can encapsulate the memory element 10559pif. Ptd page 52 579525 VI. The program is designed after assembly of the patent application; and a device for combining the first or the second faulty address storage unit with the redundant circuit. 39. The memory element described in item 38 of the scope of the patent application, further comprising a first and a second address comparator, capable of comparing an input address with those stored in the first and second fault addresses, respectively. The address of the storage unit, wherein the combination device includes a programmable back-end repair control block for activating the first address comparator output in a programmable mode and activating the second address in another programmable mode Comparator output. 4 0. A semiconductor memory element includes: N redundant circuits, N > 2, each redundant circuit can replace a faulty main memory circuit; M first faulty address storage units, M > N / 2, each of the first faulty address storage units is combined with a redundant circuit and can only be programmed before the assembly of the memory element is packaged; and N-M second faulty address storage units, each A second faulty address storage unit is combined with a redundant circuit and can be programmed after the assembly of the memory element is packaged. 41. A semiconductor memory element having a plurality of ordinary memory cells arranged in a matrix composed of columns and rows. The semiconductor memory element includes: at least two redundant lines, which can replace the ordinary memories. Unit fault line; a plurality of redundant control blocks, each of which includes a plurality of redundant control blocks 10559pi f.ptd Page 53 579525 VI. Patent application scope A laser cut-off fuse corresponding to one of the redundant circuits, each redundant control block can perform laser repair, among which there is a choice Ground the selected laser-cuttable fuses and select the redundant line corresponding to the redundant control block to replace one of the faulty lines. Each redundant control block can perform the subsequent repair. The redundant line corresponding to the redundant control block is selected to replace one of the faulty lines in response to a predetermined control signal and an electrical repair start signal; and at least two rear-end repair control blocks, each of which is repaired The control block corresponds to one of the redundant control blocks, and the control signal is output to the redundant control block as a predetermined logic level when the redundant line corresponding to the redundant control block is selected for later repair. 4 2. The semiconductor memory element as described in item 41 of the scope of patent application, further comprising: an electrical fuse box having a plurality of electrically cut-off fuses, and being able to be selected by combining these The grounded electrical fuse is programmed to generate an address that indicates one of the faulty lines; and an address comparator that initiates the electrical repair if the programmed address is the same as an external address Start signal. 43. The semiconductor memory element described in item 42 of the scope of the patent application, further includes a mode register setting circuit that receives a plurality of external instructions and address signals, wherein the mode register setting circuit is precisely used by the mode register setting circuit. The generated signal controls the electrical fuse box in response to the external signals. 4 4. The semiconductor memory device according to item 42 of the scope of patent application, wherein the address comparator has a plurality of comparison units, and each of the comparison units 10559pi f.ptd Page 54 579525 VI. The scope of the patent application receives one bit of the programmed address and one bit of the external address in the electrical fuse box, and if the received If the two bits are the same, a first logic level signal is output, and when the output signals of the comparison units are the first logic level, the address comparator will activate the electrical repair start signal. 45. The semiconductor memory device according to item 42 of the scope of the patent application, wherein each of the redundant control blocks has a laser repair processing element for performing the laser repair, and the laser repair processing element includes : A laser fuse box, including the laser fuses; the laser fuse box is programmed by combining the laser fuses that are selectively cut to generate an indication of the faulty lines An address; and an address comparison unit for outputting an output signal and activating the output signal if the programmed address in the laser fuse box is the same as the external address. 46. The semiconductor memory device according to item 42 of the scope of patent application, wherein each of the rear-end repair control blocks is installed to correspond to one of the redundant control blocks. 47. The semiconductor memory device according to item 42 of the scope of the patent application, wherein each of the rear-end repair control blocks has a laser-cut back-end repair control fuse, and the output from the rear-end repair control block is The control signal has a logic level for controlling whether the fuse is cut or not according to the subsequent repair. 48. The semiconductor memory element according to item 47 of the scope of patent application, wherein the semiconductor memory element is cut off when the semiconductor memory element is in a wafer state. 10559pif.ptd Page 55 579525 VI. Scope of patent application Back-end repair control refining 'and the back-end repair is completed when the semiconductor memory element is in a packaged state. 49. A method for repairing a back-end segment of a semiconductor memory device by replacing redundant circuits with redundant circuits, wherein the semiconductor memory device has a plurality of ordinary memory cells arranged in a matrix composed of columns and rows, and There are two or more redundant lines capable of replacing the faulty lines of the ordinary memory cells, and the post-stage repair method includes: (a) performing a laser using a laser beam when the semiconductor memory element is in a wafer state Repair; (b) Test the redundant lines that were not used in step (a) of the laser repair among the redundant lines; (c) Select at least one of the ones that proved to be of good quality in the test of step (b) Redundant circuit as a circuit used for electrical repair; (d) Testing the semiconductor memory device in a packaged state; (e) Replaced by a circuit used for electrical repair with one detected in step (d) Faulty line. 50. The post-repair method as described in item 49 of the scope of patent application, wherein step (a) includes programming a position indicating the faulty line by selectively cutting a plurality of laser-cut fuses. site. 51. The post-stage repair method as described in item 49 of the scope of patent application, wherein step (e) includes programming an instruction in step (d) by selectively cutting a plurality of electrically disconnectable fuses. The address of the faulty line detected in 10559pif.ptd Page 56