JP2003283319A - Current-controlled drive circuit for semiconductor elements - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a current-controlled drive circuit for semiconductor elements preventing a base current from decreasing when turned on. <P>SOLUTION: An N-channel MOS transistor M21 is provided between the dot side of the secondary winding S of a transformer T and the base terminal of a transistor T1. The anode of a body diode D21 of the N-channel MOS transistor M21 is connected to the secondary winding S side, while the cathode thereof is connected to the base terminal side of the transistor T1. An N-channel MOS transistor M22 is provided between the other end of the secondary winding S and the emitter terminal of the transistor T1. The anode of a body diode D22 of the N-channel MOS transistor M22 is connected to the secondary winding S side, while the cathode thereof is connected to the emitter terminal side of the transistor T1. Thus, even when the voltage of the dot side of the secondary winding S ascends caused by a parasitic resistance Rs at the time of the transistor T1 turned on, the base current is not decreased because a voltage Vgs between the gate of the N-channel MOS transistor M22 and the source is not lowered. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit used for a current control type semiconductor device that controls a current flowing into a control terminal to turn on / off.

[0002]

2. Description of the Related Art As a current control type switching transistor element for driving an inductive load, for example, Japanese Patent Laid-Open No. 6-
The one disclosed in Japanese Patent No. 252408 is known. FIG. 7 shows a conventional drive circuit for driving an inductive load using such a current control type semiconductor device.
The transistor T1 is turned on / off according to the current passed from the drive circuit to the base terminal, and drives an inductive load (not shown) connected to the transistor T1.

The drive circuit comprises a pulse power source 90, a control circuit 92, and N-type MOS transistors 93 and 94. The pulse power source 90 is the pulse generation circuit 9
1, DC power supply Vs, and diodes Ds1 and Ds2
And switches SW1 and SW2, and a transformer T. A primary winding P and a secondary winding S are wound around the transformer T.

In the circuit on the primary winding P side of the transformer T,
A switch SW1 for applying the voltage of the DC power supply Vs to the primary winding P in a positive direction (upward toward dots in the figure)
And SW2 are connected in series. Further, the diode Ds is arranged in a direction in which the current flowing through the primary winding P is circulated.
1 and Ds2 are connected in series. The pulse generation circuit 91 has a pulse-shaped control signal Vg91 to turn on / off a set of switches SW1 and SW2 at a predetermined cycle.
Is output.

In the circuit on the secondary winding S side of the transformer T,
N-type MOS transistors 93 and 94 are connected in series so that the built-in body diodes have opposite polarities. The body diode D93 is an N-type MO
It is built in the S transistor 93. Body diode D
94 is built in the N-type MOS transistor 94. The control circuit 92 includes N-type MOS transistors 93 and 94.
Control signals Vg93 and Vg94 are output so that either one of them is turned on and the other is turned off. A parasitic resistance Rs exists in the wiring that supplies the current to the base terminal of the transistor T1.

The operation timing of the above-mentioned drive circuit will be described. FIG. 8 is a timing chart explaining the operation timing of each part of the drive circuit of FIG. In FIG. 8, a control signal Vg91 output from the pulse generation circuit 91, a voltage V2 induced in the secondary winding S, a control signal Vg94 applied to the gate terminal of the N-type MOS transistor 94,
The control signal Vg93 applied to the gate terminal of the N-type MOS transistor 93, the current I2 flowing into the base terminal of the transistor T1, the base terminal-emitter terminal voltage Vbe of the transistor T1, and the collector terminal-emitter terminal voltage Vce of the transistor T1. Waveforms are shown respectively.

As described above, the control signal Vg91 is repeatedly turned on / off in a predetermined cycle. Control signal Vg9
When 1 becomes H level, the switches SW1 and SW2 are turned on. At this time, the current flowing through the primary winding P of the transformer T increases, and the voltage V2 induced in the secondary winding S increases.
Becomes a positive direction. When the control signal Vg91 becomes L level, the switches SW1 and SW2 are turned off. At this time, the current flowing through the primary winding P of the transformer T is circulated through the diodes Ds1 and Ds2 and reduced, and the voltage V2 induced in the secondary winding S has a negative direction.

At timing t1, the control circuit 92 sets the control signal Vg94 to the H level and the control signal Vg94.
When g93 is set to L level, N-type MOS transistor 9
4 is turned on and the N-type MOS transistor 93 is turned off.
The circuit on the side of the secondary winding S has an N-type MOS transistor 9
The current half-wave rectified by the body diode D93 of 3
Transistor T1 via N-type MOS transistor 94
It flows into the base terminal of. As a result, the transistor T
1 is injected into the transistor T1 and turned on. The current I2 flowing to the base terminal of the transistor T1 gradually increases due to the parasitic inductance existing in the current path on the side of the secondary winding S, and its waveform becomes a pulse-like waveform having an upward slope.

At the timing t2, the control circuit 92 sets the control signal Vg94 to the L level and the control signal Vg
When g93 is set to H level, N-type MOS transistor 9
4 is turned off and the N-type MOS transistor 93 is turned on.
The circuit on the side of the secondary winding S has an N-type MOS transistor 9
The current half-wave rectified by the body diode D94 of 4 is
It flows to the dot side (FIG. 7) of the secondary winding S through the N-type MOS transistor 93. As a result, the transistor T
No. 1 turns off by pulling out the carrier from the base terminal.

[0010]

When the transistor T1 drives an inductive load with a large current, it is necessary to supply a large current to the base terminal of the transistor T1. At this time, a voltage drop occurs due to the parasitic resistance Rs described above, and the N-type MOS transistor is compared with the potential of the base terminal of the transistor T1.
The source potential of the transistor 94 rises. As a result, the gate-source voltage Vgs of the N-type MOS transistor 94 decreases, so the N-type MOS transistor 94
The on resistance of is increased. As a result, the current I2 flowing into the base terminal of the transistor T1 decreases, the transistor T1 is not quickly turned on, and the switching loss of the transistor T1 may increase.

An object of the present invention is to provide a drive circuit for a current control type semiconductor device in which switching loss is suppressed.

[0012]

(1) A drive circuit for a current control type semiconductor device according to the invention described in claim 1 has a positive pulsed current and a negative pulse between a first terminal and a second terminal. A pulse current generating means for alternately generating a rectangular current,
A first switch means interposed between the first terminal of the pulse current generation means and the base terminal of the current control type transistor; a second terminal of the pulse current generation means and an emitter terminal of the current control type transistor. A second switch device interposed between the first switch device and the second switch device,
First rectifying means for flowing a current toward the base terminal, and second
Second rectifying means, which is arranged in parallel with the switching means of (1) and allows a current to flow toward the emitter terminal, and the current control type transistor to be turned on, turns on the second switching means and turns off the first switching means. On the other hand, by providing a switch control circuit that turns on the first switch means and turns off the second switch means during the period in which the current control type transistor is turned off, the above-described object is achieved. (2) The invention according to claim 2 is, in the current control type semiconductor element drive circuit according to claim 1, disposed between the base terminal and the emitter terminal, and is turned off during a period when the current control type transistor is turned on. In addition, it is characterized by further comprising a third switch means which is turned on during a period in which the current control type transistor is turned off. (3) The invention according to claim 3 is characterized in that, in the current control type semiconductor element drive circuit according to claim 2, the third switch means is constituted by a P-type MOS transistor. (4) The invention according to claim 4 is characterized in that, in the current control type semiconductor element drive circuit according to claim 2, the third switch means is constituted by a normally-on type transistor.

[0013]

In the current control type semiconductor element drive circuit according to the present invention, the switching loss of the current control type transistor can be suppressed.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a diagram showing a drive circuit for a current control type semiconductor device according to a first embodiment of the present invention. In FIG. 1, a transistor T1 supplies a drive current to an inductive load (not shown) including a motor and the like. The transistor T1 is turned on / off according to the pulse current IB passed from the drive circuit to the base terminal. The drive circuit includes a pulse power supply 10, a control circuit 12, and an N-type MO.
It is composed of SFETs (hereinafter referred to as MOS transistors) M21 and M22, a P-type MOS transistor M23, and a control power supply circuit 13.

The pulse power supply 10 includes a pulse generation circuit 11
, DC power supply V1, and diodes Ds1 and Ds2
And switches SW1 and SW2, and a transformer T. A primary winding P and a secondary winding S are wound around the transformer T.

In the circuit on the primary winding P side of the transformer T,
A switch SW1 for applying the voltage of the DC power supply V1 to the primary winding P in a positive direction (upward toward dots in the figure)
And SW2 are connected in series with the primary winding P.
Further, in the direction in which the current flowing through the primary winding P is circulated,
The diodes Ds1 and Ds2 are connected in series with the primary winding P. The pulse generation circuit 11 has a switch SW.
A pulsed control signal Vg11 is output to turn on / off 1 and SW2 at a predetermined cycle. Control signal Vg
The frequency of 11 is set sufficiently higher than a drive command for driving the transistor T1 described later.

When the control signal Vg11 goes high, the switches SW1 and SW2 are turned on. At this time, the current flowing through the primary winding P of the transformer T increases, and the voltage V2 induced in the secondary winding S has a positive direction. When the control signal Vg11 becomes L level, the switches SW1 and SW2 are turned off. At this time, the current flowing through the primary winding P of the transformer T is circulated through the diodes Ds1 and Ds2 and reduced. As a result, the secondary winding S
The voltage V2 induced in the negative direction has a negative direction.

In the circuit on the secondary winding S side of the transformer T,
An N-type MOS transistor M21 is provided between the dot side of the secondary winding S and the base terminal of the transistor T1. A body diode D21 is built in the N-type MOS transistor M21, the anode of the body diode D21 is on the side of the secondary winding S, and the cathode is the transistor T1.
Are connected to the base terminal side of. On the other hand, an N-type MOS transistor M22 is provided between the other end of the secondary winding S and the emitter terminal of the transistor T1. A body diode D22 is built in the N-type MOS transistor M22. The body diode D22 has an anode connected to the secondary winding S side and a cathode connected to the emitter terminal side of the transistor T1.

A P-type MOS transistor M23 is connected between the base terminal and the emitter terminal of the transistor T1. A body diode D23 is built in the P-type MOS transistor M23, and the body diode D23 has an anode connected to the emitter terminal side of the transistor T1 and a cathode connected to the base terminal side of the transistor T1. Here, a parasitic resistance Rs exists in the wiring that connects the drive circuit and the transistor T1.

A drive command (control command) for the transistor T1 is sent from an external controller (not shown) to the control circuit 12.
Entered in. When the drive command for the transistor T1 is input, the control circuit 12 turns on one of the N-type MOS transistors M21 and M22 in response to the drive command and turns off the other control signal Vg21 and Vg.
22 are output. The control circuit 12 further controls the control signal V for turning on / off the P-type MOS transistor M23.
Output g23. The control power supply circuit 13 inputs the voltage V2 induced in the secondary winding S and generates power supply voltages VCC + and VCC− to be supplied to the control circuit 12.

FIG. 2 is a diagram for explaining the control power supply circuit 13. Terminal (V2-IN) and terminal (V2-GN
During D), the voltage V2 is applied from the pulse power supply 10 described above. As described above, the voltage V2 is the pulse generation circuit 1
The positive and negative pulse voltages are synchronized with the frequency of the control signal Vg11 of 1. Signal V input to terminal (V2-GND)
When the input waveform of the signal Vg (V2-IN) input to the terminal (V2-IN) is represented with reference to g (V2-GND), the waveform of FIG. 3 is obtained.

Control power supply circuit 13 rectifies and smoothes input voltage V2, and smooths DC voltages VCC + and VC.
C- is output from the terminal (VCC +) and the terminal (VCC-), respectively. DC voltage VCC + and VCC-
Are supplied to the control circuit 12 together with the reference voltage (V2-GND). The reference voltage (V2-GND) is the potential on the non-dot side of the secondary winding S.

In the section A of FIG. 3, the terminal (V
A negative voltage V2 is applied to (2-IN). This allows
A current indicated by flows from the terminal (V2-GND) to the terminal (V2-IN) through the diode DP1 and the capacitor CP1. Charge QP1 in the capacitor CP1
Is stored, and the voltage V (CP1) across the capacitor CP1 in this case is V2-Vd (DP1). Here, Vd (DP1) is a forward voltage drop due to the diode DP1.

In the section B of FIG. 3, the terminal (V
A positive voltage V2 is applied to (2-IN). Positive voltage V
The electric charge QP1 accumulated in the capacitor CP1 is pushed up by 2 to raise the potential of the capacitor CP1. As a result, V2 + (V2-V
A voltage of d (DP1) = 2 * V2-Vd (DP1) is generated. Due to this voltage, a current indicated by is flowing toward the terminal VCC + via the diode DP2. The capacitor CP2 is a smoothing capacitor. The DC voltage between the terminal VCC + and the terminal (V2-GND) is 2 * V2-
It can be expressed as Vd (DP1) -Vd (DP2).
However, Vd (DP2) is a forward voltage drop due to the diode DP2.

On the other hand, in the section B, the terminal (V2
From -IN) to the terminal (V2-GND), the current indicated by flows through the capacitor CN1 and the diode DN1. The charge QN1 is stored in the capacitor CN1,
Voltage V (CN1) across capacitor CN1 in this case
Is V2-Vd (DN1). Here, Vd (DN
1) is a forward voltage drop due to the diode DN1.

In the section C of FIG. 3, the terminal (V
The negative voltage V2 is applied again to (2-IN). Since the accumulated charge QN1 of the capacitor CN1 is lowered by the negative voltage V2, the potential of the capacitor CN1 drops.
As a result, V2 + (V2-
A voltage of Vd (DN1)) = 2 * V2-Vd (DN1) is generated. Due to this voltage, a current indicated by the terminal VCC− flows through the diode DN2. The capacitor CN2 is a smoothing capacitor. DC voltage between terminal VCC- and terminal (V2-GND) is 2 x V2-V
It can be expressed as d (DN1) -Vd (DN2). However, Vd (DN2) is a forward voltage drop due to the diode DN2.

The control circuit 12 outputs the control signal Vg21, the control signal Vg22 and the control signal Vg23 using the DC power supply voltages VCC + and VCC- supplied from the control power supply circuit 13, respectively. That is, the control signal V
The voltage values of g21, Vg22 and Vg23 are VCC + and VCC-. Here, the value of VCC is a number (V), for example, the value of VCC + is +7 (V), and the value of VCC-
Is set to -7 (V).

The operation timing of the above drive circuit will be described. FIG. 4 is a timing chart explaining the operation timing of the drive circuit of FIG. In FIG. 4, a control signal Vg11 output from the pulse generation circuit 11 and a signal Vg (V2-I) input to the above-mentioned terminal (V2-IN).
N), the control signal Vg22 applied to the gate terminal of the N-type MOS transistor M22, and the N-type MOS transistor M
The control signal Vg21 applied to the gate terminal of the transistor 21, the control signal Vg23 applied to the gate terminal of the P-type MOS transistor M23, the current IB flowing into the base terminal of the transistor T1, and the collector terminal-emitter terminal voltage Vce of the transistor T1. The waveforms are shown respectively.

As described above, the control signal Vg11 is repeatedly turned on / off in a predetermined cycle. Timing t1
When the control circuit 12 sets the control signal Vg22 to the H level, the control signal Vg21 to the L level, and the control signal Vg23 to the H level, the N-type MOS transistor M22 turns on, the N-type MOS transistor M21 turns off, and P The type MOS transistor M23 is turned off. The circuit on the side of the secondary winding S has an N-type MOS transistor M21.
The current half-wave rectified by the body diode D21 of the above flows into the base terminal of the transistor T1. This allows
The transistor T1 is turned on by injecting carriers into the transistor T1. The current IB flowing through the base terminal of the transistor T1 gradually increases due to the parasitic inductance existing in the current path on the secondary winding S side,
The waveform becomes a pulse-like waveform having an upward slope.

At timing t2, the control circuit 12 sets the control signal Vg22 to L level and the control signal Vg21 to H level, so that the N-type MOS transistor M22 is turned off and the N-type MOS transistor M21 is turned on. The P-type MOS transistor M23 remains off. In the circuit on the side of the secondary winding S, the current half-wave rectified by the body diode D22 of the N-type MOS transistor M22 goes to the dot side (FIG. 1) of the secondary winding S via the N-type MOS transistor M21. Flowing. As a result, the extraction of carriers in the transistor T1 from the base terminal of the transistor T1 is started.

In the transistor T1, the internal carriers are reduced and the collector terminal-emitter terminal voltage Vce rises. At timing t3 immediately before the transistor T1 is turned off, the control circuit 12 sets the control signal Vg21 to the L level to turn off the N-type MOS transistor M21, and sets the control signal Vg23 to the L level to turn on the P-type MOS transistor M23. This allows
The carrier extraction in the transistor T1 by the half-wave rectified current is completed, the carrier extraction in the transistor T1 via the P-type MOS transistor M23 is performed, and the transistor T1 is gradually turned off.

The carrier extraction current due to the half-wave rectified current is larger than the carrier extraction current via the P-type MOS transistor M23. Completing the carrier extraction by the half-wave rectified current at timing t3 and shifting to the carrier extraction via the P-type MOS transistor M23 increases the R component of the damping factor of the RLC resonance phenomenon and suppresses the voltage oscillation at the base terminal. Lead to things. As a result, the voltage Vbe between the base terminal and the emitter terminal of the transistor T1 is gradually reduced and turned off, and the collector terminal-emitter voltage Vce of the transistor T1 does not oscillate. Further, when the transistor T1 is off, the P-type MOS transistor M23 causes the voltage V between the base terminal and the emitter terminal of the transistor T1.
Since the rise of be is suppressed, the transistor T1 does not accidentally turn on again after turning off.

According to the first embodiment described above,
The following effects can be obtained. (1) The N-type MOS transistor M22, which is turned on when the transistor T1 is turned on, is arranged on the emitter terminal side of the transistor T1. When a large current is supplied to the base terminal of the transistor T1 in order to supply a large current to the inductive load, a voltage drop occurs due to the parasitic resistance Rs described above, and the potential on the cathode side of the body diode D21 for half-wave rectification is the same as that of the transistor T1. It rises compared to the potential of the base terminal. Since the N-type MOS transistor M22 is not arranged at this potential rising position, unlike the prior art, the gate-source voltage Vgs of the N-type MOS transistor M22 does not decrease. Therefore, N
-Type MOS transistor M22 has an increased on-resistance and is a current IB for injecting carriers into the base terminal of the transistor T1.
Does not decrease, the transistor T1 can be quickly turned on, and as a result, the occurrence of switching loss can be suppressed. (2) The P-type MOS transistor M23 is used as the MOS transistor that connects the base terminal and the emitter terminal of the transistor T1 when the transistor T1 is off. After the timing t3 when the transistor T1 is turned off, both the N-type MOS transistor M21 and the N-type MOS transistor M22 are turned off. At this time, the potential on the drain M23D side of the P-type MOS transistor M23 is clipped to the reference voltage (V2-GND) -Vd (D22). However, Vd (D22) is a forward voltage drop due to the body diode D22. Similarly,
The potential on the source M23S side of the P-type MOS transistor M23 is the reference voltage (V2-GND) -Vd (D22) -V.
It is clipped to d (D23). However, Vd (D2
3) is a forward voltage drop due to the body diode D23. As a result, at least the potential of the control signal Vg23 is {-Vd (D22) -Vd (D23) + V (M2
3)}, the P-type MOS transistor M23 can be turned on. That is, the P-type MOS transistor M2 is supplied in a state in which no current flows in the circuit on the secondary winding S side.
Since 3 is turned on, it is not affected by the voltage drop due to the parasitic resistance Rs. The above V (M23) is P
It is a gate-source voltage threshold required to turn on the MOS transistor M23.

(Second Embodiment) FIG. 5 is a diagram showing a drive circuit for a current control type semiconductor device according to a second embodiment of the present invention. Compared to the first embodiment, the P-type MO
Normally-on N-type JF instead of S-transistor M23
ET (hereinafter referred to as a junction transistor) M23B is provided, an N-type MOS transistor M24 and a resistor RM are added, and a control circuit 12B is provided instead of the control circuit 12. Is different.

The control circuit 12B outputs the control signal Vg24 at the same timing as the control signal Vg23. N type MO
The S transistor M24 is turned on / off by the control signal Vg24. When the N-type MOS transistor M24 is turned on, the normally-on N-type junction transistor M23B
The power supply voltage VCC- is applied to the gate terminal of the junction transistor M23B to turn off the junction transistor M23B. When the N-type MOS transistor M24 is turned off, the power supply voltage VCC- applied to the gate terminal of the normally-on N-type junction transistor M23B is cut off. At this time, since the gate-source of the junction transistor M23B is connected by the resistor RM, the gate-source voltage of the junction transistor M23B is set to 0V. As a result, the junction transistor M23B is turned on.

FIG. 6 is a timing chart for explaining the operation timing of the drive circuit of FIG. At timing t1 in FIG. 6, the control circuit 12B sets the control signal Vg22 to the H level, the control signal Vg21 to the L level, and the control signal Vg24 to the H level.
Transistor M22 is on, N-type MOS transistor M
21 is turned off and the N-type MOS transistor M24 is turned on. When the N-type MOS transistor M24 is turned on, the power supply voltage VCC- is changed to the normally-on N-type junction transistor M2.
Since it is input to the gate terminal of 3B, the junction type transistor M23B is turned off. At this time, a current half-wave rectified by the body diode D21 of the N-type MOS transistor M21 flows into the base terminal of the transistor T1, so that the transistor T1 is injected with carriers and turned on.

At timing t2, the control circuit 12B
Sets the control signal Vg22 to L level and the control signal Vg21 to H level, the N-type MOS transistor M22 is turned off and the N-type MOS transistor M21 is turned on. As a result, the current half-wave rectified by the body diode D22 of the N-type MOS transistor M22 becomes
It flows to the dot side (FIG. 5) of the secondary winding S through the OS transistor M21 and starts the extraction of carriers in the transistor T1 from the base terminal of the transistor T1.

In the transistor T1, the internal carriers are decreased and the collector terminal-emitter terminal voltage Vce is increased. At a timing t3 immediately before the transistor T1 is turned off, the control circuit 12B controls the control signal Vg21.
Is set to L level to turn off the N-type MOS transistor M21, and the control signal Vg24 is set to L level to N level.
The type MOS transistor M24 is turned off. N-type MOS
When the transistor M21 is turned off, the extraction of carriers in the transistor T1 by the half-wave rectified current is completed. On the other hand, when the N-type MOS transistor M24 is turned off, the junction type transistor M23B is turned on as described above.
Therefore, the carriers are extracted through the path via the junction type transistor M23B, and the transistor T1 is gradually turned off.

Also in the second embodiment described above, it is possible to obtain the same operational effect as that of the first embodiment. That is, since the gate-source voltage Vgs of the N-type MOS transistor M22 does not decrease when the transistor T1 is turned on, it is possible to quickly turn on the transistor T1 and suppress the occurrence of switching loss. Also, when the transistor T1 is off, the transistor T
The normally-on N-type junction transistor M23B is used as a transistor for connecting the base terminal and the emitter terminal of No. 1 and the gate and source of the junction type transistor M23B are connected by the resistor RM. Therefore, the junction transistor M23B can be turned on without being affected by the voltage drop due to the parasitic resistance Rs at the timing of turning off the transistor T1.

In the second embodiment described above, the N-type JFET is described as an example of the normally-on device, but other conductivity type devices may be used.

Correspondence between each component in the claims and each component in the embodiment of the invention will be described. The first terminal corresponds to the dot side of the secondary winding S, for example. The second terminal corresponds to the non-dot side of the secondary winding S, for example. The pulse current generating means is composed of, for example, the pulse power supply 10. The first switch means is, for example, an N-type MOS transistor M2.
It is composed of 1. The second switch means is composed of, for example, an N-type MOS transistor M22. The first rectifying means is, for example, a body diode D.
21. The second rectifying means is composed of, for example, a body diode D22. Third
The switch means is constituted by, for example, a P-type MOS transistor M23 (N-type normally-on JFET M23B). Note that each component is not limited to the above configuration as long as the characteristic function of the present invention is not impaired.

[Brief description of drawings]

FIG. 1 is a diagram showing a drive circuit for a current control type semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a control power supply circuit.

FIG. 3 is a diagram showing an input signal waveform of a control power supply circuit.

FIG. 4 is a diagram illustrating an operation timing of the drive circuit in FIG.

FIG. 5 is a diagram showing a drive circuit for a current control type semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating an operation timing of the drive circuit in FIG.

FIG. 7 is a diagram showing a drive circuit of a current control type semiconductor device according to a conventional technique.

8 is a timing chart illustrating operation timing of the drive circuit of FIG.

[Explanation of symbols]

10 ... Pulse power supply, 11 ... Pulse generation circuit, 12, 12B ... Control circuit, 13 ...
Control power supply circuit, M21, M22, M24 ... N-type MOS transistor, M23 ... P-type MOS transistor, M
23B ... N type normally-on JFET, T1 ... transistor, T ... transformer, RM ... resistor

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Claims (4)

[Claims] 1. A pulse current generating means for alternately generating a positive pulsed current and a negative pulsed current between a first terminal and a second terminal, and the first terminal of the pulse current generating means. A first switch means interposed between the base terminal of the current control type transistor and a second switch means interposed between the second terminal of the pulse current generation means and the emitter terminal of the current control type transistor. Switch means, a first rectifying means arranged in parallel with the first switch means and flowing a current toward the base terminal, and a second rectifying means arranged in parallel with the second switch means and connected to the emitter terminal. Second rectifying means for flowing a current flowing therethrough and the second switch means are turned on and the first switch means are turned off during a period in which the current control type transistor is turned on. The period for turning off the current control transistor, the first current control type semiconductor device for driving circuit characterized by comprising a switch control circuit for turning off said second switch means together to turn on the switching means. 2. The current control type semiconductor element drive circuit according to claim 1, wherein the current control type semiconductor element drive circuit is disposed between the base terminal and the emitter terminal.
The current control type semiconductor device drive circuit further comprising third switch means which is turned off during a period when the current control type transistor is turned on and is turned on during a period when the current control type transistor is turned off. 3. The drive circuit for a current control type semiconductor device according to claim 2, wherein the third switch means is a P-type MOS transistor. 4. The drive circuit for a current control type semiconductor device according to claim 2, wherein the third switch means is a normally-on type transistor.