JP6675867B2 - Switching power supply - Google Patents

Description

  The present invention relates to a switching power supply device that converts DC power of an input DC voltage into DC power of a predetermined output voltage by an FET.

  Conventionally, a switching power supply device as shown in FIG. 4 is used to convert a DC power of an input DC voltage to obtain a DC power of a predetermined output voltage. FIG. 1 illustrates a circuit configuration of a step-down chopper that steps down a DC input voltage to a predetermined DC voltage.

  In FIG. 4, the DC input voltage Vi has its pulsating component smoothed by a capacitor C1 and applied to, for example, a P-channel FET Q1. The FET Q1 repeats ON / OFF in response to the control signal a from the control circuit 50, and chops the DC input voltage Vi. The energy stored in the reactor L when the FET Q1 is on is released through the diode D1 when the FET Q1 is off, and is smoothed by the capacitor C2 forming a smoothing filter together with the reactor L, so that the DC output voltage Vo is reduced. It is supplied to a load (not shown).

  The control circuit 50 outputs a control signal a including a duty pulse. That is, the control signal a is adjusted so that the pulse width increases as the output voltage Vo decreases and the pulse width decreases as the output voltage Vo increases, and the DC output voltage Vo is adjusted by the control signal a. Feedback controlled. As a result, the DC output voltage Vo is controlled to have a constant value regardless of the fluctuation of the input DC voltage Vi.

  This switching power supply device has conventionally been required to increase the switching speed of the FET Q1 to reduce the switching loss in order to improve the power conversion efficiency. Therefore, the gate resistance R1 of the FET Q1 is set to an appropriate constant that does not cause overdrive or underdrive, and the ratio of the resistance r1 of the gate resistance R1 to the resistance r5 of the gate-source resistance R5 of the FET Q1 is set. It is known that r5 / r1 is made as small as possible to reduce the time required for the FET Q1 to turn off.

  However, in the method for improving the power conversion efficiency, there is a limit in increasing the switching speed. That is, even if the resistance ratio r5 / r1 is set to be too small, the on-resistance of the FET Q1 increases and the switching loss increases. Conversely, even if it is set too large, a large amount of charge is accumulated in the gate, so that it does not turn off completely immediately, and the drain current ID continues to flow, so that the timing at which the FET Q1 actually turns off tends to be delayed. . In this case, as in the γ period of FIGS. 5A and 5B, the drain-source voltage VDS of the FET Q1 and the drain current ID overlap without zero-crossing, a switching loss occurs, and the power conversion efficiency is sufficiently improved. Can't improve. When the FET Q1 is off, the gate-source voltage VGS is 0 V as in the period ε in FIG. 5C.

  Further, for example, in a synchronous rectification application of a switching power supply using an FET having a parasitic diode such as a MOS-FET, in order to prevent a reverse current (through current) from flowing in a forward direction of the parasitic diode, It is required that the reverse recovery time (Trr) be fast, and the timing of turning on / off the FET is important. Conventionally, as an example of this, a switching power supply circuit that improves the power conversion efficiency by optimally controlling the off-timing of a MOS-FET by driving a drive circuit is known (for example, Patent Document 1).

JP 2011-72160 A

  By the way, in order to improve the power conversion efficiency by reducing the switching loss by increasing the switching speed of the FET, or to sufficiently reduce the noise caused by the reverse recovery time (Trr) when the FET is off, etc. A negative voltage generating circuit is provided that operates by including a negative voltage by shifting the voltage of the square wave to the negative side by driving the drive circuit, and applying a negative voltage to the gate voltage of the MOS-FET to turn off the MOS-FET. It is assumed that This negative voltage generating circuit is configured by, for example, connecting a Zener diode ZD1 and a capacitor C5 in parallel.

  In this case, the operation of the device requires that the capacitance of the capacitor C5 >> the input capacitance Ciss (Cgs) of the MOS-FET. When the MOS-FET is turned on, the input capacitance Ciss of the MOS-FET is almost equal to the power supply voltage. Charged up to. At this time, the capacitor C5 is hardly charged. As a result, when the MOS-FET is off, almost no negative voltage is applied between the gate and the source. Then, the negative voltage generation circuit does not operate sufficiently, and it is difficult to reduce the intended switching loss, improve the power conversion efficiency, and prevent malfunction due to noise.

  Further, simply using an FET having a high switching speed improves the power conversion efficiency, but has a problem that noise is easily generated. Therefore, it is required to realize a technique for making the negative voltage generating circuit sufficiently operate on the device to further increase the switching speed of turning off the FET.

  Further, if the rise of the gate voltage of the MOS-FET is steep when the switching power supply device is started, a malfunction may occur due to the junction capacitance of the parasitic diode and LC resonance caused by the circuit wiring.

  The present invention solves the above-mentioned problems, can increase the switching speed of the FET, reduce the switching loss and improve the power conversion efficiency with a simple configuration, and improve the power conversion efficiency when the switching power supply is started. An object of the present invention is to provide a switching power supply device capable of preventing a malfunction by making a rise of a gate voltage gentle.

In order to achieve the above object, a switching power supply according to one configuration of the present invention converts a DC power of a DC voltage to be input into a DC power of a predetermined voltage by controlling on / off of a FET by driving a drive circuit. It is converted and output.
The drive circuit includes:
A switching element for FET operation connected between the DC input side of the FET and the control electrode; a first capacitor connected between the control electrode of the switching element for FET operation and the output side of the FET; When the FET starts to be turned off, the charging current of the first capacitor is caused to flow through the control electrode of the switching element for FET operation in response to the voltage drop on the output side, whereby the switching for FET operation is performed. A quick-off control circuit for turning on the element and rapidly switching off the FET;
When the FET operation switching element is turned on, a negative voltage is applied to the control electrode of the FET to increase the speed of switching off the FET so that the voltage of the control electrode of the FET is shifted to the negative side to include the negative voltage. An operating negative voltage generating circuit, disposed between the negative voltage generating circuit and the control electrode of the FET, operating the negative voltage generating circuit so as not to be affected by the parasitic diode of the FET, including the negative voltage A protection circuit for applying a voltage to the control pole of the FET. Here, the FET refers to a switching element including a MOS-FET, an IGBT element partially including an FET, and the like.

  According to this configuration, when the FET starts to be turned off by the quick-off control circuit and the potential on the output side thereof is slightly lower than the potential on the DC input side, the control electrode of the FET operation switching element is controlled from the DC input side. A charging current flows through the first capacitor to charge the first capacitor, and the switching element for FET operation is momentarily turned on to rapidly turn off the FET. At the same time, when the switching element for FET operation is turned on, the voltage of the control electrode of the FET is shifted to the negative side to include the negative voltage when the switching element for FET operation is turned on. The switching speed is increased. At this time, the negative voltage generating circuit is operated sufficiently by the protection circuit so as not to be affected by the parasitic diode of the FET, and a voltage including the negative voltage is applied to the control electrode of the FET. Therefore, since the FET is turned off immediately, the switching speed of turning off is increased as much as possible to reduce the switching loss and to improve the power conversion efficiency.

  In the present invention, the FET is a MOS-FET, and the protection circuit is provided between a gate and a source of the MOS-FET, and includes a diode and a second resistor and a second capacitor connected in parallel. It is preferable to increase the time constants of the second resistor and the second capacitor of the protection circuit so as to make the rise of the gate voltage of the MOS-FET slower. In this case, with a simple configuration, at the time of inputting a surge voltage at the time of starting the switching power supply, the rise of the gate voltage of the MOS-FET is moderated, and the occurrence of LC resonance due to the junction capacitance of the parasitic diode and the circuit wiring is suppressed. Generation of noise can be suppressed, and malfunction can be prevented.

  Preferably, the quick-off control circuit has a snubber circuit including the first capacitor and a first resistor. Therefore, the breakdown voltage applied to the FET can be reduced.

  Preferably, the switching power supply circuit forms a step-down chopper. In this case, for the step-down chopper, the switching speed of the FET can be increased as much as possible to reduce switching loss and improve power conversion efficiency.

  According to the present invention, the FET is quickly switched off by the quick-off control circuit, the switching speed of the switch-off is further increased by the negative voltage generation circuit, and the negative voltage is controlled by the protection circuit so as not to be affected by the parasitic diode of the FET. Since the generation circuit is operated, it is possible to reduce the switching loss as much as possible and to improve the power conversion efficiency.

FIG. 1 is a circuit configuration diagram illustrating a switching power supply circuit according to an embodiment of the present invention. 2 is a time chart illustrating an operation of the switching power supply circuit of FIG. 1. FIG. 3 is a characteristic diagram showing a relationship between a DC input voltage and power conversion efficiency according to the first embodiment. FIG. 9 is a circuit diagram illustrating an example of a conventional switching power supply circuit. 9 is a time chart illustrating an operation of a conventional switching power supply circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit configuration diagram of a switching power supply device according to the present invention. 4, a step-down chopper that outputs energy stored in a reactor L through a diode D1 when the FET Q1 is on is the same as in FIG. 4, and the same or equivalent components are denoted by the same reference numerals. It is. The difference from FIG. 4 lies in the configuration in which a drive circuit 10 for driving the switching power supply is provided. The drive circuit 10 includes a quick-off control circuit 3, a negative voltage generation circuit 5, and a protection circuit 7, and is controlled by the control unit 20.

  The quick-off control circuit 3 includes a bipolar transistor Q2, which is a switching element for FET operation, connected between a source (DC input side) S and a gate (control pole) G of the FET Q1, and an emitter (DC input) of the transistor Q2. Side) A parallel circuit of a diode D2 and a resistor R2 connected between E and a base (control pole) B, and a capacitor (A) connected between the base B of the transistor Q2 and the drain (output side) D of the FET Q1. A first capacitor C4 and a resistor (first resistor) R4 are provided, and the FET Q1 is quickly turned off by turning on the transistor Q2.

  The FET Q1 is, for example, a P-channel MOS-FET, and the bipolar transistor Q2 is, for example, a PNP transistor. The diode D2, the resistor R2, the capacitor C4 and the resistor R4 form a snubber circuit. This snubber circuit is formed of an element that does not increase energy loss while absorbing noise. Further, when the input voltage Vi is high, the voltage charged in the capacitor C4 reverse-biases the emitter-base of the transistor Q2 when the FET Q1 is turned on. In this case, the rating of the emitter-base voltage may be exceeded. There is. For this reason, the diode D2 prevents a reverse bias exceeding the rating from being applied between the base and the emitter of the transistor Q2 due to the forward voltage drop.

  The negative voltage generation circuit 5 applies a negative voltage to the gate (control electrode) G of the FET Q1 to increase the switching-off speed of the FET Q1 when the transistor Q2 that rapidly switches off the FET Q1 is turned on. Is shifted to the negative side to include a negative voltage, that is, the operation is performed so as to be pulled to the negative side to increase the switch-off switching speed. The negative voltage generation circuit 6 includes, for example, a Zener diode ZD1 and a capacitor C5 connected in parallel, and is disposed between a control unit 20 that outputs a control signal a via a resistor R1 and a gate G of the FET Q1. I have.

  The protection circuit 7 operates the negative voltage generation circuit 5 so as not to be affected by the parasitic diode of the FET Q1, and applies a voltage including the negative voltage to the gate G of the FET Q1. The protection circuit 7 includes, for example, a diode D3, a resistor (second resistor) R3 and a capacitor (second capacitor) C3 connected in parallel, which are connected in series, and has a gate G and a source (DC input) of the FET Q1. Side) S.

  The resistor R3 is connected between the source S and the gate G of the FET Q1 such that when the transistor Q1 is turned on, the capacitor C5 of the negative voltage generation circuit 5 is charged up to the Zener voltage of the Zener diode ZD1.

  Next, the operation of the switching power supply device of FIG. 1 will be described with reference to FIG.

  The control unit 20 in FIG. 1 detects the DC output voltage Vo and outputs a control signal a in which the pulse width of a duty pulse generated in a constant cycle changes according to the fluctuation of the DC output voltage Vo. The FET Q1 receives the control signal a at the gate G and repeats on / off to change the drain-source potential VDS to a rectangular shape (square wave) as shown in FIG.

  The MOS-FET Q1 in FIG. 1 is a P-channel and is turned on when the control signal a is at a low level, and during a period α in FIG. The drain current ID of the ON current flows to the (output side) during the period α in FIG. 2B. When the transistor Q1 is turned on, the gate-source potential VGS in FIG. 2C also indicates the on-voltage (the lower side is positive in the figure). At this time, the capacitor C5 is also charged in the direction of VC5.

  When the control signal a rises to a high level and the FET Q1 starts to turn off and turns off, the potential VDS in FIG. 2A becomes the input voltage Vi of the off voltage, and the drain current ID in FIG. 0A, and the output voltage VD of the FET Q1 also shows the off voltage of 0V.

  When the FET Q1 starts to turn off, the voltage applied to the capacitor C4 of the quick-off circuit 3 is still 0V. Subsequently, at the moment when the potential of the voltage on the drain side (output side) of the FET Q1 drops by a slight V value from the potential on the source side (DC input side), a current flows through the capacitor C4 and is charged. This charging current flows through the base B and the resistor R2 of the transistor Q2, turning on the transistor Q2. At this time, the charging current is suppressed to an appropriate level by the resistor R4.

  Further, since the diode D2, the resistor R2, the capacitor C4, and the resistor R4 of the quick-off circuit 3 form a snubber circuit, the withstand voltage of VDS applied between the drain and source of the FET Q1 can be reduced.

  When the transistor Q2 is turned on, the potential VGS of the FET Q1 is reverse-biased by the voltage VC5 applied to the capacitor C5, so that the transistor Q2 is rapidly turned off in a period β to start turning off in FIG. Is rapidly discharged, and is pulled further to the negative side than the OFF voltage of 0 V, so that the potential VGS becomes a negative voltage of -tV. Thus, when the FET Q1 starts to be turned off, the gate voltage of the FET Q1 is pulled to the negative side, so that the switching speed at which the FET Q1 is turned off can be increased.

  The protection circuit 7 operates the negative voltage generation circuit 5 sufficiently without being affected by the parasitic diode of the FET Q1, and the gate voltage of the FET Q1 can be reliably pulled to the negative side.

  After the transistor Q2 starts to turn on, the voltage applied to the capacitor C4 increases when the transistor Q2 turns on, so that the transistor Q2 is gradually turned off. When the FET Q1 is turned on, the charge stored in the capacitor C4 is discharged through a loop of the diode D2 and the resistor R2, the FET Q1, the resistor R4, and the capacitor C4, and is prepared for the next charge.

  Conventionally, as described above, switching loss occurs because the drain-source voltage VDS of the FET Q1 and the drain current ID overlap without zero crossing. On the other hand, according to the present invention, when the FET Q1 starts to be turned off by the quick-off control circuit 3, at the moment when the potential on the drain side (output side) is slightly lower than the potential on the source side (DC input side). A charging current instantaneously flows through the capacitor C4, turning on the transistor Q2, reverse-biasing the FET Q1, and rapidly switching off the FET Q1, thereby increasing the switching speed. Further, the negative voltage generation circuit 5 pulls the base voltage of the FET Q1 to a negative voltage, thereby further increasing the switching speed. As a result, at the moment when the FET Q1 starts to turn off and the drain-source voltage VDS starts to increase (the potential on the output side starts to decrease), the drain current ID decreases to zero level, and FIGS. 2 (a) and 2 (b). , Both ID and VDS change vertically and cross zero. Therefore, switching loss can be reduced. Then, the protection circuit 7 can reliably operate the negative voltage generation circuit 5 without being affected by the parasitic diode of the FET Q1.

  Thus, in the present invention, when the FET Q1 starts to be turned off by the rapid-off control circuit 3, the negative voltage generating circuit 5, and the protection circuit 7, the drain-source voltage VDS of the FET Q1 and the drain current ID overlap. Is extremely small, so that the switching loss is as small as possible.

  As is clear from the characteristic diagram of the power conversion efficiency (vertical axis) with respect to the DC input voltage (horizontal axis) in FIG. Therefore, the power conversion efficiency is considerably high as a whole.

  Thus, according to the present invention, the charging current flows from the DC input side through the control electrode of the transistor Q2 when the FET Q1 starts to be turned off by the drive of the drive circuit and the output side potential slightly decreases with respect to the DC input side potential. The capacitor is charged and the transistor Q1 turns on momentarily, rapidly switching off the FET Q1. At the same time, when the transistor Q2 is turned on, the voltage of the control electrode of the FET Q1 is shifted to the negative side to include the negative voltage, that is, the transistor Q2 is operated to be pulled to the negative side to increase the switching speed of the switch-off. Therefore, since the FET Q1 is immediately switched off, the switching speed of the switch-off can be increased as much as possible to reduce the switching loss and to improve the power conversion efficiency.

  Further, by increasing the time constant of the resistor R3 and the capacitor C3 of the protection circuit 7, the rise of the gate voltage of the FET Q1 immediately after the start of the switching power supply device can be made gentler. Then, the transition of the FET Q1 to the ON state becomes gradual, the LC resonance caused by the junction capacitance of the parasitic diode and the L component of the circuit wire can be suppressed, noise can be suppressed, and malfunction can be prevented.

  If the time constant of the resistor R3 and the capacitor C3 is large and the rising of the gate becomes slow even during the normal operation, the FET Q1 does not turn on sufficiently and the on-resistance increases, so that the capacitor C3 is discharged by the diode D3 during the normal operation. I am holding it down. That is, the protection circuit 7 operates so as to gradually raise the gate voltage of the FET Q1 only at the time of startup. During normal operation, the circuit operates as a circuit including a diode D3 and a resistor R3 connected in series.

  In this embodiment, a MOS-FET is used for the FET, but an IGBT element having a part of the FET may be used.

  As described above, the preferred embodiment has been described with reference to the drawings. However, those skilled in the art will easily envisage various changes and modifications within the obvious scope by referring to the present specification. Accordingly, such changes and modifications are to be construed as being within the scope of the invention as defined by the appended claims.

3: Quick off control circuit 5: Negative voltage generation circuit 7: Protection circuit 10: Drive circuit 20: Control unit Q1: FET
Q2: FET operation switching element C3: second capacitor.
C4: first capacitor.
R3: second resistor R4: first resistor

Claims (4)

A switching power supply device that converts input DC power of DC voltage into DC power of a predetermined output voltage by controlling on / off of a FET by driving a drive circuit, and outputs the DC power.
The drive circuit includes:
A switching element for FET operation connected between the DC input side of the FET and the control electrode; a first capacitor connected between the control electrode of the switching element for FET operation and the output side of the FET; When the FET starts to be turned off, the charging current of the first capacitor is caused to flow through the control electrode of the switching element for FET operation in response to the voltage drop on the output side, whereby the switching for FET operation is performed. a rapid off control circuit for rapidly switching off the FET turns on the device, during on of the FET operating switching element, rapidly is switched off by the rapid off control circuit by applying a negative voltage to the control electrode of the FET was to further speed the switching off of the FET, the negative voltage operable to include a negative voltage a voltage of the control electrode is shifted to the negative side of the FET And forming circuit,
The negative voltage generation circuit is disposed between the negative voltage generation circuit and the control electrode of the FET, operates the negative voltage generation circuit so as not to be affected by the parasitic diode of the FET, and applies a voltage including the negative voltage to the control electrode of the FET. Protection circuit
A switching power supply circuit. In claim 1,
The FET is a MOS-FET, and the protection circuit is provided between a gate and a source of the MOS-FET, and includes a diode, a second resistor and a second capacitor connected in parallel, connected in series. And a switching power supply circuit in which the time constants of the second resistor and the second capacitor of the protection circuit are increased so as to moderate the rise of the gate voltage of the MOS-FET. In claim 1,
The switching power supply circuit, wherein the quick-off control circuit has a snubber circuit including the first capacitor and a first resistor. In claim 1,
A switching power supply circuit, wherein the switching power supply circuit forms a step-down chopper.

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