JP2003282790A - Semiconductor device, its manufacturing method, circuit board, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is highly reliable, its manufacturing method, a circuit board, and an electronic apparatus. <P>SOLUTION: The semiconductor device is equipped with a semiconductor substrate 10 provided with an integrated circuit 12 and an electrode 14 electrically connected to the integrated circuit 12, a resin layer 18 which is formed on the surface of the semiconductor substrate 10 on which the electrode 14 is formed so as to stay away from the electrode 14, wiring 22 which is formed of a material more corrosion-resistant than the electrode 14 as covering the electrode 14, and an external terminal 24 electrically connected to the wiring 22. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, a circuit board, and an electronic device.

[0002]

BACKGROUND ART As a package of a semiconductor device, a CSP
The diffusion rate of (chip scale / size package) is increasing. Further, a technique for manufacturing a package at a wafer level (wafer level package) has been developed. The package (for example, wafer level CSP) manufactured by this method has a structure different from that of the conventional package because the external dimensions are the semiconductor chip size, but the reliability is equal to or higher than that of the conventional package. Is required.

An object of the present invention is to provide a highly reliable semiconductor device and its manufacturing method, a circuit board, and an electronic device.

[0004]

(1) In a semiconductor device according to the present invention, a semiconductor substrate having an integrated circuit and an electrode electrically connected to the integrated circuit, and the electrode of the semiconductor substrate are formed. A resin layer formed to avoid the electrodes, a wiring formed to cover the electrodes and formed of a material that is less corrosive than the electrodes, and an external terminal electrically connected to the wiring. And.

According to the present invention, since the electrodes are covered with the wiring that is less corrosive than the electrodes, it is possible to prevent the electrodes from corroding and prevent electrical defects.

(2) A semiconductor device according to the present invention comprises: a semiconductor substrate having an integrated circuit and a plurality of electrodes electrically connected to the integrated circuit; and a surface of the semiconductor substrate on which the electrodes are formed, A material having a resin layer formed avoiding the electrodes and an external terminal, wherein at least one of the electrodes is not electrically connected to the external terminal and is less likely to corrode than the electrode. The electrodes except the at least one electrode covered with the metal film formed in 1. are electrically connected to the external terminals by wiring.

According to the present invention, since at least one electrode that is not electrically connected to the external terminal is covered with the metal film that is less corroded than the electrode, corrosion of the electrode is prevented and electrical failure is prevented. can do.

(3) A semiconductor device according to the present invention includes a semiconductor substrate having an integrated circuit, an electrode electrically connected to the integrated circuit, and a mark made of the same material as the electrode, On the surface of the semiconductor substrate on which the electrodes are formed,
A resin layer formed avoiding the electrodes, a wiring electrically connected to the electrodes, a metal film formed to cover the mark with a material that is less corrosive than the electrodes, and an electrical connection to the wiring. And an external terminal connected to.

According to the present invention, since the mark formed of the same material as the electrode is covered with the metal film which is less corroded than the electrode, it is possible to prevent the mark from being corroded.

(4) A semiconductor device according to the present invention has a semiconductor substrate having an integrated circuit and an electrode electrically connected to the integrated circuit, and the electrode on the surface of the semiconductor substrate on which the electrode is formed. A resin layer that is formed to avoid it, and has a planar shape with an upper surface having no corners, a wiring that extends from the electrode to the upper surface of the resin layer, and an external that is electrically connected to the wiring. And a terminal.

According to the present invention, since the upper surface of the resin layer has a flat shape without corners, even if the resin layer contracts, no protrusion is formed at the end portion of the upper surface. On the other hand, if the upper surface has a planar shape with corners, when the resin layer contracts, protrusions are formed near the corners of the upper surface.

(5) In a semiconductor device according to the present invention, a semiconductor substrate having an integrated circuit and an electrode electrically connected to the integrated circuit, and the electrode on the surface of the semiconductor substrate on which the electrode is formed are provided. A resin layer formed avoiding the above, and a first portion which is electrically connected to the electrode and which is formed at a boundary between a side surface and an upper surface of the resin layer, and which is connected to the first portion and is connected to the first portion. A second portion formed on the upper surface of the resin layer, the first portion having a width wider than that of the second portion, and electrically connected to the wiring. And an external terminal.

According to the present invention, the first portion is formed at the boundary between the side surface and the upper surface of the resin layer and is more easily broken than the other portions, but is formed to be wider than the second portion. Since it is, the disconnection can be suppressed.

(6) A semiconductor device according to the present invention is a semiconductor substrate having an integrated circuit and an electrode electrically connected to the integrated circuit, and the electrode on the surface of the semiconductor substrate on which the electrode is formed. Formed on the semiconductor substrate, and a resin layer formed to avoid the above, a wiring electrically connected to the electrode, an external terminal electrically connected to the wiring, and covering at least a part of the wiring. A resist layer, and the bottom surface of the resist layer has a planar shape without corners.

According to the present invention, since the bottom surface of the resist layer has no corners, peeling is less likely to occur.

(7) A semiconductor device according to the present invention is a semiconductor substrate having an integrated circuit and an electrode electrically connected to the integrated circuit, and the electrode on the surface of the semiconductor substrate on which the electrode is formed. And a plurality of external terminals, the resin layer being formed so as to avoid
One external terminal is provided without being electrically connected to the electrode, and the external terminals except the at least one external terminal are electrically connected to the electrode by wiring.

According to the present invention, since the number of external terminals is increased, the stress generated in the external terminals can be dispersed, and the reliability after mounting on the circuit board is improved.

(8) In this semiconductor device, the resin layer may be formed between the external terminal and the semiconductor substrate.

(9) In this semiconductor device, the semiconductor substrate may be a semiconductor chip.

(10) In this semiconductor device, the semiconductor substrate may be a semiconductor wafer and may have a plurality of the integrated circuits.

(11) A circuit board according to the present invention has the above semiconductor device mounted thereon.

(12) An electronic device according to the present invention has the above semiconductor device.

(13) In the method of manufacturing a semiconductor device according to the present invention, the surface of the semiconductor substrate on which the electrodes electrically connected to the integrated circuit are formed is a flat surface having no corners, avoiding the electrodes. Forming a resin layer in a shape, forming wiring from the electrode to the upper surface of the resin layer, and electrically connecting an external terminal to the wiring.

According to the present invention, since the resin layer is formed so that its upper surface has a flat shape without corners, even if the resin layer contracts, no protrusion is formed at the end portion of the upper surface. On the other hand, if the upper surface has a planar shape with corners, when the resin layer contracts, protrusions are formed near the corners of the upper surface.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a plan view of the semiconductor device according to the first embodiment of the present invention in which a part (resist layer 30 and coating layer 32) is removed, and FIG. It is a partially enlarged view.

The semiconductor device has a semiconductor substrate 10.
The semiconductor substrate 10 may be a semiconductor chip or a semiconductor wafer. One or more integrated circuits 12 are formed on the semiconductor substrate 10. One integrated circuit 12 is formed on the semiconductor chip, and a plurality of integrated circuits 12 are formed on the semiconductor wafer. A plurality of electrodes (for example, pads) 14 electrically connected to one integrated circuit 12 are formed on the semiconductor substrate 10. The electrode 14 is formed of, for example, Al. A passivation film 16 is formed on the surface of the semiconductor substrate 10 (the surface on which the electrodes 14 are formed) while avoiding the electrodes 14.
The passivation film 16 is made of SiN, SiO ₂ , MgO.
It is formed from etc.

At least one resin layer 18 is formed on the surface of the semiconductor substrate 10 on which the electrodes 14 are formed (for example, on the passivation film 16). Resin layer 18
Are formed so as to avoid the electrodes 14. The resin layer 18 is
The side surface may be inclined so that the opposite surface (bottom surface) is larger than the upper surface 20. The resin layer 18 may have a stress relaxation function. The resin layer 18 is made of polyimide resin, silicone-modified polyimide resin, epoxy resin, silicone-modified epoxy resin, benzocyclobutene (BC).
B; benzocyclobutene), polybenzoxazole (P
It can be formed of a resin such as BO; polybenzoxazole). The resin layer 18 may be formed between the semiconductor substrate 10 and the external terminal 24.

As shown in FIG. 2, the upper surface 20 of the resin layer 18 is formed.
Has a planar shape without corners (for example, a shape in which the corners of a quadrangle are rounded). Therefore, even if the resin layer 18 contracts, no protrusion is formed at the end of the upper surface 20 thereof. When the resin layer 18 is formed in a planar shape having an upper surface with a corner, when the resin layer 18 contracts, the resin is concentrated near the corner of the upper surface to form a protrusion.

The semiconductor device has one or more wirings 22. Each wiring 22 is formed of one layer or a plurality of layers. The wiring 22 is electrically connected to one or one group of electrodes 14. In the present embodiment, the wiring 22 is
It covers one or a group of electrodes 14. Wiring 22
May cover the entire exposed surface of the electrode 14 (exposed surface from the passivation film 16). The wiring 22 may be formed of a material (for example, Cu, TiW, Cr) that is more resistant to corrosion than the material (for example, Al) forming the electrode 14. When the wiring 22 is formed of a plurality of layers, at least one layer may be formed of a material (for example, Cu, TiW, Cr) that is more resistant to corrosion than the material (for example, Al) forming the electrode 14. By doing so, it is possible to prevent corrosion of the electrode 14 and prevent electrical failure.

The wiring 22 is formed so as to extend from the electrode 14 to the upper surface 20 of the resin layer 18. The wiring 22 is also formed on the inclined side surface of the resin layer 18. As described above, the upper surface 20 has a planar shape without corners, and the resin layer 1
Since no protrusion is formed on the end of the upper surface 20 of the wiring 8, the wiring 22 passing through the end of the upper surface 20 of the resin layer 18 has a smooth shape and its disconnection is prevented. Further, when plating is performed when forming the wiring 22, it is possible that the projection is plated and the wiring 22 is short-circuited due to poor adhesion of the resist when the projection is formed on the resin layer 18, but This is prevented in this embodiment.

The wiring 22 is formed on the upper surface 20 of the resin layer 18,
It may be formed straight or may be bent. By forming the bent portion 23 of the wiring 22 into a round shape so as not to have a corner, disconnection is prevented.

The semiconductor device has a plurality of external terminals 24. The external terminal 24 is electrically connected to the wiring 22. The external terminal 24 may be formed on the land 26 of the wiring 22. The external terminal 24 is a metal (for example, an alloy) having conductivity and is for melting (for example, solder) for electrical connection. External terminal 24
Is a soft solder or a hard solder
Any of the above may be used. The external terminal 24 may have a spherical shape, and may be, for example, a solder ball.

At least one electrode (for example, an electrode for inspection) 14 is covered with the metal film 28 without being electrically connected to the external terminal 24. The metal film 28 is the electrode 1
It may be formed of a material (for example, Cu, TiW, or Cr) that is less corrosive than the material (for example, Al) that constitutes No. 4.
By doing so, it is possible to prevent corrosion of the electrode 14 and prevent electrical failure. The metal film 28 may be formed of the same material as the wiring 22. The material forming the metal film 28 (for example, Cu, TiW, Cr) may have higher adhesion to the resist layer 30 than the material forming the electrode 14 (for example, Al).

A resist layer 30 is formed on the semiconductor substrate 10. The resist layer 30 covers at least a part of the wiring 22. By covering all of the wiring 22 except the portion where the external terminals 24 are provided with the resist layer 30, oxidation and corrosion of the wiring 22 can be prevented and electrical failure can be prevented. The resist layer 30 may be formed except at least the central portion of the land 26 of the wiring 22. The resist layer 30 may cover the peripheral portion of the land 26. Further, the resist layer 30 may cover all the lines 27 drawn out from the land 26 and may cover the connection portion 29 between the line 27 and the land 26. By doing so, it is possible to prevent disconnection of the connecting portion 29 between the line 27 and the land 26. The connection portion 29 between the line 27 and the land 26 may be formed to have a width wider than that of the line 27.

The bottom surface of the resist layer 30 (for example, the contact surface with the semiconductor substrate 10) may have a shape without corners. By doing so, even if the semiconductor substrate 10 is affected by chipping during dicing or stress is generated, the resist layer 30 is unlikely to be peeled from the semiconductor substrate 10. A coating layer 32 may be formed on the resist layer 30. The coating layer 32 is a root portion (lower end portion) of the external terminal 24.
Also covers. The coating layer 32 and the portion formed on the resist layer 30 and the external terminal 24 are raised from this portion.
And a portion that covers the root part of the. At least the root portion of the external terminal 24 is reinforced by the coating layer 32. After the semiconductor device is mounted on the circuit board, the stress concentration on the external terminals 24 can be dispersed by the coating layer 32.

When the semiconductor substrate 10 is a semiconductor chip, the semiconductor device can be classified as CSP because the package size of the semiconductor device is almost equal to that of the semiconductor chip, or it can be said that it is a flip chip having a stress relaxation function. it can.

The semiconductor device according to the present embodiment is configured as described above, and its manufacturing method will be described below. In the present embodiment, the integrated circuit 12 of the semiconductor substrate 10 is
On the surface on which the electrode 14 electrically connected to is formed, the resin layer 18 is formed so as to avoid the electrode 14 so that the upper surface 20 has a planar shape without corners. Electrode 14 to resin layer 18
The wiring 22 is formed so as to reach the upper surface 20 of the. The external terminal 24 is formed by being electrically connected to the wiring 22. When the semiconductor substrate 10 is a semiconductor wafer, as shown in FIG. 4, the semiconductor substrate 10 is cut into individual integrated circuits 12 by, for example, a blade 40. A plurality of semiconductor devices are obtained by cutting the semiconductor substrate 10. According to this, packaging is performed in wafer units.

In this embodiment, the resin layer 18 is formed so that the upper surface 20 thereof has a planar shape without corners. If the upper surface 20 has a planar shape with corners, when the resin layer 18 contracts, protrusions are formed near the corners of the upper surface 20,
In this embodiment, since the upper surface 20 does not have a corner, even if the resin layer 18 contracts, no protrusion is formed at the end of the upper surface 20. In other respects, the description of the semiconductor device described above corresponds to the method for manufacturing a semiconductor device according to the present embodiment.

(Second Embodiment) FIG. 5 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
FIG. 6 is a plan view in which a part (resist layer 130) of the semiconductor device according to the second embodiment of the present invention is removed,
FIG. 7 is a partially enlarged view of the portion indicated by the alternate long and short dash line in FIG.

The semiconductor device has a semiconductor substrate 110. The semiconductor substrate 110 may be a semiconductor chip or a semiconductor wafer. One or more integrated circuits 112 are formed on the semiconductor substrate 110.
One integrated circuit 112 is formed on the semiconductor chip,
A plurality of integrated circuits 112 are formed on the semiconductor wafer. The semiconductor substrate 110 has a plurality of electrodes (for example, pads) 114 electrically connected to one integrated circuit 112.
Are formed. The electrode 114 is made of, for example, Al. A passivation film 116 is formed on the surface of the semiconductor substrate 110 (the surface on which the electrodes 114 are formed), avoiding the electrodes 114. Passivation film 11
6 is made of SiN, SiO ₂ , MgO or the like.

On the semiconductor substrate 110, for example, electrodes 114 are provided.
A mark 140 (see FIG. 7) is formed on the surface where the mark is formed. The mark 140 is exposed from the passivation film 116 similarly to the electrode 114. Mark 140
May or may not be electrically connected to the integrated circuit 112. The mark 140 indicates the electrode 11
It may be formed of the same material as 4 (for example, Al). The mark 140 may be an alignment mark (mark for positioning) of the semiconductor substrate 110.

At least one resin layer 118 is formed on the surface of the semiconductor substrate 110 on which the electrodes 114 are formed (for example, on the passivation film 116). The resin layer 118 is formed so as to avoid the electrode 114. The side surface 121 of the resin layer 118 may be inclined so that the opposite surface (bottom surface) thereof is larger than the upper surface 120.
The resin layer 118 may have a stress relaxation function. The resin layer 118 can be formed using a resin such as a polyimide resin, a silicone-modified polyimide resin, an epoxy resin, a silicone-modified epoxy resin, benzocyclobutene (BCB), or polybenzoxazole (PBO). The resin layer 118 may be formed between the semiconductor substrate 110 and the external terminal 124.

As shown in FIG. 7, the upper surface 1 of the resin layer 118
20 has a planar shape without corners (for example, a shape in which the corners of a quadrangle are rounded). Therefore, the resin layer 11
Even if 8 shrinks (for example, shrinks upon curing), no protrusion is formed at the end of the upper surface 120. When the resin layer 118 is formed in a planar shape having an upper surface with a corner, when the resin layer 118 contracts (for example, shrinks by curing), the resin concentrates near the corner of the upper surface to form a protrusion.

The semiconductor device has one or more wirings 122.
Have. Each wiring 122 is formed of one layer or a plurality of layers. The wiring 122 includes one or a group of electrodes 11
4 is electrically connected. In this embodiment mode, the wiring 122 covers one or a group of electrodes 114. The wiring 122 may cover the entire exposed surface of the electrode 114 (exposed surface from the passivation film 116). The wiring 122 is made of a material (for example, Cu or Ti) that is more resistant to corrosion than the material (for example, Al) forming the electrode 114.
W, Cr) may be used. When the wiring 122 is formed of a plurality of layers, at least one layer may be formed of a material (for example, Cu, TiW, Cr) that is more resistant to corrosion than the material (for example, Al) forming the electrode 114. By doing so, it is possible to prevent corrosion of the electrode 114 and prevent electrical failure.

The wiring 122 is formed from the electrode 114 to the resin layer 11
8 is formed so as to reach the upper surface 120. Wiring 12
2 is also formed on the inclined side surface 121 of the resin layer 118. As described above, since the upper surface 120 has a flat shape without corners and no protrusion is formed at the end of the upper surface 120 of the resin layer 118, the wiring 122 passing through the end of the upper surface 120 of the resin layer 118 has a smooth shape. The disconnection is prevented. Further, when plating is performed when forming the wiring 122, if the protrusion is formed on the resin layer 118, the adhesion of the resist is bad.
It is possible that 2 is short-circuited, but this is prevented in the present embodiment.

The wiring 122 is the upper surface 120 of the resin layer 118.
Then, it may be formed straight or may be bent. By forming the bent portion 123 of the wiring 122 into a round shape so as not to have a corner, disconnection is prevented.

As shown in FIG. 7, the wiring 122 has a first portion 150 formed at the boundary between the side surface 121 and the upper surface 120 of the resin layer 118, and the upper surface 120 of the resin layer connected to the first portion 150. A second portion 152 formed on the. The first portion 150 has a width wider than that of the second portion 152. According to this, the first part 150
Even if it is formed at the boundary between the side surface 121 and the upper surface 120 of the resin layer 118 and is more easily broken than the other portions, it is formed with a width wider than that of the second portion 152, so that the disconnection is suppressed.

The semiconductor device has a plurality of external terminals 124, 1
25. The external terminal 124 is electrically connected to the wiring 122. The external terminal 124 may be formed on the land 126 of the wiring 122. External terminal 124
Is a conductive metal (for example, an alloy) for melting and establishing an electrical connection (for example, solder)
Is. The external terminals 124 may be formed of either soft solder or hard solder. The external terminal 124 may have a spherical shape, and may be, for example, a solder ball.

At least one external terminal 125 is provided without being electrically connected to the electrode 114. For example, the external terminal 125 may be provided on the land that is not electrically connected to the electrode 114. The other contents of the external terminal 125 are the same as those of the external terminal 124. The arrangement of the external terminals 124 and 125 is a full grid.
d) According to the present embodiment, the external terminal 1
Since the external terminals 125 are added to 24, the number thereof is increased, the stress generated in the external terminals 124 and 125 can be dispersed, and the reliability after being mounted on the circuit board is improved.

At least one electrode (for example, a testing electrode) 114 is covered with a metal film 128 without being electrically connected to the external terminal 124. Metal film 128
May be formed of a material (for example, Cu, TiW, Cr) that is more resistant to corrosion than the material (for example, Al) forming the electrode 114. By doing so, it is possible to prevent corrosion of the electrode 114 and prevent electrical failure. Metal film 128
May be formed of the same material as the wiring 122. Metal film 1
Material constituting 28 (eg Cu, TiW, Cr)
May have higher adhesion to the resist layer 130 than the material (for example, Al) forming the electrode 114.

The mark 140 is covered with the metal film 142 without being electrically connected to the external terminal 124.
The metal film 142 is made of a material (for example, A
l) less corrosive material (eg Cu, TiW,
It may be formed of Cr). By doing this, mark 14
It is possible to prevent 0 corrosion and prevent electrical failure. The metal film 142 may be formed of the same material as the wiring 122. The material forming the metal film 142 (for example, Cu,
TiW, Cr) may have higher adhesion to the resist layer 130 than the material (eg, Al) forming the mark 140.

A resist layer 130 is formed on the semiconductor substrate 110. The resist layer 130 covers at least a part of the wiring 122. External terminal 1 of wiring 122
The resist layer 1 is entirely provided except for the portion where 24 is provided.
Covering with 30 prevents the wiring 122 from being oxidized and corroded,
It is possible to prevent electrical failure. Resist layer 130
May be formed except for at least the central portion of the land 126 of the wiring 122. The resist layer 130 may cover the peripheral portion of the land 126. The resist layer 130 is formed on the line 12 drawn from the land 126.
7 may be entirely covered, and the connection portion 129 between the line 127 and the land 126 may be covered. By doing this, line 1
It is possible to prevent disconnection of the connecting portion 129 between the 27 and the land 126. The connecting portion 129 between the line 127 and the land 126 may be formed to have a width wider than that of the line 127.

The bottom surface of the resist layer 130 (for example, the contact surface with the semiconductor substrate 110) may have a shape without corners. This makes it difficult for the resist layer 130 to be peeled from the semiconductor substrate 110 even if the semiconductor substrate 110 is affected by chipping during dicing or stress is generated. A coating layer (not shown) may be formed on the resist layer 130. The coating layer may also cover the root portion (lower end portion) of the external terminal 124. The coating layer may have a portion formed on the resist layer 130 and a portion that rises from this portion and covers the root portion of the external terminal 124. At least the root portion of the external terminal 124 may be reinforced by the coating layer. After the semiconductor device is mounted on the circuit board, the stress concentration on the external terminals 124 can be dispersed by the coating layer.

When the semiconductor substrate 110 is a semiconductor chip, the package size of the semiconductor device is almost the same as that of the semiconductor chip, so that the semiconductor device can be classified as a CSP or a flip chip having a stress relaxation function. it can.

The semiconductor device according to the present embodiment is configured as described above, and its manufacturing method will be described below. In the present embodiment, the integrated circuit 1 on the semiconductor substrate 110 is
The resin layer 118 is formed on the surface on which the electrode 114 electrically connected to the electrode 12 is formed so as to avoid the electrode 114 so that the upper surface 120 has a planar shape without corners. Electrode 11
4 from the upper surface 120 of the resin layer 118 to the wiring 12
Form 2. The external terminal 124 is formed by being electrically connected to the wiring 122. When the semiconductor substrate 110 is a semiconductor wafer, the semiconductor substrate 110 is cut for each integrated circuit 112 by, for example, a blade. Semiconductor substrate 11
By cutting 0, a plurality of semiconductor devices are obtained. According to this, packaging is performed in wafer units.

In this embodiment mode, the resin layer 118 is formed so that the upper surface 120 thereof has a planar shape without corners. If the upper surface 120 has a planar shape with corners, when the resin layer 118 contracts (for example, cure contracts), the upper surface 120
Although the protrusions are formed in the vicinity of the corners in the present embodiment, since the upper surface 120 does not have the corners in this embodiment, the protrusions are not formed at the end portions of the upper surface 120 even when the resin layer 118 contracts (for example, shrinks upon curing). In other respects, the description of the semiconductor device described above corresponds to the method for manufacturing a semiconductor device according to the present embodiment. Further, the contents described in the second embodiment can be applied to the first embodiment.

FIG. 8 shows a circuit board 1000 on which the semiconductor device 1 according to the embodiment of the present invention is mounted. As an electronic device having the semiconductor device according to the embodiment of the present invention, FIG. 9 shows a notebook personal computer 2000, and FIG. 10 shows a mobile phone 3000.

The present invention is not limited to the above-mentioned embodiment, but various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations having the same function, method and result, or configurations having the same purpose and result). Further, the invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Further, the present invention includes a configuration having the same effects as the configurations described in the embodiments or a configuration capable of achieving the same object. Further, the invention includes configurations in which known techniques are added to the configurations described in the embodiments.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view in which a part of the semiconductor device according to the first embodiment of the present invention is excluded.

FIG. 3 is a partially enlarged view of the semiconductor device shown in FIG.

FIG. 4 is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 5 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a plan view showing a semiconductor device according to a second embodiment of the present invention with a part thereof removed.

7 is a partially enlarged view of the semiconductor device shown in FIG.

FIG. 8 is a diagram showing a circuit board on which the semiconductor device according to the present embodiment is mounted.

9A and 9B are diagrams illustrating an electronic device including the semiconductor device according to this embodiment.

FIG. 10 is a diagram showing an electronic device including the semiconductor device according to the present embodiment.

[Explanation of symbols]

10 Semiconductor substrate 12 integrated circuits 14 electrodes 18 Resin layer 20 upper surface 22 wiring 24 external terminals 28 Metal film 30 resist layer 110 Semiconductor substrate 112 integrated circuits 114 electrodes 118 resin layer 120 top 121 side 122 wiring 124 External terminal 125 external terminals 128 metal film 130 resist layer 140 mark 150 First Part 152 Second part

Claims (13)

[Claims] 1. A semiconductor substrate having an integrated circuit and an electrode electrically connected to the integrated circuit, and a resin layer formed on the surface of the semiconductor substrate on which the electrode is formed while avoiding the electrode. A semiconductor device comprising: a wiring formed to cover the electrode and formed of a material that is more resistant to corrosion than the electrode; and an external terminal electrically connected to the wiring. 2. A semiconductor substrate having an integrated circuit and a plurality of electrodes electrically connected to the integrated circuit, and a resin formed on the surface of the semiconductor substrate on which the electrodes are formed while avoiding the electrodes. A layer and an external terminal, and at least one of the electrodes is covered with a metal film formed of a material that is not electrically connected to the external terminal and is less corroded than the electrode. A semiconductor device in which electrodes other than the at least one electrode are electrically connected to the external terminals by wiring. 3. A semiconductor substrate having an integrated circuit, an electrode electrically connected to the integrated circuit, and a mark formed of the same material as the electrode, and the electrode of the semiconductor substrate is formed. A resin layer formed on the surface to avoid the electrode, a wiring electrically connected to the electrode, a metal film formed to cover the mark with a material that is more resistant to corrosion than the electrode, and the wiring A semiconductor device having an external terminal electrically connected to the. 4. A semiconductor substrate having an integrated circuit and an electrode electrically connected to the integrated circuit; a surface of the semiconductor substrate on which the electrode is formed, avoiding the electrode, and an upper surface having a corner. A semiconductor device comprising: a planar resin layer that does not have a wiring; wiring formed from the electrode to the upper surface of the resin layer; and an external terminal electrically connected to the wiring. 5. A semiconductor substrate having an integrated circuit and an electrode electrically connected to the integrated circuit, and a resin layer formed on the surface of the semiconductor substrate on which the electrode is formed so as to avoid the electrode. A first portion electrically connected to the electrode and formed at a boundary between a side surface and an upper surface of the resin layer, and formed on the upper surface of the resin layer connected to the first portion. Second
And a wiring formed by the first portion having a width wider than that of the second portion, and an external terminal electrically connected to the wiring. 6. A semiconductor substrate having an integrated circuit and an electrode electrically connected to the integrated circuit, and a resin layer formed on the surface of the semiconductor substrate on which the electrode is formed so as to avoid the electrode. A wiring electrically connected to the electrode, an external terminal electrically connected to the wiring, and a resist layer formed on the semiconductor substrate and covering at least a part of the wiring, A semiconductor device in which the bottom surface of the resist layer has a flat shape without corners. 7. A semiconductor substrate having an integrated circuit and an electrode electrically connected to the integrated circuit, and a resin layer formed on the surface of the semiconductor substrate on which the electrode is formed, avoiding the electrode. A plurality of external terminals, wherein at least one of the external terminals is provided without being electrically connected to the electrode, and the external terminals excluding the at least one external terminal are: A semiconductor device electrically connected to the electrode by wiring. 8. The semiconductor device according to claim 1, wherein the resin layer is formed between the external terminal and the semiconductor substrate. 9. The semiconductor device according to claim 1, wherein the semiconductor substrate is a semiconductor chip. 10. The semiconductor device according to claim 1, wherein the semiconductor substrate is a semiconductor wafer, and has a plurality of the integrated circuits. 11. A circuit board on which the semiconductor device according to claim 1 is mounted. 12. An electronic device including the semiconductor device according to claim 1. Description: 13. A resin layer is formed on a surface of the semiconductor substrate on which an electrode electrically connected to the integrated circuit is formed, avoiding the electrode so that the upper surface has a planar shape without corners, A method of manufacturing a semiconductor device, comprising forming a wiring from an electrode to the upper surface of the resin layer, and electrically connecting an external terminal to the wiring.