JP2003282382A - Method for manufacturing semiconductor circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor circuit, which contains a process of exposing sequentially on a piece of wafer a plurality number of times as to a mask having a different pattern, and in which a plurality of the semiconductor circuits obtained by cutting a piece of wafer into a plurality of separated semiconductor chips, by which it can be identified from what part of the wafer the semiconductor chip was isolated even after the wafer is isolated into the semiconductor chips. <P>SOLUTION: As to a piece of mask for creating a circuit part 11 to be inspected visually from a surface of a semiconductor chip 10, a relative position, with respect to the other masks differs corresponding to each position on a wafer 1 of a plurality of semiconductor circuits created on a piece of wafer 1, whereby a position on a piece of wafer 1, where the semiconductor circuit mounted on the semiconductor chip 10 is created is recorded on the semiconductor chip 10. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor circuit which includes a process of sequentially exposing one wafer for a mask having a different pattern and is divided into a plurality of semiconductor chips by cutting. .

[0002]

2. Description of the Related Art A semiconductor chip encapsulated in a package is formed by forming a plurality of semiconductor circuits on a single wafer and then cutting the wafer into individual semiconductor circuits to separate the semiconductor circuits. The semiconductor chip is completed, and the semiconductor chip is enclosed in a package to complete the process.

When a product defect is found in the semiconductor chip enclosed in the package, it is necessary to analyze the product defect and try to prevent recurrence.

Here, the defects generated in the semiconductor chips are concentrated in a plurality of semiconductor chips separated from the peripheral portion of the wafer, or concentrated in a plurality of semiconductor chips separated from the lower part of the wafer. Often depends on the position of the wafer. Therefore, in order to analyze product defects and prevent recurrence, it is important to know from which part of the wafer the defective semiconductor chip is separated.

[0005]

However, if the wafer is separated into semiconductor chips, it becomes unclear which part of the wafer each semiconductor chip is separated from.

In view of the above circumstances, the present invention provides a method for manufacturing a semiconductor circuit, which can identify from which part of a wafer a semiconductor chip is separated even after the wafer is separated into semiconductor chips. The purpose is to do.

[0007]

A method of manufacturing a semiconductor circuit according to the present invention, which achieves the above object, includes a step of successively exposing one wafer for a mask having different patterns, and a plurality of steps by cutting. In the method of manufacturing a semiconductor circuit to be separated into semiconductor chips, the relative position of one mask with respect to another mask is determined according to each position on the wafer of a plurality of semiconductor circuits formed on one wafer. On the semiconductor chip by changing the
It is characterized in that the position on the wafer is recorded.

According to the method of manufacturing a semiconductor circuit of the present invention,
Since the exposure position of the semiconductor chip is shifted each time step-and-repeat is repeated, even after the wafer is separated into semiconductor chips, by observing the pattern portion created using the mask, the semiconductor chip From which part of the wafer was separated.

In the method of manufacturing a semiconductor circuit of the present invention, the one mask is a mask for forming a bonding pad opening, and the opening position of the bonding pad is formed on one wafer. Semiconductor chip,
The mask may be made different according to the position on the wafer, or the one mask may be a mask for forming a predetermined wiring layer, and the position of the predetermined wiring layer may be set on one wafer. It is preferable that the semiconductor chips to be built differ depending on the position on the wafer.

If a mask for forming a protective film or a mask for forming a predetermined wiring layer is used, the pattern portion formed by using these masks can tolerate a slight misalignment with respect to other layers. Even if the positions are changed to represent the upper position, the performance of the semiconductor circuit is not affected.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

In the method of manufacturing a semiconductor circuit of this embodiment,
After creating multiple semiconductor circuits on one wafer,
The wafer is separated for each semiconductor circuit. When a predetermined semiconductor circuit is formed, a known method is adopted in which a pattern forming process of projecting a mask pattern on one wafer and forming a shape along the pattern is repeated a plurality of times for masks having different patterns. To be done. The mask pattern is projected by using a stepper to sequentially move the mounting table on which the wafer is placed and performing mask alignment for each partial area of the wafer in which each semiconductor circuit is formed, that is, for each semiconductor chip, and then for the mask pattern. To project.

FIG. 1 is a diagram for explaining mask alignment when forming a bonding pad opening in a protective film on the uppermost layer of a semiconductor chip.

Twenty-one semiconductor chips 10 are separated from the wafer 1 shown in FIG. Each semiconductor chip 10 has
The pattern forming process has already been performed a plurality of times, and the bonding pad 12 made of a rectangular wiring has already been formed. Further, a protective film 11 is also formed on each semiconductor chip 10 so as to cover the bonding pad.
In order to connect the bonding wire to the bonding pad, an opening forming pattern for opening an opening in the protective film 11 is projected on each semiconductor chip 10. FIG. 1A is a magnified view showing the relative position of the central semiconductor chip 10 surrounded by the alternate long and short dash line and the opening forming pattern projected on the central semiconductor chip 10 to the bonding pad 12. FIG. 3B is an enlarged view showing a relative positional relationship similar to that of FIG. 3A with respect to the lower left semiconductor chip 10 surrounded by an alternate long and short dash line, and FIG.
It is an enlarged view which shows the same relative positional relationship about the upper right semiconductor chip enclosed with the dashed-dotted line. In each of these enlarged views, the rectangle shown by the solid line is the semiconductor chip 1.
The bonding pad 12 within 0 is represented, and the rectangle shown by the dotted line represents the opening 11a of the opening forming pattern. The opening forming mask used for projecting the opening forming pattern is aligned for each semiconductor chip 10 by moving the mounting table on which the wafer is placed by the stepper. In the alignment in the central semiconductor chip 10 surrounded by the one-dot chain line, the opening forming pattern to be projected is the bonding pad 1 in the central semiconductor chip 10.
To match the pattern already formed as 2.
An opening forming pattern is projected so that an opening is provided at the center of the bonding pad (see the enlarged view of (a)).

Here, even if the formation position of the opening formed in the uppermost protective film is slightly displaced from the center of the bonding pad,
It does not affect the performance of the semiconductor circuit. In this embodiment,
The position where the opening is formed is made different by the stepper according to the position of the semiconductor circuit formed on one wafer on the wafer. Hereinafter, description will be made using XY coordinates. Here, the horizontal direction in FIG. 1 is the X direction, and the vertical direction is the Y direction. The numbers in parentheses on each semiconductor chip 10 shown in FIG. 1 indicate the relative position of the opening forming pattern in the central semiconductor chip surrounded by the one-dot chain line with respect to the bonding pad 12 in the X direction as well. When the direction is also set to ± 0 (that is, the shift is set to ± 0), it represents how many μm the projected pattern is projected in the X and Y directions. That is, the numbers in parentheses represent the displacement of the relative position of the mask for forming an opening with respect to other masks which have already undergone pattern projection. The lower left semiconductor chip 10 surrounded by the one-dot chain line
Then, the projected position of the opening forming pattern is -1 μm in the X direction (1 μm on the left side of FIG. 1), Y, compared with the position of the opening forming pattern projected on the central semiconductor chip.
The image is projected at a position shifted by +2 μm (2 μm downward in FIG. 1) in the direction. That is, as shown in the enlarged view of (b), the opening forming mask is aligned and projected by the stepper so that the opening is provided at the lower left of the bonding pad.
In the upper right semiconductor chip 10 surrounded by the one-dot chain line, the position of the projected opening forming pattern is +2 μm (in the X direction) compared to the position of the opening forming pattern projected on the central semiconductor chip. The image is projected at a position shifted by 2 μm to the right in FIG. 1 and −1 μm in the Y direction (1 μm in the upper part of FIG. 1). That is, as shown in the enlarged view of (c), the opening forming mask is aligned and projected by the stepper so that the opening is provided at the upper right of the bonding pad.
As described above, in the present embodiment, the position of the mask for forming an opening is adjusted by the stepper so that the projected position of the pattern for forming an opening is different depending on each position on the wafer of the plurality of semiconductor circuits formed on the wafer. Make a match. The stepper moves the wafer mounting table to the next semiconductor chip each time the pattern projection is completed on one semiconductor chip. After that, a shape along the projected pattern is formed, and the position on one wafer where the semiconductor circuit mounted on the semiconductor chip is formed in the uppermost protective film 11 of each semiconductor chip 10 is recorded. To be done. Wafer 1 shown in FIG.
Is finally separated into 21 semiconductor chips.
From the surface of each of the separated semiconductor chips, the circuit portion on which the pattern is projected by using the opening forming mask can be magnified and visually recognized with a microscope. Therefore, even with a separated semiconductor chip, it is possible to identify from which part of the wafer the semiconductor chip is separated by observing the position of the opening.

Next, a second embodiment to which the present invention is applied will be described with reference to FIG.

FIG. 2 is a partial sectional view of two semiconductor circuits in which the wiring positions of the wiring layers are different.

In a semiconductor chip having a multi-layered wiring, a specific wiring layer is exclusively assigned to a power source and a power source line is sufficiently wired to reduce noise on the power source in many cases. In this case, the other wiring layer is composed of a signal line, a wiring dedicated to the power supply, and a power supply line for connecting the device.

Two semiconductor circuits 100 shown at the top and bottom of FIG.
Are all manufactured on the same single wafer. In these semiconductor circuits 100, a plurality of wiring layers are laminated on the element portion with an insulating film interposed therebetween. Figure 2
In the figure, the upper two wiring layer portions of the plurality of wiring layers of each of the two semiconductor circuits 100 are shown. Of the two wiring layers 101 and 102 shown in FIG. 2, the wiring of the upper wiring layer 101 is a power line and the wiring of the lower wiring layer 102 is a signal line.

Also in forming each wiring layer, the mask pattern is projected by using the stepper. The mask used here is a wiring layer forming mask that projects a wiring forming pattern corresponding to the wiring pattern of each wiring layer. The mask used when forming the power supply line wiring layer 101 is a power supply line forming mask that projects a power supply line forming pattern, and the mask used when forming the signal line wiring layer 102 is It is a signal line forming mask for projecting a signal line forming pattern. In the alignment of the signal line forming mask, the position is determined by the stepper so that the signal line forming pattern to be projected exactly matches the already formed pattern in any of the semiconductor chips. On the wiring layer 102 of the signal line formed after performing such alignment,
The insulating film 103 is laminated, and a power supply line is formed on the insulating film 103. A contact hole 1031 for connecting a signal line and a power supply line to be formed is opened in the insulating film 103. The alignment of the power supply line forming mask is similar to the alignment of the opening forming mask described with reference to FIG. 1, and in each semiconductor chip, the positional relationship between each semiconductor chip and the mask is formed on the wafer. Positioning is performed differently according to each position on the wafer of the plurality of embedded semiconductor circuits. That is, in the alignment of the semiconductor chip in the center of the wafer, the alignment of the power supply line formation mask with respect to the signal line formation mask is performed, but in the alignment of the other semiconductor chips, the semiconductor chip in the center is aligned. As the distance increases, the relative position of the power line forming mask with respect to the signal line forming mask is displaced. The power line is
The wiring is not as crowded as the signal line and is thicker than the signal line. For this reason, the formation position of the power supply line can be slightly displaced, and even if the formation position is slightly displaced, the performance of the semiconductor circuit is not affected. When the power supply lines are formed by performing such alignment, the positions of the power supply lines are different as in the two semiconductor circuits 100 shown in FIG. 2, and the semiconductors mounted on the semiconductor chips are mounted on the wiring layers of the power supply lines of the respective semiconductor chips. The position on the single wafer where the circuit is built is recorded. After that, each semiconductor chip on which the power supply line is formed is separated into each chip after a bonding pad and a protective film are formed. From the surface of each of the separated semiconductor chips, the power supply line can be magnified and visually recognized with a microscope. Therefore, even if the semiconductor chips are separated, by observing the position of the power supply line,
It is possible to identify from which part of the wafer the semiconductor chip is separated.

In the present invention, the circuit portion for recording the position on one wafer, in which the semiconductor circuit mounted on the semiconductor chip is built, has the above-mentioned uppermost protective film or the power supply line. Not limited to the wiring layer, any circuit portion can be visually recognized from the surface of the semiconductor chip and can be allowed to be displaced relative to another mask.

[0022]

As described above, according to the method of manufacturing a semiconductor circuit of the present invention, it is possible to determine from which part of the wafer the semiconductor chip is separated even after the wafer is separated into the semiconductor chips. Can be identified.

[Brief description of drawings]

FIG. 1 is a diagram for explaining mask alignment for a protective film on the uppermost layer of a semiconductor chip.

FIG. 2 is a partial cross-sectional view of two semiconductor circuits in which wiring positions of wiring layers are different.

[Explanation of symbols]

1 wafer 10 semiconductor chips 11 Protective film 11a opening 12 Bonding pad 100 semiconductor circuits 101, 102 wiring layer 1031 contact hole

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor circuit, which includes a step of sequentially exposing one wafer for a mask having different patterns, and is divided into a plurality of semiconductor chips by cutting. , The relative position with respect to another mask is made different according to each position on the wafer of the plurality of semiconductor circuits formed on the one wafer, so that the position on the one wafer is set on the semiconductor chip. A method of manufacturing a semiconductor circuit, characterized by recording. 2. The one mask is a mask for forming a bonding pad opening, and the position of the opening of the bonding pad is set to a position on the wafer of a semiconductor chip formed on one wafer. The method of manufacturing a semiconductor circuit according to claim 1, wherein the method is different according to the method. 3. The one mask is a mask for forming a predetermined wiring layer, and the position of the predetermined wiring layer is a position of a semiconductor chip formed on one wafer on the wafer. The method of manufacturing a semiconductor circuit according to claim 1, wherein the method is different according to the above.