JP2003280613A - Display device, driving circuit and display method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device in which generation of stripes during a divided driving is suppressed by employing a simple constitution. <P>SOLUTION: A display section 3 is divided between source bus lines S<SB>p-1</SB>and S<SB>p</SB>and respective divided screens are alternatively driven by a first source driver 4 and a second source driver 5. The driving ranges of the drivers 4 and 5 are arbitrarily set by operation starting positions set in a first starting position control circuit 7 and a second starting position control circuit 8. Alternatively, by controlling the operation starting positions to be set in the circuits 7 and 8, the dividing positions are moved at a plurality of positions. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type display device such as a liquid crystal display device and a method for driving the same, and more particularly to a display device for dividing and driving a display panel.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal display device, a display screen may be divided into a plurality of blocks, and the screen of each block may be divided and driven by different data line driving circuits (hereinafter referred to as source drivers). Such divisional driving is performed when high-definition display is required.

An example of the configuration of a liquid crystal display device that performs division driving will be described with reference to FIG. Although FIG. 9 shows an example of two divisions, division drive of three or more divisions is also possible. Also,
Here, the number of inputs of the video signal (Video 1, 2 in FIG. 9) is two, but the number of inputs of the video signal correspondingly increases as the number of divisions increases. Further, although FIG. 9 shows an example of analog driving, the same effect can be obtained in the case of digital driving.

As shown in FIG. 9, in the liquid crystal display device 100, the source bus line S _n (1 ≦ n ≦ N: N is a natural number divisible by 4) and the gate bus line G _m (in the display unit 102 on the substrate 101). 1 ≦ m ≦ M) are arranged so as to intersect with each other, and further, the source driver 103 that drives the source bus lines S _{1 to} S _N around the display unit 102.
When, and a gate driver 104 for driving the gate bus lines G ₁ ~G _M. The reason why N is a natural number that can be divided by 4 is to establish a relationship of (writing to FIFO) = (reading from FIFO) × 2 in a video signal generation circuit described later.

In the display unit 102, as shown in FIG.
A picture element 110 which is one unit of display is formed in a portion surrounded by arbitrary two source bus lines S _n and S _{n + 1} and two gate bus lines G _m and G _{m + 1} . .

The picture element 110 in FIG. 10 is formed at the intersection of the source bus line S _n and the gate bus line G _m ,
A thin film transistor 1 as a switching element which is switched by a scanning signal from the gate bus line G _m.
11, a pixel electrode 112 that applies a video signal potential from the source bus line S _n via the thin film transistor 111 to drive the liquid crystal capacitance when the thin film transistor 111 is switched, and a charge storage capacitor provided in parallel with the pixel electrode 112. And 113.

The source driver 103 is connected to one end of the source bus lines S _{1 to} S _N , and has two systems of shift registers 103a and 103b, a video signal line 103c to which the video signal Video1 is input, and a video signal Video2.
Video signal line 103d to which is input, and shift register 1
03a or 103b, and a sampling circuit 103e for sampling with the output signal.

[0008] The shift register 103a, respectively 103b, the source bus lines S ₁ to S _N, which is between the source bus line S _x-1 and S _x to be divided into two drive as a boundary. Note that x = (N / 2) +1, and N is a natural number divisible by 4.

The shift registers 103a and 103b are also provided.
In each case, the start and shift operations are performed at the same timing. This activation is controlled by the shift start signal SP, and the shift operation is controlled by the shift clock signal SCLK.

The video signal line 103c is a video signal Video1 applied to the source bus lines S _{1 to} S _x-1 via the analog switch group on the left side of the sampling circuit 103c.
Is a signal line for supplying. In addition, the video signal line 10
Reference numeral 3d is a signal line for supplying the video signal Video2 applied to the source bus lines _{Sx to SN} via the analog switch group on the right side of the sampling circuit 103c.

That is, the video signal Video1 is the video signal of the image to be displayed on the left half of the display screen of one frame, and the video signal Video2 is the video signal of the image to be displayed on the right half of the display screen.
Note that the video signal for one frame is converted to the video signal Video1
The method of converting to and Video2 will be described later.

The sampling circuit 103e comprises a plurality of analog switches provided between the video signal lines 103c and 103d and the source bus lines S _{1 to SN} . The plurality of analog switches are roughly classified into a left analog switch group and a right analog switch group. The analog switch group on the left side is switching-controlled by the output signal from the shift register 103a, and the video signal V
ideo1 be applied to the source bus line S ₁ ~S _x-1.
The analog switch group on the right side is the shift register 103b.
The video signal Video2 is applied to the source bus lines _{Sx to SN} by switching control according to the output signal from. That is, the left analog switch group samples the video signal Video1 from the video signal line 103c, and the right analog switch group samples the video signal line 103d.
For sampling the video signal Video2 from.

[0013] The gate driver 104 is connected to one end of the gate bus lines G ₁ ~G _M, the gate bus lines G ₁ ~
The scanning signals for driving G _M are sequentially output. With the above configuration, the shift registers 103a and 103b
Operate at the same timing, and the video signal Vid
eo1 and Video2 are sequentially output simultaneously from the left analog switch group and the right analog switch group, respectively.

In the period from one shift start signal SP to the next shift start signal SP, one line image is displayed on the display section 102. By synchronizing this display operation and the scanning signal output operation by the gate driver 104, the liquid crystal display device 100 displays a one-line image based on the video signals Video1 and Video2 on the display screen of the display unit 102. One screen (one frame) is displayed by sequentially and repeatedly displaying the image of one line.
Is displayed.

Next, the driving operation of the source driver 103 will be described in more detail.

As shown in FIG. 11A, the original video signal V
In the video, the potential changes in one line period. By sampling this original video signal Video at every time interval t0, the data potential D
_{1 ~D x-1, D x} ~D N is obtained.

This sampled data potential D ₁ ~
D _x-1 and D _{x to} D _N are divided into two data potentials D _{1 to} D _x-1 as the video signal Video1 and data potentials D _{x to} D _N as the video signal Video2. Video signal Vid
eo1 and Video2 are output at the same time as shown in FIG. 11B in synchronization with the data clock signal DCLK having a cycle of 4t0.

The shift register 103a controls ON / OFF of the analog switch group on the left side in synchronization with the data clock signal DCLK to sequentially output the video signal potentials D ₁ , D ₂ , ..., D _x-1 of the video signal Video1. To sample. In addition, the shift register 103b receives the data clock signal D
The right analog switch group is ON / OFF controlled in synchronization with CLK to sequentially sample the video signal potentials D _x , D _{x + 1} , ..., D _N of the video signal Video2.

That is, the analog switch group on the left side is
As shown in FIG. 3C, the output signals SRa _{1 to} SRa _{(N / 2)} of the shift register 103a sequentially become high level every period 2t0 to be sequentially turned on (conductive), and shown in FIG. 3B. The video signal potentials D ₁ and D _{2 of} the video signal line Video ₁
, D _x-1 are sequentially applied to the source bus lines S _{1 to} S _x-1 . Similarly, the analog switch group on the right side of FIG.
As shown in (c), the output signals SRb _{1 to} SRb _{(N / 2)} of the shift register 103b are sequentially turned on (conducted) by sequentially becoming high level every period 2t0, and the video signal shown in FIG. Video signal potentials D _x , D _{x + 1} , ..., D of Video 2
_N is sequentially applied to the source bus lines S _{x to} S _N.

Here, one line of the original video signal Video
2 types (first half and second half) of video signals Video1 and Vi
An example of a video signal creation circuit that performs two-division conversion into deo2,
This will be described with reference to FIG.

As shown in FIG. 12, the video signal generation circuit 120 includes an A / D conversion circuit 121, a γ (gamma) correction circuit 122, two first FIFO (first in first out memory) circuits 123a and a first FIFO (first in first out memory) circuit 123a. 2FIF
An O circuit 123b, a first D / A conversion circuit 124a and a second D / A conversion circuit 124b, a gain / offset correction circuit 125, a first buffer amplifier circuit 126a and a second buffer amplifier circuit 126b are provided.

In the video signal creating circuit 120, the A / D conversion circuit 121, the γ correction circuit 122, the first F
IFO circuit 123a and second FIFO circuit 123b
Output lines are formed by buses, and the number of buses depends on the required accuracy of A / D conversion and the FIFO standard. Here, the bus width of the first FIFO circuit 123a and the second FIFO circuit 123b is (Z + 1) bit.

The A / D conversion circuit 121 outputs the original video signal Vi.
deo is input, and the input original video signal Video is converted into a digital signal of (Z + 1) bit by A / D.
Along with conversion, the A / D converted video signal is sampled in the sampling period t0.

The γ correction circuit 122 includes an A / D conversion circuit 12
By nonlinearly converting the digital output from 1
In the liquid crystal display device, correction is performed so that correct luminance can be reproduced with respect to the original image signal Video.

The first FIFO circuit 123a and the second FI
The FO circuit 123b is a two-system first-in first-out memory for temporarily storing the output signal from the γ correction circuit 122.

The first D / A conversion circuit 124a has a first FIF.
The output signal of the first FIFO circuit 123a is connected to the output side of the O circuit 123a and D / A converted. Also, the second
The D / A conversion circuit 124b is connected to the output side of the second FIFO circuit 123b, and D / A converts the output signal from the second FIFO circuit 123b.

The gain / offset correction circuit 125 has a video signal Vide which is an output signal from the first buffer amplifier circuit 126a and the second buffer amplifier circuit 126b.
Correct the level difference between o1 and Video2.

The first buffer amplifier circuit 126a has a first D
Is connected to the output side of the A / A conversion circuit 124a, and the first D / A
The output signal from the conversion circuit 124a is converted into the video signal Video.
As o1, it is amplified by a predetermined amount and temporarily stored. In addition, the second buffer amplifier circuit 126b includes the second D / A conversion circuit 124.
The output signal of the second D / A conversion circuit 124b connected to the output side of b is amplified as a video signal Video2 by a predetermined amount and temporarily stored.

In this way, in the video signal generating circuit 120, the video signal Vi from the first buffer amplifier circuit 126a.
deo1 is output and the second buffer amplifier circuit 126b is output.
To output a video signal Video2.

Next, the operation of the video signal generating circuit 120 will be described below with reference to FIGS. 13 and 14. Here, the original video signal Video is assumed to be a general video signal such as a TV video signal in which a blanking period exists for each line and for each frame. 13 and 14 are continuous timing charts showing the operation of the video signal generation circuit 120 shown in FIG. 12, and the series of signals shown in FIG. 13 correspond to the series of signals shown in FIG. 14, respectively. is doing.

As shown in FIGS. 13 and 14, first,
The original image signal Video is input to the A / D conversion circuit 121, and the A / D conversion circuit 121 receives the input original video signal V.
video is A / D converted, and is sampled at every sampling period t0 based on the sampling clock CK to obtain a video signal potential Da (that is, D ₁ , D ₂ , ...,
D _N ) are sequentially output. Each video signal potential Da is
It is provided by a plurality of potentials corresponding to the (Z + 1) bit digital signal.

Next, the output video signal potentials D ₁ , D ₂ , ..., D _N from the A / D conversion circuit 121 are input to the γ correction circuit 122 and γ corrected. The output video signal from the γ correction circuit 122 is input to the two systems of the first FIFO circuit 123a and the second FIFO circuit 123b.

In the first FIFO circuit 123a and the second FIFO circuit 123b of the two systems, the read enable signals REa and REb are initially invalid (valid at low level). Further, among the output video signals from the γ correction circuit 122, while the video signal on the left side of the image (the signals given to the source bus lines S _{1 to} S _x-1 ) is being input, the write of the first FIFO circuit 123a is performed. Enable signal WEa is valid (valid at low level), second FI
The write enable signal WEb of the FO circuit 123b is invalid, and the video signals D _{1 to} D _x-1 output from the γ correction circuit 122 are sequentially stored in the _first FIFO circuit 123a.

Next, of the output video signals from the γ correction circuit 122, the video signal on the right side of the image (source bus line S
₂ ) while the signals given to _{x to} S _N ) are being input.
The write enable signal WEb of the FIFO circuit 123b is valid, the write enable signal WEa of the first FIFO circuit 123a is invalid, and at the same time, the read enable signal R
Ea and REb are valid. During this time, the 2FIFO circuit video signal outputted from the γ correcting circuit 122 to 123b D _x to D _N are sequentially stored.

Here, the two first FIFO circuits 123 are provided.
Both a and the second FIFO circuit 123b operate with the write clock WCK at the time of writing and the read clock RCK at the time of reading. The write clock WCK is set to double the frequency of the read clock.

First D / A conversion circuit 124a and second D
The circuits subsequent to the / A conversion circuit 124b are read clock RC.
It operates in synchronization with K. That is, the original video signal Video
The video signal is displayed on the display unit 102 by taking twice as long as sampling. In this display operation, since display is performed simultaneously in each of the blocks divided into two, the operation speed at the time of display can be halved at the time of sampling.

The output video signals read from the first FIFO circuit 123a and the second FIFO circuit 123b of the two systems are input to the corresponding first D / A conversion circuit 124a and second D / A conversion circuit 124b, respectively. Each output video signal from the A conversion circuit 124a and the second D / A conversion circuit 124b is input to the corresponding first buffer amplifier circuit 126a and second buffer amplifier circuit 126b.

As described above, the above-mentioned two kinds of video signals Video1 and Video2 are obtained, and the liquid crystal display device can be dividedly driven by using these two kinds of video signals Video1 and Video2.

[0039]

However, when the division driving method is used, there arises an inconvenience that stripes occur at joints (boundary positions) of divided blocks on the display screen. There are two major causes for this. One is that the difference in the characteristics of the drive circuits that drive the divided blocks affects the image quality such as the brightness and the hue of the display, and stripes are generated at the boundary of the blocks due to the difference in the image quality. . The other is that the write timing of the display data is different in the signal lines adjacent to each other across the block boundary,
This is because the states of the voltages applied to these signal lines do not match and the stripes are emphasized.

As a method of reducing the block stripes during division driving, for example, "Display and Driving Method Therefor" has been proposed in Japanese Patent Laid-Open No. 2000-194308. In this display device and its driving method, in order to prevent display unevenness (stripe) from occurring in the vicinity of the boundaries of each block during division driving, the video signals are usually sent to the display section in the same direction in each block. However, the video signal is sent to the display section in the direction in which the boundaries are separated from each other in the left and right directions, or in the direction in which they approach each other. As a result, the conditions of the two signal lines forming the boundary are made close to each other to reduce the stripes.

However, JP-A-2000-19430
In the method described in Japanese Patent Publication No. 8, since the scanning direction is reversed for each divided block, a frame memory and a logic circuit for reading it out in reverse are required, which complicates the circuit configuration and increases the cost of the apparatus. Such a problem occurs.

Further, although the fringes due to the latter cause (that is, due to the write timing of the display data) can be reduced, the fringes due to the former cause (that is, due to the variation in the characteristics of the drive circuit) can be reduced. Can't get Furthermore, even when the refresh rate is lowered, even if the division driving is not necessary due to the operating speed, the division driving that causes stripes must be performed.

The present invention has been made to solve the above problems, and an object thereof is to provide a display device capable of suppressing the occurrence of stripes in divided driving with a simple structure.

[0044]

In order to solve the above-mentioned problems, a display device of the present invention divides a display line corresponding to each scanning line into a plurality of display areas and corresponds to each of the divided display areas. The signal lines to be driven are connected to at least two signal line drive circuits capable of changing the drive regions, and the drive regions of the signal line drive circuits are changed with the lapse of time to drive each display region. It is characterized in that the signal line drive circuit for switching is replaced with the passage of time.

According to the above structure, the display line corresponding to each scanning line is divided into a plurality of display areas, and each divided display area is divided in the division drive driven by a different signal line drive circuit. Since the signal line corresponding to each display area is connected to at least two signal line drive circuits capable of changing the drive area, the signal line drive circuit for driving each signal line can be selected from a plurality of signal line drive circuits. It becomes a state.

Then, under the condition that the signal line drive circuit can be selected, the signal line drive circuit for driving each display area is replaced with the passage of time.

As a result, in the display section of the display device,
Each divided display area is not driven only by the same signal line drive circuit, and variations in the characteristics of the signal line drive circuit are averaged in each display area, and the image quality of each display area is made uniform. Therefore, the stripes at the division positions of the display area are suppressed.

Further, the display device may be configured such that the division position of the display area to be divided is variable and the division position is changed according to the passage of time.

According to the above configuration, since the signal lines corresponding to the respective divided display areas are connected to at least two signal line drive circuits capable of changing the drive areas, each signal in the display device is changed. By changing the display area of the line driving circuit, the division position of the divided display area can be changed.

By changing the division position according to the passage of time, it is possible to prevent the division position from continuing to exist at the same place, and to make it difficult to visually recognize the stripes generated at the division position.

Further, in the above display device, it is preferable that the signal line driving circuits for driving the respective divided display areas are changed during the horizontal blanking period or the vertical blanking period.

According to the above configuration, by switching the signal line drive circuit during the blanking period, it is possible to easily switch the above-mentioned operation and avoid the image disturbance due to the operation switching.

Further, in order to solve the above-mentioned problems, the display device of the present invention is provided with at least two signal line drive circuits whose drive regions can be changed, and these signal line drive circuits can be driven. At least a part of the range is overlapped, and the drive area is variable according to the input drive area control signal. By setting the drive area of each of the signal line drive circuits, the display line corresponding to each scanning line is changed. It is characterized in that it can be divided into a plurality of display areas at arbitrary division positions.

In the display device, the drive area of each signal line drive circuit is changed with the passage of time,
The division position may be changed according to the passage of time.

Alternatively, the display device may be configured such that the division position is set based on a signal from software that generates display image data.

According to the above arrangement, since at least two signal line drive circuits capable of changing the drive area are provided so that at least a part of their drivable ranges overlap, the display unit of the display device. In, the display area can be divided within the overlapping portion of the drivable range of the signal line drive circuit, and the division position can be set at an arbitrary position.

Thus, for example, by performing the operation of changing the division position according to the passage of time,
It is possible to prevent the division positions from continuing to exist at the same location and make it difficult to visually recognize the stripes generated at the division positions.

Further, for example, by setting the division position based on a signal from software for generating display image data, the division line at the division position is overlapped with the display line existing on the display screen. This also makes it possible to make it difficult to visually recognize the stripes generated at the division position.

In the display device, it is preferable that the division position is changed during the horizontal blanking period or the vertical blanking period.

According to the above configuration, by changing the division position during the blanking period, it is possible to easily switch the above-mentioned operation and avoid the image disturbance due to the operation switching.

Further, in the above display device, when the drive speed of the signal line drive circuit is Va and the limit drive speed of the display device is Vb, each of the divided display areas has a drive speed Va satisfying the relationship of Va ≦ Vb. In multiple places that can be displayed without any shortage,
It is preferable that the division position is set.

In the division driving as described above, when the division position is moved, it is necessary to shift the position from the center of the display portion in at least one division position. When the division position is not the center of the display unit, the efficiency of the division drive is usually lower than when the division position is the center.

However, since the required operation speed can be calculated from the operation speed of the input of the video signal and the limit operation speed of the liquid crystal display device used, each divided display area is Va.
By setting the division positions at a plurality of locations that can be displayed at the driving speed Va satisfying the relationship of ≦ Vb without any shortage, it is possible to avoid the demerit of shifting the division positions from the center.

Further, in the above display device, at least one of the plurality of signal line drive circuits provided can drive the entire area of the display portion, and the division drive using the plurality of signal line drive circuits and the entire display portion can be performed. It is possible to adopt a configuration in which both the driving operation and the normal driving using one signal line driving circuit capable of driving the region are possible.

The division drive is an operation for the purpose of realizing high-definition image quality and high-speed operation speed (high refresh rate), and when high-speed operation speed is not required (low refresh rate), division operation is performed. The merit of driving is small, and the demerit such as the occurrence of a striped pattern relatively increases.

On the other hand, according to the above configuration, for example,
At the low refresh rate, by performing normal driving using one signal line driving circuit capable of driving the entire area of the display section, it is possible to avoid the occurrence of stripes due to division driving.

[0067]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. 1 to 3.
It is as follows.

The first embodiment will exemplify a case where the present invention is applied to an active matrix type liquid crystal display device (hereinafter, simply referred to as a liquid crystal display device) having a built-in drive circuit and having a plurality of video signal lines.

The structure of the above liquid crystal display device is shown in FIG. As shown in FIG. 1, the liquid crystal display device 1 includes a source bus line S _n on an insulating substrate (hereinafter simply referred to as a substrate) 2.
(1.ltoreq.n.ltoreq.N; n and N are natural numbers) and the gate bus line Gm (1.ltoreq.m.ltoreq.M; m and M are natural numbers) are driven to display the liquid crystal display unit 3 and the source bus line S. ₁ to S _N and the first source driver 4 and the second source driver 5 for driving the gate driver 6 for driving the gate bus lines G ₁ ~G _M (hereinafter referred to), the first start position control circuit 7 and the second The start position control circuit 8 is provided.

The structure of the display unit 3 is the same as the structure of the display unit 102 described with reference to FIGS. 9 and 10 in the description of the prior art, and therefore detailed description thereof is omitted here.

The first source driver 4 is connected to one ends of the source bus lines S _{1 to} S _N , the first shift register 41, the video signal line 42, and the first sampling circuit 4
3 and 3. The second source driver 5 is connected to the other ends of the source bus lines S _{1 to SN} ,
It has a shift register 51, a video signal line 52, and a second sampling circuit 53.

The first shift register 41 controls ON / OFF of the analog switch group in the first sampling circuit 43, and from the video signal line 42 to a predetermined bus line among the source bus lines S _{1 to} S _N. The input video signal Video1 is sequentially sampled.

At this time, the start of the shift operation of the first shift register 41 is controlled by the shift start signal SP1.
The shift operation is controlled by the shift clock signal SCK. In the first shift register 41, the start position of the shift operation when the shift start signal SP1 is input can be arbitrarily changed based on the numerical value stored in the first start position control circuit 7.

In the first shift register 41, after the shift operation starting from an arbitrary start position reaches the highest stage, the next shift operation returns to the first stage, and the shift operation continues to the stage immediately before the start position. When this happens, the shift operation of the first shift register 41 ends. This operation is the same in the second shift register 51.

That is, the first start position control circuit 7
Is a register that stores the value of n of the source bus line S _n , which is the start position of the shift operation of the first shift register 41. The first shift register 41 sets the start position of the shift operation to the first start position control circuit 7 It is controlled so that it will be at the position of the numerical value stored in. The numerical value stored in the first register 7 is, for example, written from the control unit 9 connected to the liquid crystal display device 1 as an external circuit.

The second shift register 51 controls ON / OFF of the analog switch group in the second sampling circuit 53, and from the video signal line 52 to the predetermined bus line among the source bus lines S _{1 to} S _N. The input video signal Video2 is sequentially sampled.

At this time, the start of the shift operation of the second shift register 51 is controlled by the shift start signal SP2,
The shift operation is controlled by the shift clock signal SCK. Further, also in the second shift register 51, similarly to the first shift register 41, the shift start signal SP2
The start position of the shift operation when is input can be arbitrarily changed based on the numerical value stored in the second start position control circuit 8.

The gate driver 6 has a gate bus line G.
₁ is connected to one end of ~G _M, sequentially supplied to drive the gate signal (scanning signal) to the gate bus line G ₁ ~G _M.

As described above, the control section 9 controls the shift start signals SP1 and SP2 and the shift clock signal SCK.
Are sent to the first shift register 41 and the second shift register 51 at the timing described later, and the first start position control circuit 7 and the second start position control circuit 8 receive the first shift register 41 and the second shift register 51. Write the start position of the shift operation of. Although not shown, the control unit 9 also sends a shift start signal and a shift clock signal to the gate driver 6.

The video signals Video1 and Video2 supplied to the video signal lines 42 and 52 are obtained by dividing the original video signal Video of one line into two types (first half and second half). Here, the original video signal Vid
2 and 3 show the configuration of the video signal creation circuit 10 for converting eo into video signals Video1 and Video2.

As shown in FIG. 2, the video signal generation circuit 10 includes an A / D conversion circuit 11, a γ correction circuit 12, two systems of a first FIFO circuit 13a and a second FIFO circuit 13.
b, a first D / A conversion circuit 14a and a second D / A conversion circuit 14b, a gain / offset correction circuit 15, a first buffer amplifier circuit 16a and a second buffer amplifier circuit 16b, and a selector circuit 17. There is.

The operation of the video signal generating circuit 10 except for the selector circuit 17 is the same as that of the video signal generating circuit 120 described with reference to FIG. 12 in the description of the prior art.

In the video signal generating circuit 120, the first
The outputs from the buffer amplifier circuit 126a and the second buffer amplifier circuit 126b are respectively the video signal Video.
o1 and Video2. On the other hand, in the video signal generation circuit 10, the outputs from the first buffer amplifier circuit 16a and the second buffer amplifier circuit 16b are further passed through the selector circuit 17 to the video signals Video1 and V1.
It is output as video2.

The selector circuit 17 is shown in FIGS. 3 (a) and 3 (b).
As shown in FIG.
The internal connection is switched by H / LOW. The select signal SEL is input from the control unit 9.

When the select signal SEL is HIGH,
As shown in FIG. 3A, the first buffer amplifier circuit 16a
Is the video signal Video1, and the output of the second buffer amplifier circuit 16b is the video signal Video2.
Further, when the select signal SEL is LOW, FIG.
As shown in (b), the output of the first buffer amplifier circuit 16a becomes the video signal Video2, and the output of the second buffer amplifier circuit 16b becomes the video signal Video1.

That is, when the select signal SEL is HIGH, the video signal generating circuit 10 outputs the original video signal Vid.
A signal corresponding to the first half of eo (the left split screen in FIG. 1) is output as the video signal Video1, and the second half (FIG. 1).
The signal corresponding to the right split screen in FIG.
Output as video2. Then, when the select signal SEL is LOW, the video signal generation circuit 10 outputs a signal corresponding to the first half of the original video signal Video as the video signal Vi.
The signal corresponding to the latter half is output as the video signal Video1.

The operation of the liquid crystal display device 1 having the above structure will be described below. Here, the original video signal Video is, like the conventional technique, like the video signal of a television, for each line,
It is assumed that a general video signal has a blanking period for each frame. In the operation of the liquid crystal display device 1 according to the first embodiment, a boundary between divided screens on the display unit 3 (hereinafter, referred to as a division position: indicated by a dashed line in FIG. 1).
Is set between the source bus lines S _{p- 1} and S _p . Here, it is preferable that p = N / 2 + 1 and the division position be the center of the display unit.

First, the first start position control circuit 7 and the second start position control circuit 8 are controlled by the control unit 9 to make the first start position control circuit 7 and the second start position control circuit 8.
The start position of the shift operation of the shift register 41 and the second shift register 51 is written.

Here, since the operation start position of the first shift register 41 is the source bus line S ₁ , 1 is written in the first start position control circuit 7. After that, the first
When the shift start signal SP1 is input to the shift register 41, the shift operation is started from the source bus line S ₁ .

In the second shift register 51, the
Set the operation start position to the source bus line S _pSo that the second
P is written in the start position control circuit 8. Or later,
The shift start signal SP2 is sent to the second shift register 51.
When input, source bus line S_pShift operation from
Be started.

At this time, the first shift register 41 starts the shift operation from the source bus line S ₁ ,
Split screen on the left side of the display unit 3 (source bus line S
_{1 to} Sp _-1 ) are driven by the first source driver 4, and as the video signal Video1, it is necessary to supply a signal corresponding to the left split screen. Similarly, when the second shift register 51 starts the shift operation from the source bus line S _p, the right divided screen (source bus lines S _{p to} S _N ) in the display unit 3 is driven by the second source driver 5. Therefore, as the video signal Video2, a signal corresponding to the right split screen needs to be supplied.

Therefore, at this time, the video signal generating circuit 1
In the selector circuit 17 of 0, the input select signal SEL is HIGH.

That is, 1 is written in the first start position control circuit 7, p is written in the second start position control circuit 8, and the select signal SEL is HIGH.
When it is, the first source driver 4 drives the left split screen in the display unit 3, and the second source driver 5 drives the right split screen. Less than,
This operation is called the first operation.

Since the above-mentioned first operation is the same as the operation described with reference to FIGS. 13 and 14 in the description of the prior art, detailed description thereof will be omitted here. Also,
The sampling clock CK, the read clock RCK, the write clock WCK, the read enable signals REa and REb, and the write enable signals WEa and WEb input in the video signal generation circuit 10 are input from the control unit 9.

In this way, when the image of one line (one line of the scanning line) is written in the display unit 3 by the first operation, in the next line, the right side of the display unit 3 by the first source driver 4 is written. Of the source driver is switched so that the second source driver 5 drives the left divided screen. Hereinafter, this operation is referred to as a second operation.

Specifically, during the second operation, the control unit 9 sets the operation start position of the first shift register 41 as the source bus line S _p and sets the operation start position of the second shift register 51 as the source bus line. In order to set S ₁ , p is written in the first start position control circuit 7 and 1 is written in the second start position control circuit 8. Further, the select signal SEL input to the selector circuit 17 of the video signal creation circuit 10 is LOW.
Can be switched to. However, as described above, when the first operation and the second operation are switched for each line, the start position of the shift operation of the first source driver 4 and the second source driver 5 is On the line
It is from the next stage after the shift operation end position of the previous line. Therefore, the operation start positions of the first shift register 41 and the second shift register 51 may be set only once at the beginning.

In the above description, the video signal generating circuit 10
By switching HIGH / LOW of the select signal SEL input to the selector circuit 17, the signal corresponding to the left split screen is supplied as the video signal Video1 in the first operation, and the right split screen is supplied as the video signal Video2. And a signal corresponding to the right split screen as the video signal Video1 during the second operation.
2, the signal corresponding to the left split screen is supplied.

In the liquid crystal display device 1 according to the first embodiment, by repeating the first and second operations for each line, the first and second source drivers 4 and 4 are provided in both of the two divided screens. The driving by 5 is alternately performed for each line. Therefore, variations in image quality due to the characteristics of the source driver are averaged in both of the two split screens, and almost the same image quality is obtained in both split screens. This reduces stripes at the boundaries of the split screen.

In the above description of the first embodiment,
Although the display unit 3 is driven to divide into two,
Even in the case of division or more, the effect of reducing stripes at the boundary of the divided screen can be obtained similarly.

In the above description, the source driver is set to 2
However, the effect of reducing the stripes at the boundary of the divided screen can be obtained similarly when three or more are used. When using three or more source drivers, it is necessary to connect two or more source drivers at at least one end of the source bus line. In this case, two source drivers may be formed on both sides of the substrate, a selection circuit may be arranged between these two source drivers and the source bus line, and the source driver may be selectively used depending on the selection circuit. Also, even if you use two source drivers,
It is possible to provide these two source drivers at the same end of the source bus line.

In the above description, the first and second
Although the operation is described as being switched for each line, it may be switched for each frame, or may be switched for every plural lines or every plural frames. Furthermore, the switching between the first and second operations may be performed aperiodically.

[Second Embodiment] The following will describe another embodiment of the present invention in reference to FIGS. 4 to 7.

In the first embodiment, by providing a plurality of source drivers capable of changing the driving area, the source driver used for driving each divided screen is switched according to the passage of time (for example, for each line or frame). By switching to), the variations in the image quality of each split screen are averaged to reduce the stripes at the boundaries of the split screens.

On the other hand, in the liquid crystal display device according to the second embodiment, by providing a plurality of source drivers capable of changing the driving area, the boundary itself of the divided screen is moved with the passage of time, This is to make the stripes at the boundaries of the split screen inconspicuous.

Liquid crystal display device 1'according to the second embodiment.
As shown in FIG. 4, it can be realized with a configuration similar to that of the liquid crystal display device 1 according to the first embodiment. However, in the liquid crystal display device 1 ′, the first start position control circuit 7 can be omitted. Further, the video signal creation circuit for creating the video signals Video1 and Video2 is replaced with the video signal creation circuit 10 instead of the video signal creation circuit 10.
0 can be used. The other configurations illustrated in the liquid crystal display device 1 ′ shown in FIG. 4 are the same as the configurations of the liquid crystal display device 1 shown in FIG. 1. Therefore, the same components as those in FIG. Is attached.

The operation of the liquid crystal display device 1'will be described below. Here, the original video signal Video is, like the video signal of the TV, one for each line, as in the conventional technique.
It is assumed that a general video signal has a blanking period for each frame.

In the liquid crystal display device 1 ', a plurality of division positions are set. Here, the division position (indicated by a chain line in FIG. 4) on the display unit 3 is between the source bus lines S _{q- 1} and S _q , and the source bus lines S _r-1 and S _r.
It is set in two places between and. Here, 1 <q <
It is preferable to set N / 2 <r <N and shift the two division positions to the left and right from the center of the display unit.

In the liquid crystal display device 1 ', the display unit 3 has
The dividing position is the source bus line S _q-1And S_qSet up between
The drive operation when it is determined is the first operation, and the source bus
Inn S_r-1And S_rThe second drive operation when set between
And the operation. During the first operation, the first source driver
4 is the source bus line S of the display unit 3.₁~ S_q-1Drive
The second source driver 5 is the source bus line S_q~ S_NDrive
Move. During the second operation, the first source driver 4 displays
Source bus line S of indicator 3₁~ S_r-1Drive the second
Source driver 5 is source bus line S_r~ S_NDrive
It

First, at the time of the first operation, the control unit 9 writes the start position of the shift operation of the second shift register 51 into the second start position control circuit 8. The first
In the shift register 41, the start position of the operation is the source bus line S ₁ in both the first and second operations, so that it is not particularly necessary to set the start position.

Here, since the operation start position of the second shift register 51 is the source bus line S _q , q is written in the second start position control circuit 8. After that, the second
When the shift start signal SP2 is input to the shift register 51, the shift operation is started from the source bus line S _q .

As the video signal Video1 input to the first source driver 4, a signal corresponding to the left divided screen (source bus lines S _{1 to} S _q-1 ) needs to be supplied. Similarly, as the video signal Video2 input to the second source driver 5, a signal corresponding to the right divided screen (source bus lines S _{q to} S _N ) needs to be supplied.

Here, one line of original video signal Video
Is a video signal Video of a form suitable for the first operation.
The operation of the video signal generation circuit for converting the video signal into 1 and Video 2 in two will be described with reference to FIG. Further, the configuration of the video signal creation circuit used here is assumed to be the same as that of the video signal creation circuit 120 shown in FIG. 12 (however, the length of the FIFO used is the maximum width of the divided screen). Depending on the length required).

FIG. 5 exemplifies a case where the division position on the display unit 3 is switched line by line. Furthermore, the split ratio of the left and right split screens during the first operation (lines 1 and 3 in FIG. 5) is a: b, and the split ratio between the left and right split screens during the second operation (line 2 in FIG. 5). It is assumed that the division ratio is b: a.

First, the original image signal Video is input to the A / D conversion circuit 121, and the A / D conversion circuit 121 performs A / D conversion on the input original video signal Video, and at the same time, based on the sampling clock CK. The video signal potential D ₁ is sampled every sampling period t0,
D ₂ , ..., D _N are sequentially output.

Next, the output video signal potentials D ₁ , D ₂ , ..., D _N from the A / D conversion circuit 121 are input to the γ correction circuit 122 and γ corrected. The output video signal from the γ correction circuit 122 is input to the two systems of the first FIFO circuit 123a and the second FIFO circuit 123b. In FIG. 5, the original image signal Video is described as being at the time of being output from the γ correction circuit 122.

Two first FIFO circuits 123a (see FIG. 5)
In the middle FIFO1) and the second FIFO circuit 123b (FIFO2 in FIG. 5), the read enable signals REa and REb are initially invalid (valid at low level).
Has become. Further, among the output video signals from the γ correction circuit 122, while the video signal on the left side of the image (the signals given to the source bus lines S _{1 to} S _q-1 ) is being input,
Write enable signal WE of the first FIFO circuit 123a
a is valid (valid at a low level), the write enable signal WEb of the second FIFO circuit 123b is invalid, and the γ correction circuit 122 is added to the first FIFO circuit 123a.
The video signals D _{1 to} D _q-1 output from are sequentially stored.

Next, of the output video signals from the γ correction circuit 122, the video signal on the right side of the image (source bus line S
₂ ) while the signals given to _{q to} S _N are being input.
The write enable signal WEb of the FIFO circuit 123b is valid, the write enable signal WEa of the first FIFO circuit 123a is invalid, and the second FIFO circuit 123b receives γ.
The video signals D _{q to} D _N output from the correction circuit 122 are sequentially stored.

Here, the two first FIFO circuits 123 are provided.
Both a and the second FIFO circuit 123b operate with the write clock WCK at the time of writing and the read clock RCK at the time of reading.

When the division position is at the center of the display range, the two division blocks are 1/2 of the entire range.
The operating speed of 1/2 can be realized, and in this case, the write clock WCK is set to a frequency twice as high as the read clock. However, in the case where the division position is not the center of the display range as in the second embodiment, the operation speed of (the longer one of the division blocks) / (the whole range) is the limit in principle.

That is, the operating speed of the liquid crystal display device 1'is b / (a + b), and the write clock W
The frequency of CK is set so as to secure at least (a + b) / b times the frequency of the read clock. The frequency of the write clock WCK is equal to the frequency of the sampling clock CK input to the A / D conversion circuit 121.

When the division position is not in the center of the display range, the efficiency of division drive is lower than that in the case of the center, but the required operation speed is the operation speed of inputting the video signal and the limit operation speed of the liquid crystal display device used. Since it can be calculated from, there is no demerit by shifting the division position from the center as long as it does not exceed this range. That is, α ≦ ((a + b) / b) β may be set as the operation speed α of inputting the video signal and the limit operation speed β of the liquid crystal display device used.

At the boundary of the divided screen (here, at the dividing position q), as shown in FIG. 6, 1 line unit (from the data immediately after the dividing position to the data immediately before the dividing position on the next line). The timings Ta to Tc are set so that the timing Ta at which the (line) read is started is between the write start timing Tb of the data immediately after the division position and the write start timing Tc of the next data. Here, it is necessary to synchronize WCK and RCK in order to make the timings of Ta to Tc the same for each line, and this can be realized by resetting RCK for each line.

The first FIFO circuit 123a and the second FIFO circuit 123b of the two systems operate with the read clock RCK during reading. At this time, in the second embodiment,
Since the split position is set at a position deviated from the center of the screen, the length of each split screen is different, and naturally the lead period required for each split screen is also different. Then, the read operation in each divided screen may be controlled so that the end timings thereof match.

However, it is necessary to match the end timing of the read operation in each divided screen at least when the divided position is on the right side of the screen center, and the divided position is on the left side of the screen center. Sometimes, the start timing of the read operation may be the same in each split screen. At this time, the read operation is completed first on the screen having the shorter divided screen, but thereafter, the read operation is completed by invalidating the read enable signal. That is, it is important that the timing of the read operation is controlled such that the write operation of the data read at the start of the read is completed in the first FIFO circuit 123a or the second FIFO circuit 123b.

When the division position is to the right of the center, the read operation end timing is matched in each divided screen, and when the division position is left of the center, the read operation start timing is matched in each divided screen. By performing such control, it is possible to shorten the deviation of the writing timing with respect to the pixels adjacent to each other at the division position as much as possible. Therefore, the conditions of the thin film transistors in these pixels can be made as close as possible, and the problem that stripes are emphasized because the states of the applied voltages to these pixels do not match can be suppressed.

Even if the division position is to the right of the center, if the division position is the same position as the previous line, the start timing of the read operation may be matched in each line on that line. It is possible.

Further, if the control is such that the end timing of the read operation is made to match in each divided screen regardless of the division position, there is an advantage that the timing control becomes easy.

The output video signals read from the first FIFO circuit 123a and the second FIFO circuit 123b of the two systems are input to the corresponding first D / A conversion circuit 124a and second D / A conversion circuit 124b, respectively. Each output video signal from the A conversion circuit 124a and the second D / A conversion circuit 124b is input to the corresponding first buffer amplifier circuit 126a and second buffer amplifier circuit 126b.

As described above, the above-mentioned two types of video signals Video1 and Video2 are obtained, and the liquid crystal display device 1'according to the present embodiment is divided by using these two types of video signals Video1 and Video2. It can be driven.

In the liquid crystal display device 1'according to the second embodiment, two division positions can be changed line by line by repeating the first and second operations described above line by line. For this reason, it is possible to reduce the degree of conspicuous stripes at the division positions.

Incidentally, in the above description of the second embodiment,
Although the display unit 3 is driven to divide into two,
Even in the case of division or more, the effect of reducing stripes at the boundary of the divided screen can be obtained similarly. Also, when three or more source drivers are used, the effect of reducing the stripes at the boundary of the divided screen can be obtained similarly.

Further, in the above description of the second embodiment, the first and second operations are explained as being switched for each line, but they are switched for each frame. Alternatively, it may be switched every plural lines or plural frames. Furthermore, the switching between the first and second operations may be performed aperiodically.

Further, in the above description of the second embodiment, the case where there are two division positions set on the display unit 3 is illustrated, but three or more division positions may be set. .

However, when the number of division positions set in the display unit 3 increases, the number of types of read clocks required for the above operation also increases, which causes a problem that the design becomes difficult. Therefore, in order to obtain a better effect with a small number of read clocks, the read clock is set at the division position (the position farthest from the center) that is possible at the limit operation speed of the liquid crystal display device, and the read clock is set. A method of operating with a fixed clock can be considered.

Further, in the liquid crystal display device 1'according to the second embodiment, the drivable areas of the first source driver 4 and the second source driver 5 are configured to overlap in the entire display section 3, but the present embodiment does not. In the operation according to mode 2,
It does not necessarily have to overlap in the entire display unit 3.

For example, as in the liquid crystal display device 1A shown in FIG. 7, only the inner regions of the two outermost division positions among the plurality of division positions set are the first source driver 4A and the second source driver. The drivable areas of 5A may be overlapped. That is, in the configuration of FIG. 7, the arrangement area of the first shift register 41A and the first sampling circuit 43A is set so that the drivable area of the first source driver 4A is the area of the source bus lines S _{1 to} S _r-1. Then, the second shift register 51A and the second sampling circuit 53A are arranged so that the drivable region of the second source driver 5A becomes the region of the source bus lines S _{q to} S _N.
The placement area of is set.

As described above, the drivable regions of the plurality of source drivers are overlapped only in the inner regions of the two outermost divided positions among the plurality of divided positions that are set. Can be downsized.

[Third Embodiment] The following will describe another embodiment of the present invention in reference to FIG.

In the first embodiment, by providing a plurality of source drivers whose drive areas can be changed, the source drivers used for driving each divided screen are switched according to the passage of time (for example, line by line or frame by frame). By switching to), the variations in the image quality of each split screen are averaged to reduce the stripes at the boundaries of the split screens.

Further, in the second embodiment, by providing a plurality of source drivers whose drive areas can be changed,
By moving the division position itself with the passage of time, the stripes at the boundaries of the divided screens are made inconspicuous.

On the other hand, the liquid crystal display device according to the third embodiment is characterized by performing the operations of the first and second embodiments at the same time. Here, the configuration of the liquid crystal display device according to the third embodiment is similar to that of the first embodiment, and the video signal creation circuit 10 shown in FIG. 2 is used as the video signal creation circuit. However, the division position is the same as in the second embodiment.
And is intended to be a plurality of locations set in the same manner, where the dividing position is a source bus line in the display unit 3 S _q-1 and S _q
And between the source bus lines S _r-1 and S _r
It shall be set at the location.

In the liquid crystal display device according to the third embodiment, the original video signal Video in the video signal creation circuit 10
FIG. 8 shows a procedure for creating two-system video signals Video1 and Video2 from o. The video signal generation circuit 10
Of the first and second buffer amplifiers 1
The procedure up to the outputs of 6a and 16b is the same as the procedure of FIG. 5 described in the second embodiment.

However, in the third embodiment, the selector 17 is provided at the subsequent stage of the first and second buffer amplifiers 16a and 16b, and it is based on HIGH / LOW of the select signal SEL input to the selector 17. Vi
The output of deo1 and video2 is switched.

That is, the select signal SEL is HIGH.
During this period, the signal read and written by the first FIFO circuit 13a becomes the video signal Video1, and the second FI
The signal read and written by the FO circuit 13b becomes the video signal Video2. Conversely, the select signal SEL
Is low, the signal read and written by the first FIFO circuit 13a becomes the video signal Video2,
The signal read and written by the second FIFO circuit 13b becomes the video signal Video1.

Further, in FIG. 8, the H level of the select signal SEL.
IGH / LOW switching is performed every two lines,
This is because the switching timing of the output system of the video signal is the first
This is to prevent it from occurring during a read operation or a write operation in the FIFO circuit 13a or the second FIFO circuit 13b. If the division position is moved for each frame, the selection signal SEL can be switched for each line.

The writing of the start position of the shift operation to the first start position control circuit 7 and the second start position control circuit 8 is controlled as follows. That is, during the period when the select signal SEL is set to HIGH,
Since the first source driver 4 drives the left split screen of the display unit 3 and the second source driver 5 drives the right split screen of the display unit 3, the first start position control circuit 7 has 1
Is written, and q or r is written in the second start position control circuit 8 according to the division position at that time.

On the other hand, during the period when the select signal SEL is set to LOW, the first source driver 4 is operated by the display unit 3
Drive the divided screen on the right side, and the second source driver 5 drives the divided screen on the left side of the display unit 3. Therefore, q or r is written in the first start position control circuit 7 according to the divided position at that time, 1 is written in the second start position control circuit 8.

In the liquid crystal display device according to the third preferred embodiment, the timing of changing the drive circuit, which is the operation of the first preferred embodiment, and the timing of changing the dividing position, which is the operation of the second preferred embodiment, are However, the timing is not limited to the above example, and these can be arbitrarily set as timings independent of each other. Further, when these timings are arbitrarily set, the operation is performed by the read clock RC.
K, write clock WCK, read enable signal RE
a, REb, write enable signals WEa and WEb, select signal SEL, shift start position writing to the first start position control circuit 7 and the second start position control circuit 8, and the like can be performed by appropriately setting them. is there.

[Embodiment 4] Another embodiment of the present invention will be described below. Any of the liquid crystal display devices according to the first to third embodiments has an effect of suppressing the stripes generated at the boundary of the divided screen when the division driving is performed. However, the above first to third embodiments
Although the liquid crystal display device in 1 can suppress the stripes generated during the division drive by the above-mentioned operation, this is not completely eliminated.

On the other hand, the division drive is an operation for the purpose of realizing high-definition image quality and high-speed operation speed (high refresh rate), and when high-speed operation speed is not required (low refresh rate). However, the merit of performing the division drive is small, and the demerit such as the occurrence of the striped pattern is relatively increased.

In the liquid crystal display device according to the fourth embodiment, at the low refresh rate, only one source driver can be used to completely eliminate the generation of stripes due to division driving. Therefore, in the liquid crystal display device according to the present embodiment, at least one of the plurality of source drivers needs to be able to drive the entire area of the display unit 3.

In the liquid crystal display device according to the fourth embodiment, during the operation at the low refresh rate, the video signal is supplied only to the source driver to be driven, and the video signal is not supplied to the other source drivers. In order to realize this, for example, when the video signal creation circuit 120 shown in FIG. 12 is used as the video signal creation circuit, the first FIFO circuit 1
23a, only the read enable signal REa and the write enable signal WEa input to 23a are made valid, and the second FI
Read enable signal R input to the FO circuit 123b
Eb and the write enable signal WEb may be invalidated. Further, when the video signal generation circuit 10 is used, the selector circuit 17 is always supplied with the select signal S in the HIGH state.
EL may be supplied. It should be noted that, regardless of which of the video signal creation circuit 120 and the video signal creation circuit 10 is used, the length of the FIFO used is the first and second FI.
At least one of the FO circuits requires a length of one line.

[Fifth Embodiment] Another embodiment of the present invention will be described below. In the liquid crystal display device according to the first to fourth embodiments, since the division position can be arbitrarily set, it is possible to set the division stripe in a portion that is difficult to see by linking with the software.

For example, when the display screen displayed on the display unit 3 is created by a specific application software or the like, and a fixed display line appears at a specific position on the display screen, the division position is changed. If it is set so as to overlap the display line, even if stripes occur at the division position, it is not recognized as a display defect.

Therefore, the application software as described above is provided with the function of setting the division position at the time of division driving, and by setting the division position in conjunction with the software, division stripes are made difficult to see. It becomes possible to set.

In each of the first to fifth embodiments described above, an example in which the present invention is applied to a liquid crystal display device has been described.
The application of the present invention is not limited to the liquid crystal display device, but may be applied to other active matrix type display devices.

Further, in the above description of the first to fifth embodiments, the first source driver 4, the second source driver 5,
An example of a monolithic display device in which circuits such as the gate driver 6, the first start position control circuit 7, and the second start position control circuit 8 are formed on the same substrate as the display unit 3 has been described. Alternatively, the display unit 3 and the display unit 3 may be formed on a different substrate and connected by an FPC (Flexible Printed Circuit) or the like.

[0158]

As described above, according to the display device of the present invention, the display line corresponding to each scanning line is divided into a plurality of display areas, and the signal lines corresponding to the respective divided display areas form the drive area. The signal line drive circuit is connected to at least two signal line drive circuits that can be changed, and the drive region of the signal line drive circuit is changed according to the passage of time, so that the signal line drive circuit that drives each display region can be changed over time. It is configured to be replaced according to the progress.

Therefore, under the condition that the signal line drive circuit for driving each display area can be selected, the signal line drive circuit for driving each display area is replaced with the passage of time, whereby the above-mentioned display is performed. In the display unit of the device, each divided display area is not driven by the same signal line drive circuit alone.
For this reason, variations in the characteristics of the signal line drive circuit are averaged in each display area, and the image quality in each display area is made uniform, so that it is possible to suppress stripes at the division positions of the display area.

Further, the display device may be configured such that the division position of the display area to be divided is variable and the division position is changed according to the passage of time.

Therefore, in the above display device, by changing the display area of each signal line drive circuit, the division position of the divided display area can be changed, and the division position can be changed according to the passage of time. Thus, it is possible to prevent the division positions from continuing to exist at the same location and to make it difficult to visually recognize the stripes generated at the division positions.

Further, in the above display device, it is preferable that the signal line drive circuit for driving each of the divided display areas is changed during the horizontal blanking period or the vertical blanking period.

Therefore, by performing the replacement of the signal line drive circuit during the blanking period, it is possible to easily switch the above-mentioned operations and to avoid the image distortion due to the operation switching.

As described above, the display device of the present invention is provided with at least two signal line drive circuits whose drive regions can be changed, and these signal line drive circuits have at least one of their drivable ranges. The parts overlap each other, and the drive area is variable according to the input drive area control signal. By setting the drive areas of the signal line drive circuits,
The display line corresponding to each scanning line can be divided into a plurality of display areas at arbitrary division positions.

In the display device, the drive area of each signal line drive circuit is changed with the passage of time,
The division position may be changed according to the passage of time.

Alternatively, the display device may be configured such that the division position is set based on a signal from software that generates display image data.

Therefore, in the display section of the display device, the display area can be divided within the overlapping portion of the drivable range of the signal line drive circuit, and the division position can be set at an arbitrary position.

As a result, for example, by performing the operation of changing the division position according to the passage of time,
It is possible to prevent the division positions from continuing to exist at the same location and to make it difficult to visually recognize the stripes generated at the division positions.

Further, for example, by setting the division position based on a signal from software for generating display image data, the division line at the division position is overlapped with the display line existing on the display screen. This also makes it possible to make it difficult to visually recognize the stripes generated at the division position.

Further, in the display device, it is preferable that the division position is changed during a horizontal blanking period or a vertical blanking period.

Therefore, by changing the division position during the retrace line period, it is possible to easily switch the above-mentioned operation and avoid the image distortion due to the operation switching.

Further, in the above-mentioned display device, when the drive speed of the signal line drive circuit is Va and the limit drive speed of the display device is Vb, each divided display area has a drive speed Va satisfying the relationship of Va ≦ Vb. In multiple places that can be displayed without any shortage,
It is preferable that the division position is set.

Therefore, each divided display area has Va ≦
Since the division positions are set at a plurality of positions that can be displayed at the drive speed Va satisfying the relationship of Vb without any shortage, the efficiency of shifting the division position from the center of the display unit can be improved. You can avoid the disadvantages of falling.

Further, in the above display device, at least one of the plurality of signal line drive circuits provided can drive the entire area of the display portion, and the division drive using the plurality of signal line drive circuits and the entire display portion can be performed. It is possible to adopt a configuration in which both the driving operation and the normal driving using one signal line driving circuit capable of driving the region are possible.

Therefore, at the time of a low refresh rate in which the merit due to the division drive becomes small, the normal drive using one signal line drive circuit capable of driving the entire area of the display section is performed, and the division drive is performed. It is possible to avoid the occurrence of streaks.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a video signal generating circuit in the liquid crystal display device.

FIG. 3A and FIG. 3B are wiring diagrams showing the operation of the selector in the above-mentioned video signal generation circuit.

FIG. 4 is a block diagram showing a configuration of a liquid crystal display device according to a second embodiment of the present invention.

5 is a timing chart showing an operation of a video signal generation circuit used in the liquid crystal display device of FIG.

FIG. 6 is a timing chart showing a relationship of clocks used in the video signal generating circuit near a division position.

FIG. 7 is a block diagram showing another configuration of the liquid crystal display device.

FIG. 8 is a timing chart showing an operation of a video signal generation circuit used in the liquid crystal display device according to the third embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional liquid crystal display device that performs divided driving.

FIG. 10 is an equivalent circuit diagram of a pixel section in a display section of the liquid crystal display device.

11A is a waveform diagram of an original video signal, FIG.
11B is a waveform diagram of a video signal obtained by sampling the original video signal, and FIG. 11C is a timing chart of each signal input to the source driver.

FIG. 12 is a block diagram showing a configuration of a video signal generating circuit used in a conventional liquid crystal display device that performs division driving.

13 is a timing chart showing a part of the operation of the video signal generation circuit of FIG.

14 is a timing chart showing a part of the operation of the video signal generation circuit of FIG.

[Explanation of symbols]

1, 1 ', 1A liquid crystal display device (display device) 3 display unit 4,4A first source driver (signal line drive circuit) 5, 5A second source driver (signal line drive circuit) G ₁ ~G _M gate bus line (Scan line) S _{1 to} S _N source bus line (signal line)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 642 G09G 3/20 642B H04N 5/66 102 H04N 5/66 102B F term (reference) 2H093 NA16 NA22 NA32 NA33 NA41 NC09 NC11 NC16 NC22 NC24 NC31 NC41 ND60 NE01 NE03 NE07 NE10 5C006 AA01 AF73 BB14 BB16 BC03 BC12 BC16 BC23 FA22 GA02 5C058 AA06 BA03 BA13 BA25 BB05 BB11 5C080 AA10 BB06 DD05 FF11 JJ03FF02

Claims (14)

[Claims] 1. A display line corresponding to each scanning line is divided into a plurality of display areas, and a signal line corresponding to each of the divided display areas is connected to at least two signal line drive circuits whose drive areas can be changed. By changing the drive area of the signal line drive circuit with the passage of time, the signal line drive circuit for driving each display area can be replaced with the passage of time. A display device characterized by. 2. The display device according to claim 1, wherein the division position of the divided display area is variable, and the division position is changed according to the passage of time. 3. A signal line driving circuit for driving each of the divided display areas is changed during a horizontal blanking period or a vertical blanking period.
The display device according to item 2. 4. A drive line control circuit comprising at least two signal line drive circuits capable of changing a drive region. These signal line drive circuits are overlapped with at least a part of their drivable range, and drive region control is inputted. The drive area can be changed according to the signal, and the display line corresponding to each scanning line can be divided into a plurality of display areas at arbitrary division positions by setting the drive area of each signal line drive circuit. A display device characterized by. 5. The drive position of each signal line drive circuit is changed according to the passage of time, so that the division position is changed according to the passage of time. The display device according to item 4. 6. The display device according to claim 5, wherein the division position is changed during the horizontal blanking period or the vertical blanking period. 7. When the drive speed of the signal line drive circuit is Va and the limit drive speed of the display device is Vb, each divided display area can be displayed at a drive speed Va satisfying the relationship of Va ≦ Vb without any shortage. The display device according to claim 5, wherein the division positions are set at a plurality of locations. 8. The display device according to claim 4, wherein the division position is set based on a signal from software for generating display image data. 9. At least one of a plurality of signal line driving circuits provided can drive the entire region of the display portion, and division driving using a plurality of signal line driving circuits and the entire region of the display portion can be driven. 9. The display device according to claim 1, which is capable of both a driving operation and a normal driving operation using one signal line driving circuit. 10. A signal line drive circuit, wherein the drive area can be changed according to an input drive area control signal. 11. A display line corresponding to each scanning line is divided into a plurality of display areas, and each of the divided display areas is driven by replacing a signal line driving circuit with the passage of time. And display method. 12. A display line corresponding to each scanning line is divided into a plurality of display areas, and a signal line corresponding to each of the divided display areas has at least two changeable drive areas connected to the signal line. One of the two signal line driving circuits is driven, and the signal line driving circuit that drives each display region by changing the driving region of the signal line driving circuit with time. A display method characterized by being replaced according to the passage of time. 13. A display method, characterized in that a display line corresponding to each scanning line is divided into a plurality of display areas and is driven while changing the division position according to the passage of time. 14. A display unit driven by at least two signal line drive circuits, wherein at least a part of a drivable range is overlapped, and the drive region is variable according to an input drive region control signal. The display line corresponding to each scanning line is divided into a plurality of display areas, and by changing the drive area of each of the signal line drive circuits, the division position of the display area to be divided is changed over time. A display method characterized by being changed according to.