JP3339438B2 - Display device and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is capable of displaying input image data having a resolution lower than that of a display panel in an image display device having a matrix-driven display panel such as a liquid crystal display device or a plasma display. The present invention relates to a display device and a method.

[0002]

2. Description of the Related Art An example of a conventional display device will be described with reference to FIGS. FIG. 1 is a diagram showing display of display data from a conventional timing image signal. FIG. 2 is a diagram illustrating a configuration of a conventional liquid crystal display device using a storage device such as a frame memory. In a conventional display screen, the number of blank pixels of the display panel is reduced at an output timing at which a personal computer or the like corresponds to a display to be displayed as shown in FIG. 1A from an image signal at the timing shown in FIG. Be smaller than the number of dot clocks or the number of Hsyncs outside the display data at the input timing (BH + FH <HP + Hbp + Hfp,
Since there is no (BV + FV <VP + Vbp + Vfp), unless the driving data and the control period are complemented, there is a possibility that a turn-back is displayed at the end or the display panel cannot be driven normally. In order to avoid the problem associated with the realization of the display function, a means for complementing the driving data and the control period using the frame memory shown in FIG. 2 has been employed.

As shown in FIG. 2, a PLL section 24 for generating a sampling clock from an input horizontal synchronization signal (Hsync), and an input horizontal synchronization signal (Hsync).
c) and a control signal generation unit 26 that generates a control signal for controlling each unit from an image synchronization signal, which is a vertical synchronization signal (Vsync), and a sampling clock generated by the PLL unit 24, and an A / D converter. , An S / H unit 28 for sampling pixel data input by a signal input from the control signal generation unit 26, and a SW for switching between pixel data from the S / H unit 28 and pixel data in a blank portion.
Unit 30, a memory unit 32 for storing pixel data according to a control signal from the control signal generation unit 26, and a control signal generation unit 2
6, a gate driver 34 composed of a shift register circuit controlled by a start pulse, a shift clock and an output enable signal from the control circuit 6; and a shift register circuit, which latches pixel data at the timing of an output signal from the circuit. A data driver 36 for outputting latched data in accordance with a control signal input through
, The signal from the gate driver 34 and the data driver 3
And a liquid crystal panel 38 for displaying display data from the data including the pixel data from No. 6.

[0004] The input image data is sampled by the S / H unit 28 and stored in the memory unit 32. The control signal generation unit 26 generates control signals required by the liquid crystal panel 38, the gate driver 34, and the data driver 36, and switches the data in the memory unit 32 and the black data for the margin by the SW unit 30 while switching the data. Driver 3
6 so that display panel drive data is input.
That is, XGA (extended video gr)
aphs array) resolution display panel with VG
When displaying image data of A (video graphics array) resolution, the input image data is sampled at the timing of VGA, stored in the frame memory, and the stored data is extracted while the blank portion is black data. And the above-mentioned display is realized by driving the display panel at the timing of XGA.

Further, when driving the display panel, more pixels are driven within a timing other than the display data at the input timing. In other words, the driving of the pixel can be complemented by partially enlarging the pixel. Among the means, the following can be mentioned as the enlargement in the vertical direction. JP 1
The method described in -158490 is to enlarge the shift clock to the gate driver by n times and scan by n times during one horizontal synchronizing signal period to perform enlarged display. The liquid crystal display device described in Japanese Patent Application Laid-Open No. 5-143028 generally enlarges the display by simultaneously driving N lines by extending the start pulse of one horizontal period to the N horizontal synchronization signal period. JP-A-7-14666
Patent Document 6 discloses a scan electrode driving circuit and an image display device using the same, in which a SW circuit is added in a gate driver,
By controlling this, an output is switched, a plurality of drive pulses are output, and a plurality of lines are collectively driven to perform enlarged display.

[0006]

When displaying analog image data corresponding to a multi-scan type CRT display device output from a personal computer or the like, the resolution and the timing of input signals are various, and these image signals are varied. Is displayed on an image display device using a display panel that performs matrix driving with a fixed number of pixels, a circuit for converting control timing of image data, an image synchronization signal such as a horizontal synchronization signal or a vertical synchronization signal, or the like is required. . In the conversion, there is also a method of displaying pixel data subjected to density conversion by conversion to the number of pixels of the display panel, but in the display of fonts, linear diagrams, etc., when the multiple value of the density conversion is not an integer or the same in vertical and horizontal, Deformation of fonts and linear diagrams and blurring of borders are difficult to see, and are not practical.

Therefore, the above-described conversion is performed in the display panel,
The input pixel data is displayed with no conversion of the number of pixels or enlarged by the same multiple of the same length and width.
A display function for controlling the display panel so as not to cause an abnormality and to prevent display of unnecessary pixel data is regarded as important. Among the above-mentioned conventional systems, those having a storage device such as a memory require a high material cost and increase power consumption, and are realized in a display device including an analog circuit which does not digitize input image data. Is also impossible.

In the method disclosed in Japanese Patent Application Laid-Open No. 1-158490, the number of searches is n times in one horizontal period, so that the driving time of one line is shortened. According to the device disclosed in the publication -143028, in the driving of the display data portion, N horizontal periods, N horizontal periods,
Since one drive signal is output and non-enlarged display is shifted by one line, the data of one line before is driven with reverse polarity before one horizontal synchronization signal of display data drive, so that the display data There is also concern that driving will be insufficient,
The device disclosed in Japanese Patent Application Laid-Open No.
It can be improved by controlling the drive pulse freely output by W control. However, the cost and power consumption of the V driver increase, and the number of control signals increases. There is a concern about source generation. Further, these enlargement means are only for gate driving, and can be enlarged in the vertical direction, but cannot be partially enlarged in the horizontal direction.

An object of the present invention is to avoid these display defects and the drawbacks of increased cost and power consumption, and to convert the image data of lower resolution than the display function and display panel without the number of pixels, or It is an object of the present invention to provide a display device and a method for realizing a display function at an integer multiple of the same height and width.

[0010]

A display device according to the present invention comprises: a PLL section for generating a clock pulse from an input horizontal synchronizing signal; and a PLL section for generating each section from the input horizontal synchronizing signal, vertical synchronizing signal and the clock pulse. A control signal generator for generating a control signal to be controlled; a SW unit for switching pixel data to a display portion of a display screen and black data to a blank portion of the display screen from the control signal;
An S / H unit that samples pixel data from the unit according to the control signal; a data driver that outputs the pixel data to the display screen according to a control signal; and the display screen according to a control signal output from the control signal generation unit And a liquid crystal panel which is the display screen, and which controls the pixel data from the data driver, and displays the display data according to a control signal from the gate driver. An interlaced display method in which data for one line is displayed every other line with a data signal obtained by masking display data synchronized with the thinned horizontal synchronizing signal at every pulse and alternately displaying lines for each frame And simultaneously driving a plurality of lines every other line, and A scan electrode driving method is employed in which the display timing is varied to partially enlarge the display in the vertical direction, and pixel data having a resolution lower than the resolution of the liquid crystal panel is converted to extra data in a margin of the display screen. Are displayed without displaying and without converting the pixel ratio. Further, the horizontal synchronizing signal is thinned out every other pulse, and a display signal synchronized with the thinned out horizontal synchronizing signal is masked. One line of data is displayed on n lines every n integer lines. In addition to the interlaced display method in which lines to be displayed are alternately displayed, a plurality of lines are collectively driven at every nth line, and the timing of the shift clock is varied during one frame to partially enlarge the display. An electrode driving method is adopted, and pixel data having a resolution lower than the resolution of the liquid crystal panel is enlarged and displayed at a pixel ratio n times without displaying extra data in a blank portion of a display screen. .

[0011] The above-described driving method complements the margins.
Due to the thinning out of the horizontal synchronizing signal and the masking of the display data for one line, a period other than the display data at the input timing is added by one horizontal synchronizing signal period, and the phase of the control synchronizing signal is adjusted for the display position adjustment. The data and timing of the horizontal margin (BH + FH) in FIG. In addition, the data of the vertical blank portion (BV + FV) in FIG. 1A can be complemented by the interlaced driving method and the collective driving of a plurality of lines every other line of the display panel and shift clock control. At this time, since the driving period for one line includes two horizontal synchronization signal periods, a sufficient driving time can be secured, and the image quality can be prevented from deteriorating even when the reverse polarity data of the display portion is continuously driven.

Further, according to the present invention, in a display method of a display device having a liquid crystal panel which performs matrix driving, an input horizontal synchronizing signal is thinned out every other pulse, and display data synchronized with the thinned out horizontal synchronizing signal is masked. With the data signal, one line of data is displayed every other line, the lines to be displayed are alternately changed for each frame, a plurality of lines are collectively driven every other line, and the timing of the shift clock during one frame is changed. The pixel data having a resolution lower than the resolution of the liquid crystal panel is displayed in a partially enlarged manner in the vertical direction by changing the pixel data without displaying extra data in the margin of the display screen and without converting the pixel ratio. It is characterized by displaying.

Further, according to the present invention, in a display method of a display device having a liquid crystal panel which performs matrix driving, an input horizontal synchronizing signal is thinned out every other pulse, and display data synchronized with the thinned out horizontal synchronizing signal is masked. With the data signal obtained, one line of data is displayed on n lines at every nth integer line, the lines to be displayed are alternately changed for each frame, and a plurality of lines are collectively driven at every nth line. Pixel data having a resolution lower than the resolution of the liquid crystal panel is partially enlarged by changing the timing of the shift clock to enlarge the pixel data at a pixel ratio n times without displaying extra data in the margin of the display screen. Is displayed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of an embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram illustrating a configuration of the display device of the present invention. As shown in FIG. 3, the display device of the present invention includes a PLL unit 10 that generates a sampling clock from a horizontal synchronization signal input from an external device, Hsync (horizontal synchronization signal) and Vsync input from the external device.
Control signals Vsp (start pulse), Vclk (shift clock) and Voe (output enable) are generated from an image synchronization signal including c (vertical synchronization signal) and a sampling clock input from the PLL unit 10. SW for masking the display data portion of the display screen input from the control signal generation unit 12, the RGB data input from the external device, the black data of the margin of the display screen, and the control signal from the control signal generation unit 12. And an S / H unit 1 that samples pixel data input from the SW unit 14 according to a control signal input from the control signal generation unit 12
6, a gate driver 18 having a shift register circuit controlled by control signals of a start pulse (Vsp), a shift lock (Vclk), and an output enable (Voe) input from the control signal generator 12;
The pixel data is latched at the timing of the output signal output from the shift register circuit controlled by the control signal from the control signal generation unit 12, and the latched data is output to the liquid crystal panel according to the control signal from the S / H unit 16. And a liquid crystal panel 22 which is controlled by the gate driver 18 and the data driver 20 and displays RGB data input from an external device.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a timing chart of each control signal for displaying a low-resolution input video signal according to the embodiment of the present invention. FIG. 5 is a timing chart of each control signal for displaying a low-resolution input video signal according to the embodiment of the present invention while converting the input video signal into an integer multiple of the pixel ratio Y. FIG. 6 shows 1st and 3rd for the timing diagram of FIG. 4 of the present invention.
It is a figure showing operation | movement of a frame. FIG. 7 is a schematic diagram of FIG.
FIG. 8 is a diagram showing operations of 2nd and 4th frames with respect to the timing chart of FIG. FIG. 8 is a diagram illustrating the operation of a frame with respect to the timing diagram of FIG. 5 of the present invention. In this embodiment, the number of collective drive lines is four. The control signal generator 12 receives the input horizontal synchronization signal (Hsync).
Is generated every other pulse, and a start pulse (Hsp) of a data driver control signal whose phase is adjusted is generated.
The SW unit 14 is switched to mask display data synchronized with the thinned horizontal synchronization signal (Hsync). The masked display data is converted by the S / H unit 16 into a data signal (H) conforming to the input specification of the data driver 20 by signal port number conversion, A / D conversion, potential conversion, or the like.
-Data) and output to the data driver 20. At this time, the margin of the line is the HD of FIG.
bp and HDfp, the data driver 2
0 is a timing at which unnecessary data is latched or a malfunction in which a next start pulse (Hsp) is input before all data is latched is avoided.

The control signal generator 12 complements the margins in the vertical direction while realizing an interlaced display method in which lines to be displayed are alternately displayed for each frame in order to supplement the above-described thinning out of the horizontal synchronization signal. The control signal (Vsp, Vclk, and Voe) for driving a plurality of lines at a time is generated for output to the gate driver 18. As shown in FIG. 4, the control signals Vsp, Vclk, and Voe are used in an odd-numbered frame in order to realize m-line batch driving and interlace driving.
First, a start pulse (Vsp) is output m times every other shift clock (Vclk). Thereafter, the blank portion outputs a 2m shift clock (Vclk) every time one line data is driven, and the display portion outputs a 2 shift clock (Vclk). Output enable (V
oe), the gate driver 20 outputs the control signal (Vsp, Vsp).
clk) Output is performed so as to mask an extra output at the time of output shift during input. In the even frame, after the first m start pulses (Vsp) are output, 1
The shift clock (Vclk) is output, and the line to be driven is shifted by one line. In the odd frame, the even line that is not driven is driven. The liquid crystal panel 22 is driven by the control signals for driving these odd and even frames, as shown in FIGS. 6 and 7, the margin is displayed at m / 2 times, and the display is at the pixel ratio of 1: 1. Display can be realized. The complementation of the horizontal synchronizing signal thinning-out is required depending on the resolution and timing of the input signal, but can be dealt with only by changing the number m of collective drive lines. Further, when it is necessary to switch the polarity of the applied data as in the case of a liquid crystal display panel, one line can be set to "+-++-+ -..." or "-++-+" by dot inversion.
− +. . . , And by switching every driving, and controlling every four frames, it is possible to prevent the image quality from deteriorating.
+,-Described in each line application data shown in FIGS.
Represents the polarity of the first dot of the line.

As shown in FIG. 5, the pixel ratio (Y) is doubled,
The number M of batch drive lines (multiple of Y) is set to 8 lines. Since the display of the pixel ratio twice in the horizontal direction can be realized by setting the frequency of the dot clock generated by the PLL to twice, the data driver control signal of the data driver 20 is exactly the same as that of FIG. is there. The gate driver control signal of the gate driver 18 outputs a start pulse (Vsp) M times every successive Y shift clocks (Vclk) in an odd-numbered frame.
2M shift clock (Vc
lk), the display part is a 2Y shift clock (Vclk)
Output. In the even frame, after the first M start pulses (Vsp) are output, the Y shift clock (Vclk) is further output, the line to be driven is shifted by Y line, and in the odd frame, the undriven line is driven. You. The liquid crystal panel 22 is driven by the control signals for driving these odd-numbered frames and even-numbered frames as shown in FIG. 8, and the blank portion displays M / 2 times and the display portion displays the image at an integer Y times the pixel ratio. realizable. The complementation of the horizontal synchronizing signal is different depending on the resolution and timing of the input signal.
Only by changing the number M of collective drive lines or the number of batch drive lines can be dealt with.

[0018]

According to the display device of the present invention, the input pixel data can be displayed by the pixel ratio non-conversion or the conversion of the vertical and horizontal equivalent integer multiples only by the existing driver control method. No need to add signal lines to the driver, no need to add any components and power consumption, and transform low-resolution display panels input to high-resolution display panels into fonts and linear diagrams. And a display function without blurring of the boundary line can be realized. In addition, a sufficient driving time per one line of the display panel can be ensured, so that a still image can be displayed without deterioration of display color image quality.

Further, according to the present invention which does not require a storage device, an analog display panel which does not digitize input image data, which has been impossible until now, can be input to a high resolution display panel without increasing cost and power consumption. A low-resolution display panel can realize a display function without deformation of fonts and linear diagrams and blurring of boundaries.

[Brief description of the drawings]

FIG. 1 is a diagram showing display of display data from a conventional timing image signal.

FIG. 2 is a diagram illustrating a configuration of a conventional liquid crystal display device using a storage device such as a frame memory.

FIG. 3 is a block diagram illustrating a configuration of a display device of the present invention.

FIG. 4 is a timing chart of each control signal for displaying a low-resolution input video signal according to the embodiment of the present invention.

FIG. 5 is a timing chart of respective control signals for displaying a low-resolution input video signal while converting the input video signal into an integer Y times the pixel ratio according to an embodiment of the present invention.

6 is a diagram illustrating the operation of the first and third frames with respect to the timing diagram of FIG. 4 of the present invention.

FIG. 7 is a diagram illustrating the operation of the second and fourth frames with respect to the timing diagram of FIG. 4 of the present invention.

8 is a diagram illustrating the operation of a frame with respect to the timing diagram of FIG. 5 according to the present invention.

[Explanation of symbols]

 Reference Signs List 10 PLL 12 control signal generation unit 14 SW unit 16 S / H unit 18 gate driver 20 data driver 22 liquid crystal panel 24 PLL 26 control signal generation unit 28 S / H unit 30 SW unit 32 memory unit 34 gate driver 36 data driver 38 liquid crystal panel

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 H04N 5/66-5/74

Claims (6)

(57) [Claims] 1. A PLL section for generating a clock pulse from an input horizontal synchronizing signal, and a control signal generating section for generating a control signal for controlling each section from the input horizontal synchronizing signal, vertical synchronizing signal and the clock pulse. A SW unit for switching pixel data to a display portion of a display screen and black data to a blank portion of the display screen from the control signal; and sampling pixel data from the SW unit by the control signal. / H section, a data driver that outputs the pixel data to the display screen by a control signal, a gate driver that controls the display screen by a control signal output from the control signal generation section, and the display screen. Display data is displayed by the controlled pixel data from the data driver and the control signal from the gate driver. A liquid crystal panel, wherein the horizontal synchronizing signal is thinned out every other pulse, and data for one line is displayed every other line with a data signal obtained by masking display data synchronized with the thinned horizontal synchronizing signal. The display employs an interlaced display method that alternates the lines to be displayed on the display, and simultaneously drives a plurality of lines every other line, and changes the timing of the shift clock during one frame to partially enlarge the display in the vertical direction. Adopting a scan electrode driving method, pixel data having a resolution lower than the resolution of the liquid crystal panel, without displaying extra data in a margin of a display screen,
A display device characterized by displaying without conversion of pixel ratio. 2. A PLL section for generating a clock pulse from an input horizontal synchronizing signal, and a control signal generating section for generating a control signal for controlling each section from the input horizontal synchronizing signal, vertical synchronizing signal and the clock pulse. A SW unit for switching pixel data to a display portion of a display screen and black data to a blank portion of the display screen from the control signal; and sampling pixel data from the SW unit by the control signal. / H section, a data driver that outputs the pixel data to the display screen by a control signal, a gate driver that controls the display screen by a control signal output from the control signal generation section, and the display screen. Display data is displayed by the controlled pixel data from the data driver and the control signal from the gate driver. And a liquid crystal panel, thinning the horizontal synchronizing signal to one pulse every and the data signal obtained by masking the display data in synchronism with the horizontal synchronizing signal obtained by thinning the data for one line to the integer n lines every n
It employs an interlaced display method in which lines are displayed and the lines to be displayed are alternately displayed for each frame, and a plurality of lines are collectively driven every n lines, and the timing of the shift clock is varied during one frame. Adopt the scanning electrode drive system to perform enlarged display, pixel data of lower resolution than the resolution of the liquid crystal panel,
A display device characterized in that a display is enlarged and displayed at a pixel ratio of n times without displaying extra data in a margin portion of a display screen. 3. The data driver latches pixel data sampled by the S / H section with a control signal from the control signal generation section, and latches the pixel data by a control signal output through the S / H section. 3. The display device according to claim 1, wherein the display is output to a liquid crystal panel. 4. The data driver according to claim 1, wherein the timing is such that an erroneous operation in which excess data is latched or a next start pulse is input before all data is latched is avoided. The display device according to claim 3. 5. A display method for a display device having a liquid crystal panel performing matrix driving, wherein an input horizontal synchronizing signal is thinned every other pulse, and a data signal obtained by masking display data synchronized with the thinned horizontal synchronizing signal. Displaying data for one line every other line, alternately displaying the lines for each frame, driving a plurality of lines collectively every other line, and varying the timing of the shift clock during one frame To display pixel data with a resolution lower than the resolution of the liquid crystal panel partially in the vertical direction without displaying extra data in the margin of the display screen and without converting the pixel ratio. Characteristic display method. 6. A display method for a display device having a liquid crystal panel performing matrix driving, wherein an input horizontal synchronizing signal is thinned out every other pulse, and a data signal obtained by masking display data synchronized with the thinned horizontal synchronizing signal. , Integer n
One line of data is displayed on n lines every other line,
While alternately displaying the line for each frame,
A plurality of lines are collectively driven every n lines, and the timing of the shift clock is varied during one frame to partially enlarge and display pixel data having a resolution lower than the resolution of the liquid crystal panel in a blank portion of the display screen. A display method wherein the image is enlarged and displayed at a pixel ratio n times without displaying extra data.