JP2003273488A - Wiring board and manufacturing method thereof - Google Patents

Wiring board and manufacturing method thereof

Info

Publication number
JP2003273488A
JP2003273488A JP2002067848A JP2002067848A JP2003273488A JP 2003273488 A JP2003273488 A JP 2003273488A JP 2002067848 A JP2002067848 A JP 2002067848A JP 2002067848 A JP2002067848 A JP 2002067848A JP 2003273488 A JP2003273488 A JP 2003273488A
Authority
JP
Japan
Prior art keywords
hole
wiring board
conductor layer
thickness
wall surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002067848A
Other languages
Japanese (ja)
Inventor
Toshimasa Iwata
年匡 岩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP2002067848A priority Critical patent/JP2003273488A/en
Publication of JP2003273488A publication Critical patent/JP2003273488A/en
Pending legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board where reduction in reliability is prevented in interlayer connection in a through hole having a high aspect ratio and a fine pattern is formed, and to provide a method for manufacturing the wiring board. <P>SOLUTION: A plating film having a thickness of 30 μm or more is formed on the wall surface of the through hole by a plating process. Then, the inside of the through hole is filled with a protection agent by a paste fill process. As a result, the plating film of the through hole is not affected by etching in a succeeding process or the like. Conductor layers on the front and rear are thinned until a fine pattern can be formed by etching and polishing processes. Then, the fine pattern is formed by a pattern formation process. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は,導体層と層間絶縁
層とを積層してなる積層配線板およびその製造方法に関
する。さらに詳細には,表裏間の導通をとるスルーホー
ルを有する配線板およびその配線板の製造方法に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated wiring board formed by laminating a conductor layer and an interlayer insulating layer, and a method for manufacturing the same. More specifically, the present invention relates to a wiring board having a through hole for establishing conduction between the front and back and a method for manufacturing the wiring board.

【0002】[0002]

【従来の技術】近年,導体層や絶縁層を20層以上も積
層した積層配線板が製造されている。このような積層配
線板としては,例えば,電話の基地局等の産業用途に使
用されるいわゆるインフラ基板がある。このインフラ基
板は,通常の配線板と比較して使用期間が長いため,耐
久性および長期にわたる信頼性が求められる。このこと
もあって,板厚が通常の配線板より大きい。さらに,こ
の積層配線板に形成された貫通穴は,通常の配線板と比
較してアスペクト比が大きい。ここでいうアスペクト比
とは,配線板の板厚を当該貫通穴の穴径で除した値をい
う。そして,この積層配線板にスルーホールめっきを施
す場合には,層間接続の信頼性を確保するために膜厚の
大きいめっき皮膜を形成する必要がある。
2. Description of the Related Art In recent years, a laminated wiring board in which 20 or more conductor layers and insulating layers are laminated has been manufactured. As such a laminated wiring board, for example, there is a so-called infrastructure board used for industrial applications such as a base station of a telephone. Since this infrastructure board has a longer service life than ordinary wiring boards, durability and long-term reliability are required. Because of this, the board thickness is larger than that of ordinary wiring boards. Furthermore, the through hole formed in this laminated wiring board has a large aspect ratio as compared with a normal wiring board. The aspect ratio here means a value obtained by dividing the thickness of the wiring board by the hole diameter of the through hole. When the laminated wiring board is subjected to through-hole plating, it is necessary to form a plating film having a large film thickness in order to secure reliability of interlayer connection.

【0003】また,配線板では,配線板に設けられたス
ルーホール内にピンを差し込むことにより,配線板と電
子部品等との接続が行われることがある。ところが,当
該ピンの抜差しが頻繁に行われた場合には,スルーホー
ルの壁面のめっき皮膜が磨耗してしまう。そのため,ス
ルーホールのめっき皮膜をさらに厚くしておく必要があ
る。具体的には,電解めっき等により30μm以上の膜
厚のめっき皮膜を形成する必要がある。このようなめっ
き皮膜を形成することにより,めっき皮膜がいくらか磨
耗したとしても接触不良を起こすことがない。
Further, in the wiring board, the wiring board and the electronic parts may be connected by inserting pins into the through holes provided in the wiring board. However, when the pin is frequently inserted and removed, the plating film on the wall surface of the through hole is worn. Therefore, it is necessary to make the plated film of the through hole thicker. Specifically, it is necessary to form a plating film having a thickness of 30 μm or more by electrolytic plating or the like. By forming such a plating film, contact failure will not occur even if the plating film is worn to some extent.

【0004】[0004]

【発明が解決しようとする課題】しかしながら,前記し
た従来の技術には,次のような問題点があった。すなわ
ち,通常の電流密度(1〜10A/dm2)により電解
めっきを行った場合には,貫通穴の壁面よりも表面の導
体層の方に多くの金属が析出する。特に,アスペクト比
が10以上の貫通穴に対して電解めっきを行った場合に
は,貫通穴のめっき皮膜の膜厚と比較して,導体層には
2倍以上の厚さのめっき層が形成されてしまう。すなわ
ち,当該貫通穴に30μm以上の膜厚のめっき皮膜を形
成すると,表面の導体層の厚さは60μm以上になって
しまう。そのため,ファインパターンの形成が困難であ
る。
However, the above-mentioned conventional technique has the following problems. That is, when electrolytic plating is performed at a normal current density (1 to 10 A / dm 2 ), more metal is deposited on the conductor layer on the surface than on the wall surface of the through hole. In particular, when electrolytic plating is performed on a through hole having an aspect ratio of 10 or more, a plated layer having a thickness twice or more is formed on the conductor layer as compared with the thickness of the plated film of the through hole. Will be done. That is, when a plating film having a film thickness of 30 μm or more is formed in the through hole, the thickness of the conductor layer on the surface becomes 60 μm or more. Therefore, it is difficult to form a fine pattern.

【0005】この具体的な例として,図4の配線板10
0を用いて説明する。この配線板100には,板厚が
3.0mmの基板1に穴径が0.3mmの貫通穴5が形
成されている。すなわち,貫通穴5のアスペクト比は1
0である。このため,貫通穴5の壁面に厚さ30μmの
めっき皮膜3を形成すると,表面に60μm程度の厚さ
のめっき層2が形成される。すなわち,12μmの銅箔
6を含めると72μmもの厚さの導体層8が形成されて
しまう。このため,導体層8にファインパターンを形成
することは困難である。
As a concrete example of this, the wiring board 10 of FIG.
It will be described using 0. In this wiring board 100, a through hole 5 having a hole diameter of 0.3 mm is formed in a substrate 1 having a board thickness of 3.0 mm. That is, the aspect ratio of the through hole 5 is 1
It is 0. Therefore, when the plating film 3 having a thickness of 30 μm is formed on the wall surface of the through hole 5, the plating layer 2 having a thickness of about 60 μm is formed on the surface. That is, if the copper foil 6 having a thickness of 12 μm is included, the conductor layer 8 having a thickness of 72 μm is formed. Therefore, it is difficult to form a fine pattern on the conductor layer 8.

【0006】また,低電流密度(0.1〜1.0A/d
2)で電解めっきを行うことにより,表面に形成され
るめっき層の厚さと,貫通穴の壁面に形成されるめっき
皮膜の膜厚との不均一を緩和することができる。しか
し,それでも表面のめっき層の厚さが貫通穴の壁面のめ
っき皮膜より薄くなることはない。このため,貫通穴の
壁面に厚さ30μm以上のめっき皮膜を形成した場合に
は,導体層に30μm以上の厚さのめっき層が形成され
る。よって,ファインパターンを形成することは困難で
ある。
Also, low current density (0.1 to 1.0 A / d)
By performing the electroplating with m 2 ), it is possible to reduce the nonuniformity between the thickness of the plating layer formed on the surface and the thickness of the plating film formed on the wall surface of the through hole. However, the thickness of the plating layer on the surface never becomes thinner than that on the wall surface of the through hole. Therefore, when a plating film having a thickness of 30 μm or more is formed on the wall surface of the through hole, a plating layer having a thickness of 30 μm or more is formed on the conductor layer. Therefore, it is difficult to form a fine pattern.

【0007】また,ソフトエッチングによって表面の導
体層を薄くすることができる。しかし,表面の導体層を
薄くするとともに,貫通穴の壁面のめっき皮膜まで薄く
なってしまう。
Further, the conductor layer on the surface can be thinned by soft etching. However, as the conductor layer on the surface becomes thinner, the plating film on the wall surface of the through hole also becomes thinner.

【0008】本発明は,前記した従来の技術が有する問
題点を解決するためになされたものである。すなわちそ
の課題とするところは,高アスペクト比のスルーホール
における層間接続の信頼性の低下を防止し,ファインパ
ターンが形成された配線板およびその製造方法を提供す
ることにある。
The present invention has been made to solve the above-mentioned problems of the conventional technique. That is, it is an object of the invention to provide a wiring board on which a fine pattern is formed and a method for manufacturing the wiring board, which prevents deterioration of reliability of interlayer connection in a through hole having a high aspect ratio.

【0009】[0009]

【課題を解決するための手段】この課題の解決を目的と
してなされた配線板は,導体層と絶縁層とを交互に積層
してなる配線板であって,貫通穴と,表裏面に設けられ
た表層導体層と,貫通穴の壁面に設けられるとともに表
裏間の導通をとる壁面導体層とを有し,壁面導体層の厚
さは,表層導体層の厚さより大きいことを特徴とするも
のである。この配線板は,表裏面の表層導体層が薄い。
このため,ファインパターンを形成することができる。
また,貫通穴の壁面の壁面導体層の膜厚が厚い。このた
め,層間接続の信頼性の低下を防止することができる。
よって,この配線板は,層間接続の信頼性の低下を防止
しつつ,ファインパターンを形成することが可能であ
る。なお,ここでいう貫通穴は,形成された時点で貫通
していればよく,その後に保護剤等を充填されていても
よい。
A wiring board made for the purpose of solving this problem is a wiring board in which conductor layers and insulating layers are alternately laminated, and the wiring board is provided with through holes and front and back surfaces. A surface conductor layer and a wall conductor layer provided on the wall surface of the through hole for establishing conduction between the front and back surfaces, and the thickness of the wall conductor layer is larger than that of the surface conductor layer. is there. This wiring board has thin front and back surface conductor layers.
Therefore, a fine pattern can be formed.
In addition, the film thickness of the wall surface conductor layer on the wall surface of the through hole is large. Therefore, it is possible to prevent the reliability of the interlayer connection from decreasing.
Therefore, with this wiring board, it is possible to form a fine pattern while preventing a decrease in reliability of interlayer connection. In addition, the through hole referred to here may be penetrated at the time of being formed, and may be thereafter filled with a protective agent or the like.

【0010】また,本発明の配線板は,板厚が大きい配
線板の場合に特に有意義である。具体的には,アスペク
ト比が5以上(特には7以上,さらには10以上)の貫
通穴を有する配線板に有意義である。これにより,イン
フラ基板等の板厚の大きい配線板であっても,表裏面の
表層導体層にファインパターンを形成することができ
る。
The wiring board of the present invention is particularly significant in the case of a wiring board having a large thickness. Specifically, it is meaningful for a wiring board having a through hole having an aspect ratio of 5 or more (particularly 7 or more, and further 10 or more). As a result, fine patterns can be formed on the surface conductor layers on the front and back surfaces even with a wiring board having a large thickness such as an infrastructure board.

【0011】また,本発明の配線板の貫通穴は,部品の
端子ピンの差込み用のものである場合に特に有意義であ
る。貫通穴の壁面に十分な厚さの壁面導体層が形成され
ているため,磨耗によっていくらか壁面導体層の厚さが
減少したとしても接触不良を起こすことがないからであ
る。
The through hole of the wiring board of the present invention is particularly significant when it is used for inserting a terminal pin of a component. This is because the wall surface conductor layer having a sufficient thickness is formed on the wall surface of the through hole, so that even if the thickness of the wall surface conductor layer is reduced to some extent due to abrasion, contact failure does not occur.

【0012】また,本発明の配線板は,貫通穴の壁面に
壁面導体層を形成し,当該貫通穴に保護剤を充填し,当
該保護剤が貫通穴に充填された状態で表裏面の表層導体
層の厚さを減少させたものである。すなわち,本発明の
配線板は,ファインパターンを形成することができるま
で表層導体層の厚さを減少させたものである。このた
め,本発明の配線板には,ファインパターンを形成する
ことができる。また,表層導体層の厚さを減少させる処
理を行っている時点では,貫通穴が保護剤により保護さ
れているため,貫通穴の壁面の壁面導体層の膜厚まで小
さくなることはない。よって,層間接続の信頼性の低下
を防止している。
Further, in the wiring board of the present invention, a wall surface conductor layer is formed on the wall surface of the through hole, the through hole is filled with a protective agent, and the through hole is filled with the protective agent. The thickness of the conductor layer is reduced. That is, in the wiring board of the present invention, the thickness of the surface conductor layer is reduced until a fine pattern can be formed. Therefore, a fine pattern can be formed on the wiring board of the present invention. Further, at the time of performing the process of reducing the thickness of the surface conductor layer, since the through hole is protected by the protective agent, the thickness of the wall surface conductor layer on the wall surface of the through hole does not decrease. Therefore, the reliability of the interlayer connection is prevented from decreasing.

【0013】また,本発明の配線板の製造方法は,導体
層と絶縁層とを交互に積層してなる配線板の製造方法で
あって,貫通穴の壁面に壁面導体層を形成する壁面導体
層形成工程と,壁面導体層が形成された貫通穴に保護剤
を充填する穴埋め工程と,穴埋め工程により貫通穴が保
護剤で充填された状態で,表裏面の表層導体層を薄くす
る薄層化工程とを含むことを特徴とする。
The method of manufacturing a wiring board according to the present invention is a method of manufacturing a wiring board in which conductor layers and insulating layers are alternately laminated, wherein a wall surface conductor layer is formed on the wall surface of the through hole. A layer forming step, a step of filling a through hole in which the wall surface conductor layer is formed with a protective agent, and a thin layer for thinning the surface conductive layer on the front and back surfaces in a state where the through hole is filled with the protective agent by the hole filling step And a chemical conversion step.

【0014】本発明の製造方法では,まず,壁面導体層
形成工程により,貫通穴の壁面に必要な厚さの壁面導体
層を形成する。次に,穴埋め工程により,貫通穴を保護
剤によって充填する。これにより,壁面導体層は,後工
程でのエッチング等の影響を受けることがない。このた
め,壁面導体層は,必要な厚さを維持できる。次に,薄
層化工程により,表裏面の表層導体層を薄くする。すな
わち,ファインパターンの形成に支障がない程度まで表
層導体層を薄くするのである。これにより,表裏面の表
層導体層にファインパターンを形成することができる。
In the manufacturing method of the present invention, first, in the wall surface conductor layer forming step, a wall surface conductor layer having a required thickness is formed on the wall surface of the through hole. Next, a through hole is filled with a protective agent in a hole filling process. As a result, the wall surface conductor layer is not affected by etching or the like in a later process. Therefore, the wall surface conductor layer can maintain the required thickness. Next, the surface conductor layers on the front and back surfaces are thinned by a thinning step. That is, the surface conductor layer is thinned to the extent that it does not hinder the formation of the fine pattern. As a result, fine patterns can be formed on the surface conductor layers on the front and back surfaces.

【0015】[0015]

【発明の実施の形態】以下,本発明を具体化した実施の
形態について,添付図面を参照しつつ詳細に説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments embodying the present invention will be described in detail below with reference to the accompanying drawings.

【0016】本実施の形態に係る積層配線板10は,図
1に示す断面構造を有している。積層配線板10は,基
板1と,当該基板1の表裏面の導体層8,8とを有する
積層配線板である。この基板1は,導体層と絶縁層とを
交互に積層したものであるが図中は省略している。基板
1の板厚は,3.0mm程度である。また,各々の導体
層8は,銅箔6と銅めっき層2とにより構成されてい
る。勿論,各導体層には,適宜パターニングが施されて
いる。また,各々の導体層8の厚さは28μm程度であ
り,そのうち銅箔6は12μm程度である。
The laminated wiring board 10 according to the present embodiment has a sectional structure shown in FIG. The laminated wiring board 10 is a laminated wiring board including the substrate 1 and the conductor layers 8 on the front and back surfaces of the substrate 1. This substrate 1 is one in which conductor layers and insulating layers are alternately laminated, but is omitted in the drawing. The plate thickness of the substrate 1 is about 3.0 mm. Each conductor layer 8 is composed of a copper foil 6 and a copper plating layer 2. Of course, each conductor layer is appropriately patterned. The thickness of each conductor layer 8 is about 28 μm, of which the copper foil 6 is about 12 μm.

【0017】さらに,積層配線板10には,貫通穴5が
形成されている。また,貫通穴5の壁面には,表裏面の
導体層8,8間の導通をとるため,銅めっき皮膜3が形
成されている。この貫通穴5の穴径は,0.3mm程度
である。すなわち,貫通穴5のアスペクト比はおよそ1
0である。また,貫通穴5の壁面の銅めっき皮膜3の膜
厚は30μm程度である。すなわち,表面の導体部分
(厚さ:28μm)よりも貫通穴5の壁面の導通部分
(膜厚:30μm)の方が厚い。
Further, a through hole 5 is formed in the laminated wiring board 10. In addition, a copper plating film 3 is formed on the wall surface of the through hole 5 in order to establish conduction between the conductor layers 8 on the front and back surfaces. The diameter of the through hole 5 is about 0.3 mm. That is, the aspect ratio of the through hole 5 is about 1
It is 0. The thickness of the copper plating film 3 on the wall surface of the through hole 5 is about 30 μm. That is, the conductive portion (thickness: 30 μm) on the wall surface of the through hole 5 is thicker than the conductor portion (thickness: 28 μm) on the surface.

【0018】次に,積層配線板10の製造プロセスを図
2のフローチャートに基づいて説明する。まず,表裏面
の導体層8,8間の導通をとるために電解銅めっきを行
う(S1:めっき工程)。これにより,貫通穴5の壁面
に厚さ30μm程度の銅めっき皮膜3が形成される。ま
た,各々の銅箔6上に厚さ60μm程度の銅めっき層
2,2が形成される。すなわち,12μmの厚さの銅箔
6と併せて,72μm程度の厚さの導体層8,8が形成
される。なお,この電解銅めっきは,通常の電流密度で
行ってもよいし,低電流密度で行ってもよい。
Next, the manufacturing process of the laminated wiring board 10 will be described with reference to the flowchart of FIG. First, electrolytic copper plating is performed to establish conduction between the conductor layers 8 on the front and back surfaces (S1: plating step). As a result, the copper plating film 3 having a thickness of about 30 μm is formed on the wall surface of the through hole 5. Further, copper plating layers 2 and 2 having a thickness of about 60 μm are formed on each copper foil 6. That is, the conductor layers 8 having a thickness of about 72 μm are formed together with the copper foil 6 having a thickness of 12 μm. The electrolytic copper plating may be performed at a normal current density or a low current density.

【0019】次に,貫通穴5に溶解可能なペースト状の
保護剤を充填する(S2:ペースト充填工程,図3)。
当該保護剤により銅めっき皮膜3が外部から遮断される
ため,銅めっき皮膜3が保護される。保護剤としては,
例えば,サンノプコ社製の「ノプコキュアF701」
(商品名)が使用可能である。
Next, the through hole 5 is filled with a soluble paste-like protective agent (S2: paste filling step, FIG. 3).
Since the copper plating film 3 is shielded from the outside by the protective agent, the copper plating film 3 is protected. As a protective agent,
For example, San Nopco's "Nopco Cure F701"
(Product name) can be used.

【0020】次に,導体層8,8を薄くするためにハー
フエッチングを行う(S3:エッチング工程)。これに
より,各々の導体層8は,厚さ36μm程度まで薄くな
る。なお,このエッチングでは保護剤が溶解することは
ない。
Next, half etching is performed to thin the conductor layers 8 (S3: etching step). As a result, the thickness of each conductor layer 8 is reduced to about 36 μm. The protective agent is not dissolved in this etching.

【0021】次に,導体層8,8をさらに薄くするため
にバフ研磨を行う(S4:研磨工程)。これにより,各
々の導体層8がさらに薄くなり,厚さ28μm程度とな
る。また,このバフ研磨工程では,表面の微細な凹凸の
除去も行われる。
Next, buffing is performed to make the conductor layers 8 and 8 thinner (S4: polishing step). As a result, each conductor layer 8 is further thinned to have a thickness of about 28 μm. Further, in this buffing step, fine irregularities on the surface are also removed.

【0022】次に,導体層8,8のパターン形成を行う
(S5:パターン形成工程)。ここで,各々の導体層8
は厚さ28μm程度まで薄層化されているため,ファイ
ンパターンを形成することが可能である。このパターン
形成工程では,レジストとして日立化成社製の「H−9
040」等が使用可能であり,当該レジストを現像する
ためには炭酸ナトリウム系の現像液等が使用される。な
お,レジストのパターニング時の露光によって保護剤が
硬化することはない。また,レジストの現像によっても
保護剤が溶解することはない。また,パターンエッチン
グには,塩化銅系のエッチング液等が使用される。この
エッチングによっても保護剤が溶解することはない。す
なわち,銅めっき皮膜3はパターン形成による影響を受
けることはない。
Next, the conductor layers 8 and 8 are patterned (S5: pattern forming step). Here, each conductor layer 8
Since it has been thinned to a thickness of about 28 μm, it is possible to form a fine pattern. In this pattern forming process, as a resist, "H-9 manufactured by Hitachi Chemical Co., Ltd."
040 "or the like can be used, and a sodium carbonate-based developer or the like is used to develop the resist. Note that the protective agent is not hardened by exposure during patterning of the resist. Moreover, the protective agent is not dissolved even when the resist is developed. Further, a copper chloride-based etching solution or the like is used for pattern etching. The protective agent is not dissolved even by this etching. That is, the copper plating film 3 is not affected by the pattern formation.

【0023】次に,必要に応じて保護剤の除去を行う。
これにより,図1に示す配線板10が製造される。保護
剤が除去された貫通穴5には,電子部品等のピンを接続
することができる。そして,貫通穴5の銅めっき皮膜3
は,30μm以上の十分な膜厚を有しているため,ピン
の抜差しによっていくらか磨耗した場合であっても層間
接続の信頼性が低下することはない。なお,この保護剤
の溶解には,サンノプコ社製の「SNソルバー861」
等の現像液が使用可能である。なお,ピンの抜差しを行
わない用途であれば,保護剤を残しておいてもよい。
Next, the protective agent is removed if necessary.
As a result, the wiring board 10 shown in FIG. 1 is manufactured. A pin such as an electronic component can be connected to the through hole 5 from which the protective agent has been removed. And the copper plating film 3 of the through hole 5
Has a sufficient film thickness of 30 μm or more, the reliability of the interlayer connection is not deteriorated even if the pin is removed and attached to cause some abrasion. In addition, to dissolve this protective agent, "SN Solver 861" manufactured by San Nopco
Developer solutions such as the above can be used. Note that the protective agent may be left if the pin is not inserted and removed.

【0024】以上詳細に説明したように本形態の製造方
法では,まず,めっき工程により,貫通穴5の壁面に厚
さ30μm以上の銅めっき皮膜3を形成することとして
いる。次に,ペースト充填工程により,貫通穴5の内部
を保護剤によって充填することとしている。これによ
り,貫通穴5の壁面の銅めっき皮膜3は,後工程でのエ
ッチング等の影響を受けることがなく,30μm以上の
膜厚を確保できる。このため,層間接続の信頼性も高
い。次に,エッチング工程および研磨工程により,導体
層8,8を薄くすることとしている。これにより,各々
の導体層8の厚さを貫通穴5の銅めっき皮膜3の膜厚よ
り薄くすることができる。すなわち,各々の導体層8を
30μm以下の厚さにすることができる。このため,パ
ターン形成工程では,ファインパターンを形成すること
ができる。よって,アスペクト比が大きいスルーホール
の場合であっても,層間接続の信頼性の低下を防止し,
ファインパターンが形成された配線板およびその製造方
法が実現されている。
As described above in detail, in the manufacturing method of this embodiment, first, the copper plating film 3 having a thickness of 30 μm or more is formed on the wall surface of the through hole 5 by the plating process. Next, in the paste filling step, the inside of the through hole 5 is filled with a protective agent. As a result, the copper plating film 3 on the wall surface of the through hole 5 is not affected by etching or the like in a subsequent process, and a film thickness of 30 μm or more can be secured. Therefore, the reliability of interlayer connection is high. Next, the conductor layers 8 are thinned by an etching process and a polishing process. Thereby, the thickness of each conductor layer 8 can be made thinner than the thickness of the copper plating film 3 of the through hole 5. That is, each conductor layer 8 can have a thickness of 30 μm or less. Therefore, a fine pattern can be formed in the pattern forming step. Therefore, even in the case of a through hole with a large aspect ratio, it is possible to prevent deterioration of reliability of interlayer connection,
A wiring board having a fine pattern and a manufacturing method thereof have been realized.

【0025】また,パターン形成工程後に,貫通穴5を
充填している保護剤を溶解することとしてもよい。この
溶解後の配線板10には,貫通穴5に対してピンを抜差
しすることができる。この場合にも,貫通穴5の壁面の
めっき皮膜3は30μm以上の膜厚が確保されているた
め,層間接続の信頼性は高い。
Further, the protective agent filling the through holes 5 may be dissolved after the pattern forming step. Pins can be inserted into and removed from the through holes 5 in the wiring board 10 after the melting. Also in this case, since the plating film 3 on the wall surface of the through hole 5 has a thickness of 30 μm or more, reliability of interlayer connection is high.

【0026】なお,本実施の形態は単なる例示にすぎ
ず,本発明を何ら限定するものではない。したがって本
発明は当然に,その要旨を逸脱しない範囲内で種々の改
良,変形が可能である。例えば,図1中の基板1は,絶
縁層のみであってもよい。
The present embodiment is merely an example and does not limit the present invention. Therefore, naturally, the present invention can be variously improved and modified without departing from the gist thereof. For example, the substrate 1 in FIG. 1 may be an insulating layer only.

【0027】[0027]

【発明の効果】以上の説明から明らかなように本発明に
よれば,高アスペクト比のスルーホールにおける層間接
続の信頼性の低下を防止し,ファインパターンが形成さ
れた配線板およびその製造方法が提供されている。
As is apparent from the above description, according to the present invention, there is provided a wiring board having a fine pattern formed, which prevents deterioration of reliability of interlayer connection in a through hole having a high aspect ratio, and a manufacturing method thereof. It is provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施の形態の製造方法により形成された配線板
の断面を示す図である。
FIG. 1 is a diagram showing a cross section of a wiring board formed by a manufacturing method according to an embodiment.

【図2】実施の形態の製造方法を示すフローチャートで
ある。
FIG. 2 is a flowchart showing a manufacturing method according to an embodiment.

【図3】ペースト充填工程後の配線板の断面を示す図で
ある。
FIG. 3 is a view showing a cross section of the wiring board after the paste filling step.

【図4】従来の形態の製造方法により形成された配線板
の断面を示す図である。
FIG. 4 is a view showing a cross section of a wiring board formed by a conventional manufacturing method.

【符号の説明】[Explanation of symbols]

1 基板 2 導体層 3 めっき皮膜 5 貫通穴 6 銅箔 8 導体層 1 substrate 2 conductor layers 3 plating film 5 through holes 6 copper foil 8 conductor layers

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E317 AA24 BB01 BB12 CC33 CD17 CD25 CD27 CD40 GG14 GG20 5E319 AA02 AA08 AA09 AB01 AC01 GG01 GG20 5E339 AC01 AD03 AE01 BC02 BD02 BD08 BE13 CE06 CE11 CE14 CF16 CF17 CG04 DD04 GG10   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5E317 AA24 BB01 BB12 CC33 CD17                       CD25 CD27 CD40 GG14 GG20                 5E319 AA02 AA08 AA09 AB01 AC01                       GG01 GG20                 5E339 AC01 AD03 AE01 BC02 BD02                       BD08 BE13 CE06 CE11 CE14                       CF16 CF17 CG04 DD04 GG10

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 導体層と絶縁層とを交互に積層してなる
配線板において,貫通穴と,表裏面に設けられた表層導
体層と,前記貫通穴の壁面に設けられるとともに表裏間
の導通をとる壁面導体層とを有し,前記壁面導体層の厚
さは,前記表面導体層の厚さより大きいことを特徴とす
る配線板。
1. A wiring board having conductor layers and insulating layers alternately laminated, wherein a through hole, a surface conductor layer provided on the front and back surfaces, and conduction between the front and back surfaces provided on the wall surface of the through hole. A wiring board having a wall conductor layer having a thickness greater than that of the surface conductor layer.
【請求項2】 請求項1に記載する配線板において,前
記貫通穴のアスペクト比が10以上であることを特徴と
する配線板。
2. The wiring board according to claim 1, wherein the through hole has an aspect ratio of 10 or more.
【請求項3】 請求項1または請求項2に記載する配線
板において,前記貫通穴は,部品の端子ピンの差込み用
のものであることを特徴とする配線板。
3. The wiring board according to claim 1, wherein the through hole is for inserting a terminal pin of a component.
【請求項4】 請求項1から請求項3までのうち少なく
とも一つに記載する配線板において,貫通穴の壁面に壁
面導体層を形成し,当該貫通穴に保護剤を充填し,当該
保護剤が貫通穴に充填された状態で表裏面の表層導体層
の厚さを減少させたものであることを特徴とする配線
板。
4. The wiring board according to claim 1, wherein a wall surface conductor layer is formed on a wall surface of the through hole, and the through hole is filled with a protective agent. The wiring board is characterized in that the thickness of the surface conductor layers on the front and back surfaces is reduced in a state in which the through holes are filled.
【請求項5】 導体層と絶縁層とを交互に積層してなる
配線板の製造方法において,貫通穴の壁面に壁面導体層
を形成する壁面導体層形成工程と,前記壁面導体層が形
成された前記貫通穴に保護剤を充填する穴埋め工程と,
前記穴埋め工程により前記貫通穴が保護剤で充填された
状態で,表裏面の表層導体層を薄くする薄層化工程と,
を含むことを特徴とする配線板の製造方法。
5. A method of manufacturing a wiring board, which comprises alternately stacking conductor layers and insulating layers, wherein a wall conductor layer forming step of forming a wall conductor layer on a wall surface of a through hole and the wall conductor layer are formed. And a hole filling step of filling the through hole with a protective agent,
A thinning step of thinning the surface conductor layer on the front and back surfaces in a state where the through hole is filled with a protective agent by the hole filling step;
A method for manufacturing a wiring board, comprising:
JP2002067848A 2002-03-13 2002-03-13 Wiring board and manufacturing method thereof Pending JP2003273488A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002067848A JP2003273488A (en) 2002-03-13 2002-03-13 Wiring board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002067848A JP2003273488A (en) 2002-03-13 2002-03-13 Wiring board and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JP2003273488A true JP2003273488A (en) 2003-09-26

Family

ID=29199096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002067848A Pending JP2003273488A (en) 2002-03-13 2002-03-13 Wiring board and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2003273488A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006049804A (en) * 2004-07-07 2006-02-16 Shinko Electric Ind Co Ltd Manufacturing method of wiring board
CN100442953C (en) * 2004-03-29 2008-12-10 日本梅克特隆株式会社 Method for making circuit substrate
JP2015222805A (en) * 2014-04-30 2015-12-10 京セラサーキットソリューションズ株式会社 Printed-circuit board and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100442953C (en) * 2004-03-29 2008-12-10 日本梅克特隆株式会社 Method for making circuit substrate
JP2006049804A (en) * 2004-07-07 2006-02-16 Shinko Electric Ind Co Ltd Manufacturing method of wiring board
JP2015222805A (en) * 2014-04-30 2015-12-10 京セラサーキットソリューションズ株式会社 Printed-circuit board and manufacturing method thereof

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