JP2003272947A - Ceramic electronic component and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ceramic electronic component which can be protected against a sheet attack and is almost kept free from a structural defect such as a short circuit or a withstand voltage failure. <P>SOLUTION: Laminated groups C1 to Cn each comprise a first to a third ceramic layer, 110 to 130, and internal electrodes 21 and 22, wherein the first ceramic layer 110 serves as a lowermost layer, and the third ceramic layer 130 serves as an uppermost layer. The laminated groups C1 to Cn are laminated in a manner where the first ceramic layer 110 and the third ceramic layer 130 are located adjacent to each other. The ceramic average grain diameters α1 to α13 and thicknesses T1 to T3 of the ceramic layers 110 to 130 are so set as to satisfy following formulas; (α1≤α2, α3), (0.05<α1≤0.35 μm), (T1<T2, T3), and (0<T1<1.5 μm). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a ceramic electronic component and a method for manufacturing the same.

[0002]

2. Description of the Related Art As one method of manufacturing ceramic electronic components such as capacitors and piezoelectric elements, a ceramic coating containing ceramic powder, an organic binder, a plasticizer, a solvent, etc. is formed on a support by a doctor blade method into a ceramic coating layer. A method is known in which molding is performed and an electrode of palladium, silver, nickel, or the like is formed thereon by screen printing.

When obtaining a laminated structure, the obtained green sheets are laminated so as to have a desired laminated structure, and a ceramic green chip is obtained through a press cutting process. The binder in the ceramic green chip thus obtained was burned out and fired at 1000 ° C to 1400 ° C, and the fired body thus obtained was provided with silver, silver-palladium, nickel,
A terminal electrode made of copper or the like is formed to obtain a ceramic electronic component.

In the above-described manufacturing method, for example, when manufacturing a monolithic ceramic capacitor, a method of reducing the thickness of a ceramic coating layer per layer and increasing the number of laminated layers is adopted as a method of miniaturization and large capacity. It has been. For example, a monolithic ceramic capacitor in which the thickness of the ceramic coating layer is about 3 μm and the number of laminated layers is 800 or more is already known.

By the way, in manufacturing a ceramic electronic component represented by a monolithic ceramic capacitor, when forming an internal electrode thereof, conventionally, a ceramic coating is applied to the surface of a flexible belt-shaped support. It was common to print the internal electrode paste after forming the ceramic paint layer. The support is composed of a polyethylene terephthalate (PET) film or the like.

As the ceramic paint, a paint prepared by mixing an organic binder such as acrylic resin or butyral resin, an organic solvent, a plasticizer and ceramic powder is used.

As the internal electrode paste, a vehicle in which a resin as an organic binder is dissolved by an organic solvent is used, and a conductive metal powder such as Ag, Pd, Ni or Cu is dispersed in this vehicle, and in some cases, the viscosity is increased. Prepared by adding an adjusting diluent. As the organic solvent in the vehicle, terpione, methyl etiketone, or the like is used, and as the binder, a cellulose resin such as ethyl cellulose or nitrocellulose, or an acrylic resin such as butyl methacrylate or methyl methacrylate is used. Further, as the diluent, aromatic hydrocarbon, fatty acid hydrocarbon or the like is used.

However, when the internal electrode paste having the above-mentioned composition is printed on the ceramic coating layer applied on the support according to the conventional manufacturing method, terpione or methyl contained in the internal electrode paste is printed. The organic solvent such as etiketone dissolves the organic binder such as acrylic resin or butyral resin contained in the ceramic coating layer. This phenomenon is called sheet attack.

When sheet attack occurs, it becomes difficult to peel the ceramic coating layer from the support. Also,
Holes and wrinkles may occur in the ceramic paint layer, and when a multilayer ceramic capacitor is manufactured using such a ceramic paint layer, a short circuit failure in which internal electrodes are conducted or a withstand voltage failure occurs, Furthermore, there is a possibility of causing a fatal defect such as the inability to obtain the target electrostatic capacity.

As a means for avoiding this problem, after printing the internal electrodes directly on the support, a ceramic paste is applied thereon to form a ceramic coating layer, and then the ceramic coating layer is formed. There is a method of peeling from the surface of the support together with the internal electrodes (for example, Japanese Patent No. 21366761).

In this case, however, the adhesion between the internal electrode and the ceramic coating layer with respect to the support becomes strong, and it becomes extremely difficult to peel the ceramic coating layer without causing breakage.

The peeling difficulty can be avoided by applying a peeling facilitating agent (hereinafter referred to as a peeling agent) on the surface of the support and forming the internal electrodes and the ceramic coating layer on the surface of the peeling agent. Ah

However, when the internal electrode is printed on the surface of the release agent, since the affinity between the two is low, the surface tension of the internal electrode causes the internal electrode to agglomerate and the pattern shape of the internal electrode collapses. As a result, predetermined characteristics cannot be obtained.

[0014]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a ceramic electronic component, particularly a monolithic ceramic capacitor, which can prevent sheet attack and hardly cause structural defects such as a short circuit defect and a withstand voltage defect. .

Another object of the present invention is to provide a highly accurate and highly reliable ceramic electronic component capable of significantly reducing the probability of peeling difficulty or defective product characteristics even if the ceramic coating layer is thin. It is to provide a manufacturing method.

Still another object of the present invention is to provide a method of manufacturing a ceramic electronic component in which the step difference between the layers due to the electrodes is significantly reduced and the reliability is improved.

[0017]

SUMMARY OF THE INVENTION The present invention discloses a ceramic electronic component and a method of manufacturing the same for solving the above-mentioned problems.

1. Ceramic Electronic Component In order to solve the above problems, a ceramic electronic component according to the present invention includes a ceramic base and a plurality of internal electrodes. Each of the internal electrodes is embedded in the inside of the ceramic base at a distance.

The ceramic substrate includes a first ceramic layer, a second ceramic layer, and a third ceramic layer.

The first ceramic layer is adjacent to one surface side of the internal electrode, and the second ceramic layer is
The third ceramic layer is adjacent to one surface of the other internal electrode which is not adjacent to the first ceramic layer, and the third ceramic layer is adjacent to the other surface of the other internal electrode which is adjacent to the second ceramic layer. There is.

The first and third ceramic layers, and
The internal electrodes form a laminated group in which the first ceramic layer is the lowermost layer and the third ceramic layer is the uppermost layer.

There are a plurality of laminated groups, and the first ceramic layer and the third ceramic layer are laminated in such a manner that they are adjacent to each other.

The average ceramic grain size of the first ceramic layer is α1, the layer thickness is T1, the average ceramic grain size of the second ceramic layer is α2, and the layer thickness is T2.
And the ceramic average particle diameter of the third ceramic layer is α3 and the layer thickness is T3, α1 ≦ α2, α3 0.05 <α1 ≦ 0.35 μm, T1 <T2, T3, and 0 < T1 <1.5 μm is satisfied.

As described above, the ceramic electronic component according to the present invention includes the ceramic base and the plurality of internal electrodes, and each of the internal electrodes is embedded inside the ceramic base at a distance. Thus, it is possible to obtain a ceramic electronic component having a number of laminated layers corresponding to the number of internal electrodes, particularly a laminated ceramic capacitor.

The ceramic substrate includes a first ceramic layer, a second ceramic layer and a third ceramic layer. The first ceramic layer is adjacent to one surface of the internal electrode, the second ceramic layer is adjacent to one surface of another internal electrode that is not adjacent to the first ceramic layer, and the third ceramic layer is adjacent to the third ceramic layer. The layer is adjacent to the other surface of the adjacent other internal electrode of the second ceramic layer. The first and third ceramic layers and the internal electrodes form a laminated group in which the first ceramic layer is the lowermost layer and the third ceramic layer is the uppermost layer.

Therefore, it is possible to obtain a ceramic electronic component, especially a laminated ceramic capacitor, having the first to third ceramic layers and the number of laminated layers depending on the number of internal electrodes for each laminated group.

There are a plurality of laminated groups, each of which is
Stacked. Therefore, it is possible to obtain a ceramic electronic component having a number of laminated layers depending on the number of laminated groups, particularly a laminated ceramic capacitor.

Moreover, each of the stacked groups has a first
The ceramic layer and the third ceramic layer are laminated in a relationship of being adjacent to each other. With this structure, since the dense and highly packed first ceramic layers are interposed between the respective laminated groups, the short-circuit failure rate and the withstand voltage failure rate can be reduced.

Average ceramic particle size α1 of the first ceramic layer, average ceramic particle size α2 of the second ceramic layer,
And the average ceramic particle size α3 of the third ceramic layer
Since α1 ≦ α2 and α3 are satisfied, structural defects such as pinholes and defective withstand voltage can be more effectively avoided.

Further, the average ceramic particle size α1 of the first ceramic layer satisfies 0.05 <α1 ≦ 0.35 μm. By satisfying this condition, it is possible to reduce the sheet attack in the manufacturing process and reduce the short-circuit defect rate and the withstand voltage defect rate.

Further, since the layer thickness T1 of the first ceramic layer, the layer thickness T2 of the second ceramic layer, and the layer thickness T3 of the third ceramic layer satisfy T1 <T2, T3, the first ceramic layer It is possible to avoid an increase in the thickness due to the layer thickness T1 as much as possible, and for example, to secure the electrical characteristics such as the acquisition capacitance in the multilayer ceramic capacitor.

The layer thickness T1 of the first ceramic layer satisfies 0 <T1 <1.5 μm. Within this range, it is possible to reduce the short-circuit defect rate and the withstand voltage defect rate due to the sheet attack in the manufacturing process. When the layer thickness T1 of the first ceramic layer is 1.5 μm or more, the short circuit defect rate is reduced but the withstand voltage defect rate is increased. The layer thickness T1 is the thickness of the ceramic coating layer before firing. When fired, it contracts, so that the above-mentioned thickness condition is always satisfied.

2. Method for Manufacturing Ceramic Electronic Component Next, in the method for manufacturing a ceramic electronic component according to the present invention, first, a first ceramic coating layer is formed on the surface of a support, and then the surface of the first ceramic coating layer. Then, an internal electrode is printed, and then a second ceramic paint layer is formed on the surface of the first ceramic paint layer so as to cover the internal electrode.

Next, a third ceramic paint layer is formed on the surface of the second ceramic paint layer so as to cover the internal electrodes thereon, to form a laminated body.

Next, the laminated body is peeled from the support, and a plurality of the laminated bodies obtained by peeling the laminated body are included in one of the adjacent two laminated bodies. The ceramic paint layer is sequentially laminated so as to be adjacent to the third ceramic paint layer included in the other laminated body.

The ceramic average particle size of the first ceramic coating layer is α1, its layer thickness is T1, the ceramic average particle size of the second ceramic coating layer is α2, and the layer thickness is T2. 3 has a ceramic average particle diameter of α3 and a layer thickness of T3, α1 ≦ α2, α3 0.05 <α1 ≦ 0.35 μm, T1 <T2, T3, and 0 <T1 <1. 5 μm is satisfied.

In the manufacturing method according to the present invention, the first ceramic coating layer is formed on the surface of the support, the internal electrodes are printed on the surface of the first ceramic coating layer, and then the first ceramic coating layer is printed. Second, cover the internal electrodes on the surface of the ceramic paint layer.
To form a ceramic paint layer. Next, an internal electrode is printed on the surface of the second ceramic paint layer, and then a third ceramic paint layer is formed on the surface of the second ceramic paint layer so as to cover the internal electrode thereon. Then, a laminated body is formed. Next, the laminate is peeled from the support. For this reason,
It can be handled as a laminated body that is unlikely to cause failure, and structural defects such as delamination, pinholes, and poor withstand voltage due to failure can be avoided as much as possible.

Further, since the first ceramic paint layer is formed on the surface of the support and then the internal electrodes are printed on the surface of the first ceramic paint layer, when the first ceramic paint layer is peeled from the support, the first ceramic paint layer is formed. The peeling surface of the ceramic coating layer and the peeling surface of the internal electrode are flush with each other. Therefore, by using this flat release surface as a laminated surface, structural defects such as delamination due to steps, pinholes, and withstand voltage defects can be avoided.

Moreover, since the first ceramic coating layer is formed on the surface of the support and then the internal electrodes are printed on the surface of the first ceramic coating layer, the release agent is applied on the support. Thus, the first ceramic paint layer can be easily peeled off, and even a very thin first ceramic paint layer of several μm can be surely peeled off from the support without causing breakage. Therefore, structural defects such as delamination, pinholes, and poor withstand voltage due to the breakage of the first ceramic coating layer during peeling can be avoided as much as possible.

Since the internal electrodes are formed on the first ceramic paint layer, unlike the case where the internal electrodes are printed on the surface of the release agent, the shape of the internal electrodes is not destroyed by the surface tension. .

A plurality of the laminates obtained by peeling are
In two adjacent laminated bodies, the first ceramic paint layer included in one laminated body is sequentially laminated in a relationship of adjoining the third ceramic paint layer included in the other laminated body. For this reason, it is very
Since the first ceramic layer having a high packing density is interposed between the internal electrodes, it is possible to reduce the short circuit defect rate and the withstand voltage defect rate.

The ceramic average particle size α1 of the first ceramic coating layer, the ceramic average particle size α2 of the second ceramic coating layer, and the ceramic average particle size α3 of the third ceramic coating layer are α1 ≦ α2. , Α 3 are satisfied, structural defects such as pinholes and defective withstand voltage can be more effectively avoided.

The average ceramic grain size α1 of the first ceramic layer satisfies 0.05 <α1 ≦ 0.35 μm. By satisfying this condition, it is possible to reduce the sheet attack in the manufacturing process and reduce the short-circuit defect rate and the withstand voltage defect rate.

Furthermore, the layer thickness T of the first ceramic coating layer
Since the layer thickness T2 of the first and second ceramic coating layers and the layer thickness T3 of the third ceramic coating layer satisfy T1 <T2 and T3, the thickness increase by the layer thickness T1 of the first ceramic coating layer is By avoiding as much as possible, it is possible to secure the electrical characteristics such as the acquisition capacity of the monolithic ceramic capacitor.

The layer thickness T1 of the first ceramic coating layer satisfies 0 <T1 <1.5 μm. Within this range, it is possible to reduce the short-circuit defect rate and the withstand voltage defect rate due to the sheet attack in the manufacturing process. Short circuit failure and withstand voltage failure will not occur. The layer thickness T1 of the first ceramic coating layer is 1.5μ
It was found that when the length was m or more, the short-circuit defect rate was reduced, but the withstand voltage defect rate was increased. The layer thickness T1 is the thickness of the ceramic coating layer before firing. When fired, the layer thickness T1 contracts, so that the thickness condition described above is always satisfied.

Preferably, the ceramic coating is applied using an extrusion coating head. It is desirable to control the amount of ceramic paint supplied by a mass flow meter and a metering pump. The manufacturing method according to the present invention is particularly suitable for manufacturing a laminated ceramic capacitor.

Other features of the present invention and the effects thereof will be described in more detail with reference to the accompanying drawings. The figures are merely examples.

[0048]

BEST MODE FOR CARRYING OUT THE INVENTION 1. Ceramic Electronic Component FIG. 1 shows a cross-sectional view of a ceramic electronic component according to the present invention embodied as a monolithic ceramic capacitor. Although detailed description is omitted, the present invention can be applied to the manufacture of ceramic electronic components such as piezoelectric elements.

The illustrated monolithic ceramic capacitor is
It includes a ceramic base 1 made of a ceramic dielectric and a plurality of internal electrodes 21 and 22. Each of the internal electrodes 21 and 22 is embedded inside the ceramic substrate 1 with a space therebetween. Since the figure shows a monolithic ceramic capacitor, adjacent internal electrodes 21 and 22 are electrically connected at opposite ends to terminal electrodes 31 and 32 provided at opposite ends of the ceramic substrate 1, respectively. .

FIG. 2 is an enlarged sectional view schematically showing the internal structure of the monolithic ceramic capacitor shown in FIG. For convenience of illustration, the intermediate portion is omitted. The ceramic base 1 includes a first ceramic layer 110, a second ceramic layer 120, and a third ceramic layer 130.

The first ceramic layer 110 is the inner electrode 2
Adjacent to one surface side of 1. The second ceramic layer 120 is
Other internal electrodes 2 that are not adjacent to the first ceramic layer 110
Adjacent to 2.

The third ceramic layer 130 is adjacent to the other surface of another internal electrode 22 adjacent to the second ceramic layer 120.

First and third ceramic layers 110-13
0 and the internal electrodes 21 and 22 are laminated groups C1, C2, ... Having the first ceramic layer 110 as the lowermost layer and the third ceramic layer 130 as the uppermost layer. ． ． Configure Cn.

The laminated groups C1 to Cn are a plurality of n.
The number n of the stacked groups C1 to Cn is arbitrary. Each of the laminated groups C1 to Cn has a first ceramic layer 110.
And the third ceramic layer 130 are laminated so as to be adjacent to each other.

The first ceramic layer 110 and the second and third ceramic layers 120 and 130 are made of the same material, but have different ceramic average particle diameters and thicknesses.
That is, the average ceramic grain size α1 of the first ceramic layer 110, the layer thickness T1, the average ceramic grain size α2 of the second ceramic layer 120, the layer thickness T2, and the average ceramic grain size α3 of the third ceramic layer 130. , The layer thickness T3 satisfies α1 ≦ α2, α3 0.05 <α1 ≦ 0.35 μm, T1 <T2, T3, and 0 <T1 <1.5 μm.

As described above, the ceramic electronic component according to the present invention includes the ceramic base 1 and the plurality of internal electrodes 21 and 22, and each of the internal electrodes 21 and 22 is provided inside the ceramic base 1. Since they are embedded at intervals, it is possible to obtain a ceramic electronic component having a number of laminated layers corresponding to the number of internal electrodes, particularly a laminated ceramic capacitor.

The ceramic substrate 1 includes a first ceramic layer 110, a second ceramic layer 120, and a third ceramic layer 130. First ceramic layer 11
0 is adjacent to one surface side of the internal electrode 21. The second ceramic layer 120 is adjacent to one surface of another internal electrode 22 that is not adjacent to the first ceramic layer 110. In the illustrated embodiment, the second ceramic layer 120 is the first ceramic layer 110.
Is adjacent to the other surface of the adjacent internal electrode 21. The third ceramic layer 130 is adjacent to the other surface of the adjacent internal electrode 22 of the second ceramic layer 120.

First and third ceramic layers 110 to 13
0 and the internal electrodes 21 and 22 form a laminated group C1 to Cn in which the first ceramic layer 110 is the lowermost layer and the third ceramic layer 130 is the uppermost layer.

Therefore, in each of the laminated groups C1 to Cn, a ceramic electronic component having a number of laminated layers depending on the number of laminated layers of the first to third ceramic layers 110 to 130 and the internal electrodes 21 and 22, especially a laminated ceramic. Capacitor can be obtained.

The laminated groups C1 to Cn are a plurality of n,
Each is stacked. Therefore, it is possible to obtain a ceramic electronic component having a number of laminated layers depending on the number of laminated groups, particularly a laminated ceramic capacitor.

Moreover, in each of the laminated groups C1 to Cn, the first ceramic layer 110 and the third ceramic layer 130 are laminated in a relationship of adjoining each other. With this structure, the first ceramic layer 110 that is dense and has a high packing density is interposed between each of the stacked groups C1 to Cn, so that the short-circuit failure rate and the withstand voltage failure rate can be reduced. it can.

The first to third ceramic layers 110 to 13
Ceramic average particle diameters α1 to α3 of 0 satisfy α1 ≦ α2 and α3. According to this configuration, structural defects such as pinholes and defective withstand voltage can be more effectively avoided.

Further, the average ceramic particle size α1 of the first ceramic layer 110 satisfies 0.05 <α1 ≦ 0.35 μm. By satisfying this condition, it is possible to reduce the sheet attack in the manufacturing process and reduce the short-circuit defect rate and the withstand voltage defect rate.

Further, the first to third ceramic layers 110
And the layer thicknesses T1 to T3 of the above satisfy T1 <T2 and T3. According to this condition, the first ceramic layer 11
An increase in thickness due to the layer thickness T1 of 0 can be avoided as much as possible, and for example, electrical characteristics such as the acquisition capacitance of the laminated ceramic capacitor can be secured.

The layer thickness T1 of the first ceramic layer 110 satisfies 0 <T1 <1.5 μm. Within this range, it is possible to reduce the short-circuit defect rate and the withstand voltage defect rate due to the sheet attack in the manufacturing process. Short circuit failure and withstand voltage failure will not occur. The layer thickness T1 of the first ceramic layer 110 is 1.5
It has been found that when the thickness is more than μm, the short-circuit failure rate decreases, but the withstand voltage failure rate increases. The layer thickness T1 is the thickness of the ceramic coating layer before firing. When fired, the layer thickness T1 contracts, so that the thickness condition described above is always satisfied.

FIG. 3 is an enlarged sectional view schematically showing another internal structure of the monolithic ceramic capacitor shown in FIG.
In the figure, the same components as those shown in FIGS. 1 and 2 are designated by the same reference numerals. The feature of the embodiment is that the second ceramic layer 120 and the internal electrode 2 are
That is, the combination of 1 or 22 is plural.
In the illustrated embodiment, the number of combinations of the second ceramic layer 120 and the internal electrodes 22 and 21 is two, but the number can be further increased. Also in the case of the embodiment shown in FIG. 3, the same effect as that of the embodiment shown in FIG. 2 can be obtained.

2. Method for Manufacturing Ceramic Electronic Component Next, a method for manufacturing a ceramic electronic component according to the present invention will be described with reference to FIGS.

First, as shown in FIGS. 4 to 6, the coating device 5 is used to apply a ceramic coating on the surface of the support 6 to form a first ceramic coating layer having a layer thickness T1 (see FIG. 6). 110 is formed.

The layer thickness T1 is formed so as to satisfy 0 <T1 <1.5 μm. Layer thickness T1 of the first ceramic layer 110
Is 1.5 μm or more, the short-circuit failure rate is reduced, but the withstand voltage failure rate is increased.

The support 6 is made of a flexible organic resin film, specifically polyethylene. Terephthalate. A film (PET film) is used.

The support 6 is made up of the first ceramic coating layer 11
Considering the peeling of 0, it is preferable to subject the ceramic coating layer molding surface to a peeling treatment. The peeling treatment can be performed by thinly coating one surface of the support 6 with a peeling film made of Si or the like. By performing such a peeling treatment, the first ceramic coating layer 110 formed on the support 6 can be easily peeled from the support 6.

As the ceramic paint, a paint prepared by mixing an organic binder such as an acrylic resin or a butyral resin, an organic solvent, a plasticizer and ceramic powder can be used.

The average particle size α1 of the ceramic particles contained in the ceramic paint for forming the first ceramic paint layer 110 is in the range of 0.05 μm <α1 ≦ 0.35 μm.

If the average particle size α1 is smaller than 0.05 μm, the dispersibility of the ceramic paint when making the ceramic paint is deteriorated, and it becomes impossible to form a uniform ceramic paint layer.

The average particle size α1 of the ceramic particles forming the first ceramic layer 110 further satisfies α1 ≦ 0.35 μm. Within such a range, short circuit defects and withstand voltage defects can be reduced, and the average ceramic particle size α1 is 0.35.
It has been found that when the thickness exceeds μm, short circuit failure and withstand voltage failure easily occur. This means that there is a critical point where the influence of the sheet attack can be reduced in the vicinity of the average ceramic particle size α1 of 0.35 μm. Average particle size α
It can be seen that 1 and α2 are almost constant before and after firing.

In forming the first ceramic coating layer 110 by coating, an extrusion type coating head, a doctor blade method, a reverse roll method or the like can be used as the coating device 5. Of these, the extrusion coating head is particularly preferable.

The illustrated embodiment shows an example in which an extrusion type coating head is used as the coating device 5. When the coating device 5 including the extrusion coating head is used, it is possible to obtain a uniform first ceramic coating layer 110 with very good surface accuracy and less variation in thickness.

The extrusion type coating head 5 shown in the figure has a slit 51 for discharging ceramic paint, an upstream nozzle 52,
A downstream nozzle 53, a ceramic paint pool 54, a supply port 55 to the ceramic paint 54 pool, and the like are provided. Such extrusion type coating head is known. In FIG. 4, reference numeral F1 indicates the traveling direction of the support 6.

When a ceramic electronic component such as a monolithic ceramic capacitor or a piezoelectric element is obtained, either one of a dielectric ceramic material or a piezoelectric ceramic material is used as the ceramic powder.

Next, after passing through necessary steps such as a drying step for drying the first ceramic coating layer 110, as shown in FIGS. 7 and 8, the first ceramic coating layer 110 is formed.
The internal electrodes 21 and 22 are printed on the surface of the. Internal electrode 2
As the internal electrode pastes for Nos. 1 and 22, those conventionally known can be used. Specifically, using a vehicle in which an organic binder is dissolved in an organic solvent,
It is prepared by dispersing a conductive metal powder such as Ag, Pd, Ni or Cu in this vehicle and adding a viscosity adjusting diluent in some cases. As the organic solvent in the vehicle, terpione, methyl etiketone, or the like is used, and as the binder, a cellulose resin such as ethyl cellulose or nitrocellulose, or an acrylic resin such as butyl methacrylate or methyl methacrylate is used. Further, as the diluent, aromatic hydrocarbon, fatty acid hydrocarbon or the like is used.

In the case of the present invention, even if the internal electrodes 21 and 22 are formed by applying the internal electrode paste having the above-mentioned composition to the first ceramic coating layer 110, the first ceramic coating layer 110 still has the internal electrode paste. Less susceptible to sheet attack by organic solvents such as terpione and methyl etiketone contained in. This is because the average particle size α1 of the ceramic particles contained in the ceramic paint for forming the first ceramic paint layer 110 is set in the range of 0.05 μm <α1 ≦ 0.35 μm, so that the sheet attack is blocked. It is supposed to be because.

Therefore, according to the present invention, it is not difficult to separate the first ceramic coating layer 110 from the support, and no holes or wrinkles are formed in the first ceramic coating layer 110. . Therefore, short circuit failure and withstand voltage failure can be avoided and a predetermined capacitance can be secured.

The internal electrodes 21, 22 are formed as a group of patterns. The internal electrodes 21, 22 are, for example, 30 cm
It can be formed in a pattern such that thousands are regularly arranged in the regions GR1 to GR3 (see FIG. 6) of x30 cm. As the printing means, not only ordinary screen printing but also gravure printing or the like can be applied.

As described above, since the internal electrodes 21 and 22 are formed on the first ceramic paint layer 110, unlike the case where the internal electrodes 21 and 22 are printed on the surface of the release agent, the internal electrodes 21 and 22 are different. , 22 shape does not collapse due to the surface tension.

Next, after the internal electrode drying step and the like, FIG.
0 and FIG. 11, the first ceramic paint layer 1
The second electrode on the surface of 10 so as to cover the internal electrodes 21 and 22.
The ceramic coating layer 120 is formed. The second ceramic coating layer 120 can also be formed by using the coating device 5 with an extrusion coating head.

The composition of the ceramic coating material forming the second ceramic coating material layer 120 may be the same as or different from that of the ceramic coating material forming the first ceramic coating material layer 110.

The average particle size α of the ceramic particles contained in the ceramic paint which constitutes the second ceramic paint layer 120.
2 is the average particle size α of the ceramic particles contained in the ceramic paint for forming the first ceramic paint layer 110.
1 is selected so as to satisfy α1 ≦ α2.

By satisfying the condition α1 ≦ α2, it is possible to form the first ceramic paint layer 110 which is dense and has a high packing density, and to avoid structural defects such as pinholes and defective withstand voltage as much as possible.

As described above, the average particle size α1 of the first ceramic coating layer 110 is selected to be 0.05 μm or less. The viewpoint of blocking the sheet attack and the pinhole A1 generated in the second ceramic paint layer 120 is filled with the ceramic particles b1 having a small average particle size α1 that compose the first ceramic paint layer 110 to improve the withstand voltage. From the viewpoint of making it possible, it is better that the average particle size α1 is smaller, but if the average particle size α1 is smaller than 0.05 μm, the dispersibility at the time of producing the ceramic paint is deteriorated and the uniform ceramic paint is obtained. The layer cannot be formed.

The second ceramic paint layer 120 is formed so that its layer thickness T2 satisfies T1 <T2 with respect to the layer thickness T1 of the first ceramic paint layer 110. By satisfying this relationship, the layer thickness T1 of the first ceramic coating layer 110 is limited, and the thickness increase due to the layer thickness T1 of the first ceramic coating layer 110 is avoided as much as possible. It is possible to avoid an increase in thickness as much as possible, and to secure electrical characteristics such as acquisition capacity.

Next, after performing necessary steps such as a drying step for drying the second ceramic coating layer 120, as shown in FIG.
2, as shown in FIG. 13, the second ceramic paint layer 12
The internal electrodes 21 and 22 are printed on the surface of 0. As the internal electrode paste for the internal electrodes 21 and 22, the one exemplified above is used. FIG. 13 shows the first ceramic paint layer 11
FIG. 12 is an enlarged cross-sectional view taken on the internal electrode 21 of the two internal electrodes 21 and 22 (see FIGS. 10 and 11) formed in 0. The same notation is used in the following drawings.

Next, after the internal electrode drying step and the like, FIG.
As shown in FIG. 4, the third ceramic paint layer 130 is formed on the surface of the second ceramic paint layer 120 so as to cover the internal electrodes 21 and 22. Third ceramic paint layer 1
The ceramic paint that constitutes 30 may be the same as or different from the ceramic paint for the first and second ceramic paint layers 110, 120.

As shown in FIG. 3, when there are a plurality of combinations of the second ceramic layer and the internal electrodes, before forming the third ceramic coating layer 130, the second ceramic coating layer 120 and the internal electrode are formed. The combination of the electrodes 22 (or 21) is formed multiple times. In practice, it is preferable that the second ceramic coating layer 120 has about 2 to 3 layers from the viewpoint of eliminating steps.

The average particle diameter α of the ceramic particles contained in the ceramic coating material forming the third ceramic coating layer 130.
3 is the average particle size α of the ceramic particles contained in the ceramic paint for forming the first ceramic paint layer 110.
1 is selected so as to satisfy α1 ≦ α3. The average particle size α3 may be the same as or different from the average particle size α2 of the ceramic paint contained in the second ceramic paint layer 120.

The third ceramic coating layer 130 is formed so that its layer thickness T3 satisfies T1 <T3 with respect to the layer thickness T1 of the first ceramic coating layer 110. The layer thickness T3 may be the same as or different from the layer thickness T2 of the second ceramic paint layer 120.

In the relationship of the third ceramic coating layer 130 to the first ceramic coating layer 110, the conditions that the average grain size α3 should satisfy for the average grain size α1 and the layer thickness T3 for the layer thickness T1 are set. The conditions to be satisfied are the average particle size of the second ceramic coating layer 120, the average particle size α2, and the layer thickness T.
It is set for the same purpose as the condition 2 to be satisfied.

Next, after passing through necessary steps such as a drying step,
A laminated body, which is a combination of the first ceramic coating layer 110, the internal electrode 21, the second ceramic coating layer 120, the internal electrode 22, and the third ceramic coating layer 130, is set as a set and is peeled from the support 6. To do. FIG. 15 shows the laminated body after peeling. Although illustration is omitted, the internal electrode 22 is also present on the formation surface of the internal electrode 21 (see FIG. 7).
The internal electrode 21 is also present on the surface on which the internal electrode 22 is formed (see FIG. 12).

Here, the first ceramic coating layer 110,
A set of laminated bodies that are a combination of the internal electrode 21, the second ceramic coating layer 120, the internal electrode 22, and the third ceramic coating layer 130 is taken as a set, and this is used as the support 6 (FIG. 14).
Since it can be peeled off, it can be handled as a laminated body that is unlikely to cause failure and the like, and structural defects such as delamination, pinholes and withstand voltage failure due to failure can be avoided as much as possible.

Further, the first ceramic paint layer 110 is formed on the surface of the support, and then the first ceramic paint layer 1 is formed.
Since the internal electrodes 21 and 22 are printed on the surface of 10, the first ceramic paint layer 11 when peeled from the support 6
The peeling surface of 0 and the peeling surfaces of the internal electrodes 21 and 22 are flush with each other.

Next, as shown in FIG. 16, the punched laminated body is punched for each of the regions GR1 to GR3 in FIG.
A necessary combination on the pedestal 7 as a set of laminated bodies which are a combination of the first ceramic coating layer 110, the internal electrode 21, the second ceramic coating layer 120, the internal electrode 22 and the third ceramic coating layer 130. The number of layers is sequentially laminated.
When laminating each set, in the laminated body of the adjacent set, the first ceramic coating layer 110 and the third ceramic coating layer 130 are sequentially laminated in such a relationship that they are adjacent to each other.

The laminate obtained as described above is shown in FIG.
As shown in FIG. 6, a press 8 is used for thermocompression bonding.

Here, the peeling surface of the first ceramic paint layer 110 and the peeling surfaces of the internal electrodes 21, 22 are flush with each other. Therefore, by using this flat release surface as a laminated surface, structural defects such as delamination due to steps, pinholes, and withstand voltage defects can be avoided.

Then, by cutting, a laminated green chip is obtained. The obtained laminated green chip,
After the binder removal treatment is performed under a predetermined temperature condition, the binder is fired, and the terminal electrode is baked and formed.

The conditions for binder removal and firing are well known in the art. For example, the binder is removed at 280 ° C. for 12 hours, and firing is performed at 1300 ° C. for 2 hours in a reducing atmosphere. The terminal electrodes 31 and 32 are formed on the laminated body obtained after firing. The materials and forming methods of the terminal electrodes 31, 32 are also well known in the art. For example, copper as the main component and 80 in N2 + H2
Baking is performed at 0 ° C. for 30 minutes to perform plating.

Next, the effects of the ceramic electronic component according to the present invention will be described with reference to experimental data.

According to the manufacturing method of the present invention, a monolithic ceramic capacitor having a length × width of 3.2 × 2.5 (mm) and a number of laminated layers of 100 was manufactured. In manufacturing, different thicknesses T1 to T3 of the first to third ceramic coating layers 110 to 130 and further changing the average particle diameters α1 to α3 of the ceramic coating within the scope of the present invention to obtain different laminated ceramic capacitor samples. Was manufactured. The samples of the obtained monolithic ceramic capacitors are referred to as Examples 1 to 4.

On the other hand, the first to third ceramic coating layers 1
Samples of different monolithic ceramic capacitors were produced by varying the thicknesses T1 to T3 of 10 to 130 and further the average particle diameters α1 to α3 of the ceramic paint outside the scope of the present invention.
The obtained multilayer ceramic capacitor samples are referred to as Comparative Examples 1 to 3. In addition, a sample according to an application example of a conventional general manufacturing method in which a ceramic coating layer is applied on a support and internal electrodes are formed thereon is referred to as Comparative Example 4.

Examples 1 to 4 described above and Comparative Examples 1 to 1
For 4, the short circuit failure rate and the withstand voltage failure rate were measured.
The withstand voltage defect rate was measured by applying a DC voltage of 50V.
The number N of samples used in the experiment is 100 in each of the examples and the comparative examples.

Regarding Examples 1 to 4 and Comparative Examples 1 to 4,
The obtained measurement results of the short-circuit failure rate and the withstand voltage failure rate are shown as the thicknesses T1 and T2 of the ceramic coating layer and the average particle sizes α1 and α2.
Is also shown.

As shown in Table 1, in the comparative example 4 of the conventional product in which the ceramic coating layer was applied on the support and the internal electrodes were formed thereon, the short circuit failure rate was 40 in the conventional product. The withstand voltage failure rate reaches as high as 17%, which is a high value of 17%.

It has a first ceramic coating layer and a second ceramic coating layer, and the thicknesses T1 and T2 and the average particle diameters α1 and α2 of the ceramic particles are specified by the present invention, that is, α1 ≦ α2, In Comparative Examples 1 to 3 which do not satisfy any of 0.05 <α1 ≦ 0.35 μm, and T1 <T2, 0 <T1 <1.5 μm, the short circuit failure rate is in the range of 13% to 47%. , Withstand voltage failure rate is also 9-2
It shows a high value of 1 (%).

On the other hand, in Examples 1 to 4 according to the present invention satisfying the above relationships, the short-circuit defect rate was within the range of 1 to 6 (%), and the withstand voltage defect rate was 1 to 5 (%). It falls within the range of, and shows a remarkable superiority in comparison with Comparative Examples 1 to 4.

[0113]

As described above, according to the present invention, the following effects can be obtained. (A) It is possible to provide a ceramic electronic component in which structural defects such as a short circuit defect and a withstand voltage defect are less likely to occur, particularly a laminated ceramic capacitor. (B) It is possible to provide a method for manufacturing a ceramic electronic component with high accuracy and high reliability, which can significantly reduce the probability of causing peeling difficulty and defective properties of products even if the ceramic coating layer is thin. (C) It is possible to provide a method for manufacturing a ceramic electronic component in which the step difference between the layers due to the electrodes is significantly reduced and the reliability is improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a ceramic electronic component (multilayer ceramic capacitor) according to the present invention.

FIG. 2 is a diagram schematically showing an internal structure of the ceramic electronic component shown in FIG.

3 is a diagram schematically showing another embodiment of the internal structure of the ceramic electronic component shown in FIG.

FIG. 4 is a diagram showing a method for manufacturing a ceramic electronic component according to the present invention.

5 is a diagram showing a first ceramic paint layer obtained by the manufacturing process shown in FIG. 4. FIG.

6 is a cross-sectional view schematically showing the structure of the first ceramic paint layer shown in FIG.

FIG. 7 is a diagram showing a step that follows the step shown in FIG.

8 is a cross-sectional view schematically showing the structure of a first ceramic coating layer and internal electrodes after undergoing the process shown in FIG.

9 is a diagram showing a step that follows the step shown in FIGS. 7 and 8. FIG.

FIG. 10 is a diagram showing a second ceramic coating layer obtained by the manufacturing process shown in FIG. 9.

FIG. 11 is a second view obtained by the manufacturing process shown in FIG.
It is a figure which shows the ceramic coating layer.

12 is a diagram showing a step that follows the step shown in FIG.

FIG. 13 is a diagram showing a step that follows the step shown in FIG.

FIG. 14 is a diagram showing a step that follows the step shown in FIG.

FIG. 15 is a diagram showing a laminated body obtained through the steps shown in FIG.

16 is a diagram showing a step that follows the step shown in FIG.

[Explanation of symbols]

21, 22 internal electrode 110 first ceramic layer or first ceramic coating layer 120 second ceramic layer or second ceramic coating layer 130 third ceramic layer or third ceramic coating layer

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yasushi Izumibe             1-13-1, Nihonbashi, Chuo-ku, Tokyo             -In DC Inc. (72) Inventor Kazushi Ishida             1-13-1, Nihonbashi, Chuo-ku, Tokyo             -In DC Inc. (72) Inventor Akira Saito             1-13-1, Nihonbashi, Chuo-ku, Tokyo             -In DC Inc. F-term (reference) 5E082 AB03 BC35 BC36 EE04 EE35                       FF15 FG04 FG06 FG26 FG46                       PP09

Claims (5)

[Claims] 1. A ceramic electronic component including a ceramic base and a plurality of internal electrodes, wherein each of the internal electrodes is embedded inside the ceramic base at a distance, and the ceramic base is A first ceramic layer, a second ceramic layer, and a third ceramic layer are included, the first ceramic layer is adjacent to one surface side of the internal electrode, and the second ceramic layer is provided. The layer is adjacent to one surface of another internal electrode that is not adjacent to the first ceramic layer, and the third ceramic layer is adjacent to another surface of the other internal electrode of the second ceramic layer. Adjacent to each other, the first and third ceramic layers and the internal electrode form a laminated group in which the first ceramic layer is the lowermost layer and the third ceramic layer is the uppermost layer. Oh And the first ceramic layer and the third ceramic layer are laminated so as to be adjacent to each other, and the average ceramic grain size of the first ceramic layer is α1. , The layer thickness is T1, the ceramic average particle size of the second ceramic layer is α2, the layer thickness is T2, the ceramic average particle size of the third ceramic layer is α3, and the layer thickness is T3. At this time, a ceramic electronic component satisfying α1 ≦ α2, α3 0.05 <α1 ≦ 0.35 μm, T1 <T2, T3, and 0 <T1 <1.5 μm. 2. The ceramic electronic component according to claim 1, wherein there are a plurality of combinations of the second ceramic layer and the other internal electrodes. 3. The ceramic electronic component according to claim 1, which is a monolithic ceramic capacitor. 4. A method of manufacturing a ceramic electronic component, comprising forming a first ceramic coating layer on the surface of a support, and then printing an internal electrode on the surface of the first ceramic coating layer, Next, a second ceramic paint layer is formed on the surface of the first ceramic paint layer so as to cover the internal electrodes, and then an internal electrode is printed on the surface of the second ceramic paint layer. Then, a third ceramic paint layer is formed on the surface of the second ceramic paint layer so as to cover the internal electrodes thereon, to form a laminated body, and then the support body is formed. In the two adjacent laminated bodies, the first ceramic coating material layer included in one laminated body is the other laminated body in which two or more laminated bodies obtained by peeling the laminated body from each other are separated. Adjacent to the third ceramic coating layer included in The step of sequentially laminating the first ceramic coating material layer with the average ceramic particle size of α
1, the layer thickness is T1, the ceramic average particle size of the second ceramic coating layer is α2, the layer thickness is T2, the ceramic average particle size of the third ceramic coating layer is α3, and the layer thickness is Is T3, α1 ≦ α2, α3 0.05 <α1 ≦ 0.35 μm, T1 <T2, T3, and 0 <T1 <1.5 μm. 5. The manufacturing method according to claim 4, wherein the laminated ceramic capacitor is manufactured.