JP2003259237A - Random trigger shutter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce exposure for a long time and dark noise and to prevent a smear. <P>SOLUTION: A VD counter 26 starts to count vertical synchronous pulses VD when a trigger pulse Trig is inputted, and an HD counter 28 counts horizontal synchronous pulses HD at each cycle of the vertical synchronous pulses VD. VD comparators 30, 32 and 34 compare a count value of the VD counter 26 with values of the VD position data of a charge read pulse SG, a charge sweeping out pulse SUB and a fast drive pulse Vdrf, respectively, while HD comparators 36, 38 and 40 compare a count value of the HD counter 28 with the values of the HD position data of the respective pulses SG, SUB and Vdrf, respectively to determine the timing of each of the pulses. Since the vertical synchronous pulses VD are also counted, a long time of exposure is available. Since timing can be flexibly set, dark noise can be reduced, and a smear can be prevented by interlocking with a mechanical shutter. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a random trigger shutter circuit that controls exposure in a solid-state image sensor.

[0002]

2. Description of the Related Art Solid-state image pickup devices are widely used as image pickup means for video cameras and electronic still cameras. Figure 6
FIG. 3 is a schematic plan view showing an example of this type of solid-state imaging device. The conventional solid-state image sensor 102 shown in FIG. 6 is a CCD.
It is a solid-state image sensor of interline transfer type having a structure, and includes a large number of photosensors 106 (photodiodes) provided on a semiconductor substrate 104, a vertical charge transfer register 108, a horizontal charge transfer register 110, and the like. The photosensors 106 are arranged in a matrix, and the vertical charge transfer registers 108 are provided along the columns of the photosensors 106 for each column of the photosensors 106. The horizontal charge transfer register 110 is provided on one end side of the vertical charge transfer register 108 so as to be orthogonal to the vertical charge transfer register 108, that is, in the direction of the row of the photosensor 106, and the charge-voltage conversion is performed at the output end thereof. Floating diffusion unit 112
The (FD unit 112) is provided. The image signal generated by the FD unit 112 is output to the outside of the solid-state image sensor 102 through the output circuit 114 with low impedance.

On the charge transfer paths of the vertical charge transfer register 108 and the horizontal charge transfer register 110, transfer electrodes (not shown) composed of pairs of transfer electrodes and storage electrodes are arranged in the charge transfer direction in each transfer register. By applying a drive pulse to these electrodes, the signal charges are transferred on the transfer register.

In this example, the signal charges received by the photosensors 106 are generated by applying a charge read pulse to the transfer electrodes of the vertical charge transfer register 108.
For each column of the photosensors 106, the data is simultaneously read to the vertical charge transfer registers 108 through a read gate unit (not shown) between the vertical charge transfer registers 108 and the photosensors 106. Then, by driving the vertical charge transfer register 108 by applying a drive pulse to the transfer electrode, the signal charges read from the photosensor 106 are directed to the horizontal charge transfer register 110 on the vertical charge transfer register 108. The light sensor 106 is sequentially transferred.
Horizontal charge transfer register 11 for each signal charge of one row
Supplied to zero.

The signal charges for one row of the photosensors supplied to the horizontal charge transfer register 110 are sequentially driven toward the FD section 112 on the horizontal charge transfer register 110 by driving the horizontal charge transfer register 110 with a driving pulse. F is transferred from the end of the horizontal charge transfer register 110.
It is output to the D section 112. The signal charge is converted into a voltage in the FD section 112, and is output from the output circuit 114 as an image signal to the outside with low impedance.

The charge read pulse is supplied to the vertical charge transfer register 108 in synchronization with the vertical sync pulse.
Then, the signal charge transfer in the vertical charge transfer register 108 is started in synchronization with the vertical sync pulse. The vertical sync pulse is generated for every predetermined number of horizontal sync pulses, and the drive pulse applied to the transfer electrode of the vertical charge transfer register 108 is a pulse of, for example, four phases having the same period as the horizontal sync pulse.

The exposure control by the electronic shutter in the solid-state imaging device 102 is performed by applying a charge sweeping pulse to the substrate 104 and discarding the signal charges accumulated in the optical sensor 106. The charge sweep pulse is applied at the time when a set time elapses from the vertical sync pulse in each cycle of the vertical sync pulse, and the time from the timing until the charge read pulse is supplied is the exposure time of the optical sensor 106. Becomes Then, during this time, the signal charge accumulated in the photosensor 106 moves to the vertical charge transfer register 108 side by applying the charge read pulse to the transfer electrode of the vertical charge transfer register 108 in synchronization with the vertical synchronization pulse.

The charge sweep pulse is normally applied to the substrate 104 at each timing of each horizontal synchronizing pulse, and the supply of the charge sweep pulse is stopped at the time of exposure, so that the signal charge is not accumulated in the optical sensor 106. Be started. Therefore, the exposure start timing of the photosensor 106 is determined by the last applied charge sweep pulse.

On the other hand, when the exposure using the electronic shutter is performed by the random trigger, the solid-state image pickup device 102 is controlled as follows. FIG. 7 is a timing chart showing the control when the exposure using the electronic shutter is performed by a random trigger. As shown in FIG. 7, in a normal state before the trigger pulse Trig is input, for example, a four-phase drive pulse Vdrv (only one drive pulse is shown for simplicity in the figure is synchronized with a horizontal sync pulse (not shown). (Shown), and a charge read pulse SG synchronized with the vertical sync pulse VD having a constant period is supplied to the vertical charge transfer register 108. A charge sweep pulse SUB is applied to the substrate 104 in synchronization with a horizontal sync pulse (not shown).

When the trigger pulse Trig is input at the timing Tt, the period Td starts from the timing of the horizontal synchronizing pulse immediately after the falling timing of the trigger pulse Trig, that is, the timing of the driving pulse Vdr and the charge sweeping-out pulse SUB. During this period, a drive pulse having a cycle shorter than usual is supplied to the vertical charge transfer register 108 as a high speed drive pulse Vdrf, and unnecessary charges accumulated in the vertical charge transfer register 108 are transferred and discarded.

On the other hand, in order to set the exposure time, the last charge sweep-out pulse SUB is applied to the substrate at the timing Ts when a predetermined number of horizontal synchronizing pulses are generated, and thereafter, the signal charge is accumulated in the photosensor 106. Then, the exposure time T
When e has elapsed, the charge read pulse SG is supplied to the vertical charge transfer register 108, and the optical sensor 10
The signal charge accumulated in 6 is the vertical charge transfer register 108.
Read to the side. And the vertical charge transfer register 1
The signal charge taken in 08 is transferred by the vertical charge transfer register 108 in the signal output period To after the next vertical synchronizing pulse is generated, and further transferred by the horizontal charge transfer register 110 to be an image signal from the solid-state image sensor 102. Is output.

In normal operation, a charge read pulse is always generated immediately after each vertical sync pulse VD. However, in exposure control by a random trigger, the first normal charge read pulse SG after the exposure is finished. , Fig. 7
As shown by the dotted line in FIG.
Is blocked. Accordingly, as a result of the exposure by the random trigger, the vertical charge transfer register 108 is already generated.
The signal charge read in is transferred as it is in the next cycle of the vertical charge transfer register 108.

[0013]

By the way, in such exposure control of the conventional solid-state image pickup device 102, the trigger pulse Trig is input to set the timing of supplying the last charge sweeping-out pulse or the charge reading pulse. After that, the horizontal synchronizing pulse is counted by a counter. Therefore, it is difficult to control the long-time exposure in which the exposure time extends over a plurality of periods of the vertical synchronizing pulse, and the low-speed shutter function by the random trigger has not been realized.

Further, in the conventional exposure control by the random trigger, as shown in FIG. 7, after the exposure is completed and the charge read pulse SG is applied, the vertical charge is generated until the next vertical synchronizing pulse VD is generated. The drive pulse is not supplied to the transfer register 108, and the vertical charge transfer register 1
08 is in a stopped state. However, dark noise occurs when the vertical charge transfer register 108 stops, and dark noise increases as the stop time of the vertical charge transfer register 108 increases.

Further, in the conventional exposure control, the timing of starting the supply of the high speed drive pulse Vdrf is always the timing of the horizontal synchronizing pulse immediately after the trigger pulse Trig is supplied, and the trigger pulse Tri
The timing of g cannot be set arbitrarily. Even during the period in which the vertical charge transfer register 108 is being driven at high speed, the photosensor 106 is exposed after the last charge sweeping-out pulse SUB, which causes a smear. A mechanical shutter is used to prevent smearing, and the optical sensor 10 is used during high-speed driving.
It is effective to prevent 6 from being exposed, but since the timing of the high-speed drive pulse Vdrf is fixed as described above, it has been difficult to use a mechanical shutter together in the past.

The present invention has been made to solve such a problem, and an object thereof is to flexibly perform exposure control by a random trigger and enable long-time exposure over a plurality of periods of vertical synchronizing pulses. Another object of the present invention is to provide a random trigger shutter circuit for a solid-state image sensor that can reduce dark noise and prevent smear.

[0017]

In order to achieve the above-mentioned object, the present invention provides a solid-state image pickup device for picking up an image of a subject by a plurality of optical sensors and outputting an image signal representing the image pickup result in synchronization with a first synchronizing pulse. On the other hand, when a trigger pulse is input, the signal sweeping pulse that sweeps away the signal charge accumulated in the photosensor to determine the timing of starting the exposure of the photosensor and the signal charge accumulated in the photosensor are signaled. A random trigger shutter circuit that supplies a charge read pulse to be read to a charge transfer unit and a high-speed drive pulse that drives the transfer unit and rapidly transfers and discards the signal charge held by the transfer unit, A first for measuring the time by counting the first synchronization pulse;
And a second timing means for measuring the time by counting a second synchronizing pulse having a shorter cycle than the first synchronizing pulse, and data for timing of the charge sweeping pulse, and the trigger. Generation of a charge sweep pulse for supplying the charge sweep pulse to the solid-state image pickup device at a timing corresponding to the timing data based on a result of time measurement by the first and second timing means when a pulse is input. Means and data relating to the timing of the high-speed drive pulse, and when the trigger pulse is input, based on the measurement results of the time by the first and second timing means, at a timing corresponding to the timing data. High-speed drive pulse generating means for supplying the high-speed drive pulse to a solid-state imaging device, and the charge reading Then, the charge read pulse is received at the timing corresponding to the timing data based on the measurement result of the time by the first and second timing means when the trigger pulse is input. And a charge read pulse generating means for supplying to the solid-state image pickup device.

In the random trigger shutter circuit of the present invention, the charge sweep-out pulse generating means receives data relating to the timing of the charge sweep-out pulse, and when the trigger pulse is input, the time by the first and second timing means is set. Based on the measurement result of 1), the electric charge sweep pulse is supplied to the solid-state image sensor at the timing corresponding to the timing data. Further, the high speed drive pulse generating means receives the data relating to the timing of the high speed drive pulse, and responds to the timing data based on the measurement results of the time by the first and second time measuring means when the trigger pulse is input. A high-speed drive pulse is supplied to the solid-state image sensor at the timing. Then, the charge read pulse generating means receives the data relating to the timing of the charge read pulse, and responds to the timing data based on the result of the time measurement by the first and second time measuring means when the trigger pulse is input. A charge read pulse is supplied to the solid-state image sensor at a timing.

As described above, in the present invention, the charge sweeping pulse, the high speed driving pulse, and the high speed driving pulse are provided by using the first and second timing means for counting the first and second synchronizing pulses, respectively.
Also, since the timing of the charge read pulse is set, the timing of each pulse can be set not only in the cycle unit of the second synchronization pulse but also in the cycle unit of the first synchronization pulse. Therefore, the exposure time of the optical sensor can be flexibly controlled in a wide range from short time to long time, and further, the timing of supplying each pulse after the trigger pulse is input can be set variously.

As a result, in the present invention, it is possible to perform long-time exposure over a plurality of cycles of the first synchronizing pulse. Further, after the trigger pulse is input, each pulse is supplied to the solid-state image sensor with a time, and the charge read pulse is supplied in the vicinity of the subsequent first synchronization pulse to reduce dark noise. be able to. Further, when the mechanical shutter is used, it is possible to prevent the smear from occurring by supplying the high speed drive pulse and the charge read pulse after the mechanical shutter is closed.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an example of a random trigger shutter circuit according to the present invention, and FIG. 2 is a block diagram showing an entire solid-state imaging device including the random trigger shutter circuit of FIG. Also, FIG.
Is a timing chart showing the operation of the random trigger shutter circuit of the embodiment, FIG. 4 is a timing chart showing the operation of the random trigger shutter circuit of the embodiment at the time of long-time exposure, and FIG. 7 is a timing chart showing an operation of the random trigger shutter circuit of the exemplary embodiment in the case.

First, the entire solid-state image pickup device will be described with reference to FIG. The solid-state imaging device 2 shown in FIG.
CD solid-state image sensor 102 (FIG. 6), CDS / AD
It is configured to include a C circuit 4, a signal processing circuit 6, a timing generation circuit 8 and a microcomputer 10. The timing generation circuit 8 is controlled by the microcomputer 10 and includes a crystal oscillator 12 (VCO).
In order to control the exposure and charge transfer of the solid-state image pickup device 102 based on the reference clock pulse 14 from, the four-phase vertical drive pulse Vdr, the charge read-out pulse SG, and the charge sweep-out pulse SUB are supplied to the solid-state image pickup device 102. Further, two-phase drive pulses H1 and H2 applied to the transfer electrodes of the horizontal charge transfer register 110 are supplied. The timing generation circuit 8 also supplies a timing signal as described below to each unit.

CDS (Correlated Double Sampling) /
The ADC circuit 4 receives the timing signals XSHP and XSHD related to sampling and the like from the timing generation circuit 8 and removes the offset component from the image signal output by the solid-state image sensor 102, thereby eliminating noise due to offset variation. Then, the image signal from which the noise is removed is digitized and output to the signal processing circuit 6. Under the control of the microcomputer 10, the signal processing circuit 6 receives the vertical synchronizing pulse VD from the timing generating circuit 8,
Based on the horizontal synchronizing pulse HD, the image signal from the CDS / ADC circuit 4 is subjected to automatic exposure control and automatic white balance control, and output as a video signal 16.

The random trigger shutter circuit of the embodiment forms the timing generating circuit 8, and is specifically constructed as shown in FIG. That is, the random trigger shutter circuit 18 includes a trigger control block 19, an HD counter 20, and a drive pulse generation circuit 22.

The trigger control block 19 includes a trigger mode controller 24 and a VD counter 26.
(First Clocking Means According to the Present Invention), HD Counter 28
(Second timing means according to the present invention), and further VD
Includes comparators 30, 32, 34 and HD comparators 36, 38, 40.

The trigger mode controller 24 uses the trigger pulse Tri based on the operation of the operator, for example.
When g is generated and input, it immediately enters the trigger mode at the falling edge of the next horizontal sync pulse HD,
After the count values are cleared by the VD counter 26 and the HD counter 28, the count operation is started, and
At the same time, each comparator has a microcomputer 10
The data supplied from (Fig. 2) is loaded.

The VD counter 26 counts the vertical synchronizing pulse VD under the control of the trigger mode controller 24, and counts the count value to VD comparators 30, 32, and 3.
Output to 4. Further, the HD counter 28 counts the horizontal synchronizing pulse HD under the control of the trigger mode controller 24 and counts the count value with the HD comparator 36,
Output to 38 and 40. The HD counter 28 receives the signal from the VD counter 26, and clears the count value each time the VD counter 26 increments the count value by one, and thus every vertical sync pulse VD, and recounts the horizontal sync pulse HD from 0.

In the VD comparators 30, 32, and 34, the microcomputer 10 is used to set V for setting the timing of the charge read pulse SG, the charge sweep-out pulse SUB, and the high speed drive pulse Vdrf.
D position data is supplied, and each VD comparator, under the control of the trigger mode controller 24, fetches and holds each data when the trigger mode is entered.

Also, the HD comparators 36, 38, 4
0 is supplied with HD position data for setting the timing of the charge read pulse SG, the charge sweep pulse SUB, and the high-speed drive pulse Vdrf from the microcomputer 10, and each HD comparator is a trigger mode controller. Under the control of 24, when the trigger mode is entered, each data is captured and retained.

When the count value of the VD counter 26 coincides with the value of the VD position data of the charge read pulse SG given from the microcomputer 10, the VD comparator 30 sends a signal to the HD comparator 36 indicating that. After the output, the HD comparator 36 receives this signal, and when the count value of the HD counter 28 coincides with the value of the HD position data of the charge read pulse SG given from the microcomputer 10, the charge read indicating that is output. The timing signal 42 is output to the HD counter 20.

The VD comparator 32, when the count value of the VD counter 26 coincides with the value of the VD position data of the charge sweep pulse SUB given from the microcomputer 10, outputs a signal indicating this to the HD comparator 38. After receiving this signal, the HD comparator 38, when the count value of the HD counter 28 matches the value of the HD position data of the charge sweep pulse SUB given from the microcomputer 10,
The charge sweep-away timing signal 44 indicating that is HD
Output to the inner counter 20. VD comparator 34
Indicates that the count value of the VD counter 26 is V of the high-speed drive pulse Vdrf given from the microcomputer 10.
When the value of the D position data matches, a signal indicating that is output to the HD comparator 40, and the HD comparator 40 receives this signal and then the HD counter 2
When the count value of 8 matches the value of the HD position data of the high speed drive pulse Vdrf given from the microcomputer 10, the high speed drive timing signal 4 indicating that
6 is output to the HD counter 20.

The VD comparator 30 and the HD comparator 36 constitute the charge read pulse generating means according to the present invention, and the VD comparator 32 and the HD comparator 38 constitute the charge sweeping pulse generating means according to the present invention. In addition, VD comparator 34, H
The D comparator 40 constitutes the high speed drive pulse generating means according to the present invention.

The HD counter 20 includes a CLK counter 48 and a high speed drive counter 50. When the high-speed drive timing signal 46 is input from the HD comparator 40, the high-speed drive counter 50 counts the basic clocks for a certain period of time to drive the high-speed drive pulse Vdr.
The signal VT that determines the timing of f is applied to the CLK counter 4
Output to 8. The CLK counter 48 uses the horizontal sync signal to accurately set the timing of the charge read pulse SG, the charge sweep pulse SUB, and the timing signal VT from the high-speed drive counter 50 with an accuracy equal to or less than the cycle of the horizontal sync pulse HD. A basic clock with a sufficiently short cycle is counted. Then, the count value of each pulse S
A timing pulse is output to the drive pulse generation circuit 22 when the value reaches G, SUB, or VT.

The drive pulse generation circuit 22 includes a charge read pulse generation circuit 52, a high speed drive pulse generation circuit 54, and a charge sweep-out pulse generation circuit 56.
The charge read pulse generation circuit 52, the drive pulse generation circuit 54, and the charge sweep-away pulse generation circuit 56 receive the timing pulses corresponding to the respective pulses SG, SUB, and Vdrf from the HD counter 20 as described above. , At that timing, the charge read pulse SG, the four-phase high-speed drive pulse Vdrf (V1 to V4),
In addition, a charge sweep-off pulse SUB is generated and supplied to the solid-state image sensor 102.

Next, the operation of the random trigger shutter circuit 18 thus constructed will be described. First, the operation during high-speed shutter will be described with reference to FIG. When performing the high-speed shutter operation by setting the exposure time shorter than one cycle of the vertical synchronizing signal, all of the VD position data representing the timing of the charge read pulse SG, the charge sweep-away pulse SUB, and the high-speed drive pulse Vdrf is used. The data having a value of 0 is sent from the microcomputer 10 to the respective VD comparators 30, 32, 3
Supply to 4. On the other hand, for the HD position data, the charge sweep pulse SUB and the high speed drive pulse Vdrf
The HD position data indicating the timing of the charge read pulse SG has a value of 0, and the HD position data indicating the timing of the charge read pulse SG has a value corresponding to the exposure time from the microcomputer 10 to the HD comparators 36, 38, 4 respectively.
Supply to 0.

When the trigger pulse Trig is input at the timing Tt as shown in FIG. 3 in the state where such position data is given to each comparator,
The trigger mode controller 24 controls each part to operate in the trigger mode at the timing of the horizontal synchronizing pulse HD immediately after the fall of the trigger pulse Trig (hence the timing of the drive pulse Vdr and the charge sweep-out pulse SUB). The VD counter 26 counts the vertical synchronizing pulse VD and the HD counter 28 counts the horizontal synchronizing pulse HD, but when the trigger mode is entered, the VD counter 26 once clears the count value to zero.

Then, each VD comparator 30, 3
Reference numerals 2 and 34 compare the count value of the VD counter 26 with the value of each VD position data input from the microcomputer 10 and held. In this case, since the values of the VD position data are all 0, each The VD comparators 30, 32, and 34 immediately output signals indicating that the count value of the VD counter 26 matches each VD position data to the corresponding HD comparators 36, 38, and 40, respectively.

As a result, each HD comparator 36,
38 and 40 compare the count value of the HD counter 28 with the value of each HD position data input from the microcomputer 10 and held, and determine whether or not they match. As described above, the HD position data of the charge sweep-out pulse SUB and the high-speed drive pulse Vdrf is 0, so the HD comparators 38, 40 are
Immediately outputs the charge sweep-away timing signal 44 and the high-speed drive timing signal 46 to the HD counter 20.
Output to. As a result, the HD counter 20 outputs a timing pulse representing a more precise timing of the charge sweep-out pulse SUB and the high speed drive pulse Vdrf to the drive pulse generation circuit 22. Drive pulse generation circuit 22
Then, when the charge sweep-out pulse generation circuit 56 receives this timing pulse, at that point, the final charge sweep-out pulse SUB is output, and then the charge sweep-out pulse SU is output.
Stop the output of B. In addition, the high-speed drive pulse generation circuit 5
4 outputs the high-speed drive pulse Vdrf for a certain period from the timing of receiving the timing pulse.

Therefore, as shown in FIG. 3, when the trigger pulse Trig is input, at the timing Ts immediately after that, the final charge sweep-out pulse SUB is supplied to the solid-state image pickup device 102, and the high-speed drive pulse Vdrf is supplied. Is a vertical charge transfer register 108 of the solid-state image sensor 102.
(FIG. 6). After that, when the count value of the HD counter 28 increases and coincides with the value of the HD position data of the charge read pulse SG, the HD comparator 36 outputs a charge read timing signal 42 indicating this to the HD counter 20. As a result, the HD counter 20 outputs a timing pulse representing a more precise timing of the charge read pulse SG to the drive pulse generation circuit 2.
Output to 2. In the drive pulse generation circuit 22, the charge read pulse generation circuit 52 receives this timing pulse, and outputs the charge read pulse SG at that time.

Therefore, as shown in FIG. 3, after the exposure of the optical sensor 106 is started at the timing Ts, for example, when the exposure time Te elapses, the charge read pulse SG is supplied to the solid-state image sensor 102, and the exposure time is T
The signal charge accumulated in the photosensor 106 during the period e is read out and moved to the vertical charge transfer register 108. The signal charges that have moved to the vertical charge transfer register 108 are transferred by the vertical charge transfer register 108 in the signal output period To after the first vertical synchronization pulse VD, and are further transferred by the horizontal charge transfer register 110, as in the conventional case, and are transferred to the image. The signal is output from the solid-state image sensor 102.

In this example, the mechanical shutter is also used, and as shown in FIG. 3, the mechanical shutter starts from the timing Tms preceding the trigger pulse Trig to the timing Tm immediately before the start of the image signal output.
In the period up to e, the aperture is opened in a preset aperture state, and is closed after timing Tme.

The above is the basic operation at the time of high-speed shutter. In such an operation, since the exposure is started immediately after the fall of the trigger pulse Trig, the delay time from the trigger pulse Trig to the start of the exposure is set. We can meet the demand of making it as small as possible.

By the way, when the exposure time is longer than the time illustrated in FIG. 3, the timing for supplying the high-speed drive pulse Vdrf to the solid-state image sensor 102 is the trigger pulse T.
It is advantageous to suppress the occurrence of smear by setting the timing closer to the charge read pulse SG, not immediately after the fall of rig. The example of the present embodiment is highly flexible with respect to such timing adjustment.
High-speed drive pulse Vdrf given to the D comparator 40
It is possible to supply the high-speed drive pulse Vdrf to the solid-state image sensor 102 at a timing suitable for suppressing smear only by changing the value of the HD position data of.

Further, in the example of FIG. 3, the time until the signal output is started after the charge read pulse SG is supplied is relatively long, and during this period, the vertical charge transfer register 10 is started.
8 is in a stopped state. However, if the vertical charge transfer register 108 has a long stop period, dark noise increases in proportion to the length of the stop period. Therefore, in terms of suppressing the dark noise, the vertical charge transfer register 108 is suppressed.
It is desirable to make the suspension period of (2) as short as possible.

In order to shorten the stop period of the vertical charge transfer register 108, as shown by the dotted line in FIG.
It suffices to supply the charge read pulse SG at a position close to the signal output period To (hence, the succeeding vertical synchronizing pulse VD). Therefore, exposure is started and the high speed drive pulse Vd is started.
The timing of supplying rf may be shifted to the rear, for example, Ts'. In this embodiment, such a timing shift is caused by the value of the HD position data of the charge sweep-out pulse SUB given to the HD comparator 38 and the high-speed drive pulse Vd given to the HD comparator 40.
The HD position data of rf may be simply increased, and this is extremely easy.

Next, the operation at the low speed shutter will be described with reference to FIG. Since the exposure time is set to be longer than one cycle of the vertical synchronizing signal to perform the low-speed shutter operation, here, as an example, the value of the VD position data representing the timing of the charge read pulse SG and the high speed drive pulse Vdrf is set to 2, and the charge sweep is performed. The value of the VD position data indicating the timing of the discard pulse SUB is set to 0, and the microcomputer 10 causes the respective VD comparators 30, 32, 34 to
Supply to.

On the other hand, with respect to the HD position data, as an example, the HD position data representing the timing of the charge sweep-out pulse SUB is set to 0 and the HD comparator 3 is set.
Supply to 8. As the value of the HD position data representing the timing of the charge read pulse SG and the high speed drive pulse Vdrf, the high speed drive pulse Vdrf is supplied after the mechanical shutter is closed, and then the horizontal sync pulse is supplied to supply the charge read pulse SG. The value set in the cycle unit is supplied from the microcomputer 10 to the HD comparators 36 and 40.

When the trigger pulse Trig is input at the timing Tt as shown in FIG. 4 in the state where such position data is given to each comparator,
The trigger mode controller 24 controls each part to operate in the trigger mode at the timing of the horizontal synchronizing pulse HD immediately after the fall of the trigger pulse Trig (hence the timing of the drive pulse Vdr and the charge sweep-out pulse SUB).

The VD counter 26 counts the vertical sync pulse and the HD counter 28 counts the horizontal sync pulse, but when the trigger mode is entered, the VD counter 26 once clears the count value to zero. Further, when the trigger mode is entered, the HD comparators 36 and 40 take in the count value (corresponding to Tof in FIG. 4) of the HD counter 28 at that time point, and the value is given from the microcomputer 10 and held therein. The value of the HD position data added to the value of the HD position data and the count value added is held as new HD position data.

Then, each VD comparator 30, 3
Reference numerals 2 and 34 compare the count value of the VD counter 26 with the value of each VD position data held, but since the value of the VD position data of the charge sweep-out pulse SUB is 0, the VD comparator 32 Immediately, a signal indicating that the count value of the VD counter 26 matches each VD position data is output to the corresponding HD comparator 38.

As a result, the HD comparator 38
The count value of the HD counter 28 and the charge sweep pulse SU that is input from the microcomputer 10 and is being held
The value of the HD position data of B is compared, and it is determined whether or not they match. Here, charge sweep pulse SU
Since the HD position data of B also has a value of 0, the HD comparator 38 immediately outputs the charge sweep-away timing signal 44.
Is output to the HD counter 20. As a result, the HD counter 20 outputs a timing pulse representing a more precise timing of the charge sweep-out pulse SUB to the drive pulse generation circuit 22. In the drive pulse generation circuit 22,
The charge sweep-out pulse generation circuit 56 receives this timing pulse, and at that point, the last charge sweep-out pulse SU
After outputting B, the output of the charge sweep-away pulse SUB is stopped. Therefore, as shown in FIG. 4, when the trigger pulse Trig is input, the timing T immediately after that is input.
At s, the final charge sweep pulse SUB is supplied to the solid-state image sensor 102.

After that, when the count value of the VD counter 26 rises to 2, the count values of the VD comparators 30 and 34 coincide with the value of the VD position data.
The VD comparators 30 and 34 output signals indicating that to the HD comparators 36 and 40, respectively. As a result, the HD comparators 36 and 40 subsequently compare the value of the HD position data held by each with the count value of the HD counter 28, and when they match, the high-speed drive timing signal 46 and the charge reading, respectively. The timing signal 42 is output to the HD counter 20.

Then, the HD counter 20 outputs a timing pulse representing a more precise timing of the high speed drive pulse Vdrf and the charge read pulse SG to the drive pulse generation circuit 22. In the drive pulse generation circuit 22,
The high speed drive pulse generation circuit 54 and the charge read pulse generation circuit 52 receive these timing pulses,
When the timing pulse is received, the high speed drive pulse Vdrf and the charge read pulse SG are output to the solid-state image sensor 102, respectively.

In this example, as shown in FIG. 4, the mechanical shutter is opened in a preset aperture state during the period from the timing Tms preceding the trigger pulse Trig to the timing Tme, and the timing Tm is reached.
The state after e is closed, and the exposure time Te is from the timing Tms to the timing Tme. Then, the high speed drive pulse Vdrf and the charge read pulse SG V
Since the D position data and the HD position data are set as described above, the high speed drive pulse Vdrf is supplied to the solid-state image sensor 102 in synchronization with the closing of the mechanical shutter at the timing Tme, and the timing Tr immediately after that is supplied. Then, the charge read pulse SG is supplied to the solid-state image sensor 102. After the charge read pulse SG is supplied, as in the case of the high speed shutter operation, in the signal output period To following the next vertical synchronizing pulse VD,
The signal charge is transferred, and an image signal representing the image pickup result is output from the solid-state image pickup element 102.

As described above, in the random trigger shutter circuit 18 of the present embodiment, since the timing of each pulse can be set in units of vertical synchronizing pulse periods, long-time exposure over a plurality of vertical synchronizing pulse periods is possible. . Also, after closing the mechanical shutter as described above,
Since the high speed drive pulse and the charge read pulse can be supplied, it is possible to prevent smear by preventing exposure during the period in which the vertical charge transfer register 108 is driven at high speed in order to discard unnecessary signal charges. .

In the present embodiment, as described above, when the trigger mode is entered, the HD comparators 36 and 40 take in the count value of the HD counter 28 at that time, and the value is read by the microcomputer 10. Is added to the values of the respective HD position data given by the above, and the addition result is used to determine the timing of the high speed drive pulse Vdrf and the charge read pulse SG. Therefore, even if the trigger pulse Trig is input at an arbitrary timing with respect to the vertical synchronizing pulse VD, the exposure time Te
Can be accurately set to the time corresponding to the values of the VD position data and the HD position data given to the VD comparator and the HD comparator.

In an actual photographing environment, the shutter may be re-opened immediately after the random shutter is operated once, but the present embodiment also deals with such re-shuttering. be able to. As shown in FIG. 5, when the first trigger pulse Trig is input at the timing Tt1, the final charge sweep pulse SUB, the high speed drive pulse Vdrf, and the charge read pulse SG are input as described with reference to FIG.
Is generated (indicated by the dotted line in FIG. 5). However, after that, when the shutter is turned off again at the timing Tt2 and the trigger pulse Trig is input again,
The VD comparators 30, 32, 34 and the HD comparators 36, 38, 40 again fetch and hold the VD position data and the HD position data from the microcomputer 10, and the VD counter 26 is cleared to perform the same operation. Repeated. Therefore, at the timing of the horizontal synchronizing pulse HD immediately after the timing Tt2, the charge sweep pulse SUB and the high speed drive pulse V
drf is output, and then the charge read pulse SG is output. Then, the signal charge is transferred in the subsequent signal output period To, and the image signal is output from the solid-state image sensor 102.

[0058]

As described above, in the random trigger shutter circuit of the present invention, the charge sweep pulse generating means receives the data relating to the timing of the charge sweep pulse, and when the trigger pulse is input, Based on the time measurement result by the second time measuring means, the charge sweeping-off pulse is supplied to the solid-state imaging device at the timing corresponding to the timing data. Further, the high speed drive pulse generating means receives the data relating to the timing of the high speed drive pulse, and responds to the timing data based on the measurement results of the time by the first and second time measuring means when the trigger pulse is input. A high-speed drive pulse is supplied to the solid-state image sensor at the timing. And
The charge read pulse generation means receives data relating to the timing of the charge read pulse, and at the timing corresponding to the timing data based on the result of the time measurement by the first and second timing means when the trigger pulse is input. A charge read pulse is supplied to the solid-state image sensor.

As described above, in the present invention, the charge sweeping pulse, the high speed driving pulse, and the high speed driving pulse are obtained by using the first and second timing means for counting the first and second synchronizing pulses, respectively.
Also, since the timing of the charge read pulse is set, the timing of each pulse can be set not only in the cycle unit of the second synchronization pulse but also in the cycle unit of the first synchronization pulse. Therefore, the exposure time of the optical sensor can be flexibly controlled in a wide range from short time to long time, and further, the timing of supplying each pulse after the trigger pulse is input can be set variously.

As a result, according to the present invention, it is possible to perform long-time exposure over a plurality of cycles of the first synchronizing pulse. Further, after the trigger pulse is input, each pulse is supplied to the solid-state image sensor with a time, and the charge read pulse is supplied in the vicinity of the subsequent first synchronization pulse to reduce dark noise. be able to. Further, when the mechanical shutter is used, it is possible to prevent the smear from occurring by supplying the high speed drive pulse and the charge read pulse after the mechanical shutter is closed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a random trigger shutter circuit according to the present invention.

FIG. 2 is a block diagram showing an entire solid-state imaging device including the random trigger shutter circuit of FIG.

FIG. 3 is a timing chart showing the operation of the random trigger shutter circuit according to the embodiment.

FIG. 4 is a timing chart showing the operation of the random trigger shutter circuit of the embodiment example during long-time exposure.

FIG. 5 is a timing chart showing the operation of the random trigger shutter circuit of the embodiment when the shutter is turned off again.

FIG. 6 is a schematic plan view showing an example of a solid-state image sensor.

FIG. 7 is a timing chart showing a control when exposure using an electronic shutter is performed by a random trigger.

[Explanation of symbols]

2 ... Solid-state imaging device, 4 ... CDS / ADC circuit, 6 ...
... Signal processing circuit, 8 ... Timing generation circuit, 10 ...
Microcomputer, 12 ... Crystal oscillator, 14 ...
… Reference clock pulse, 16 …… Video signal, 18 ……
Random trigger shutter circuit, 19 ... Trigger control block, 20 ... HD counter, 22 ... Drive pulse generation circuit, 24 ... Trigger mode controller, 26 ... VD counter, 28 ... HD counter, 30, 32, 34 ... VD comparator, 36,
38, 40 ... HD comparator, 52 ... Charge reading pulse generation circuit, 54 ... High-speed drive pulse generation circuit, 56 ... Charge sweep-out pulse generation circuit

Claims (7)

[Claims] 1. An optical sensor when a trigger pulse is input to a solid-state imaging device that images a subject with a plurality of optical sensors and outputs an image signal representing an imaging result in synchronization with a first synchronization pulse. Charge sweep pulse for sweeping away the signal charge accumulated in the photosensor to determine the timing of starting the exposure, a charge read pulse for reading the signal charge accumulated in the photosensor to the signal charge transfer means, and the transfer means. A random trigger shutter circuit that supplies a high-speed drive pulse for driving and driving the signal charge held by the transfer unit at a high speed and discarding the signal charge, the time being measured by counting the first synchronization pulse. A first time measuring means; a second time measuring means for measuring a time by counting a second synchronizing pulse having a shorter cycle than the first synchronizing pulse; The data related to the timing of the charge sweep pulse is received, and the charge sweep is performed at the timing corresponding to the timing data based on the measurement result of the time by the first and second timing means when the trigger pulse is input. A charge sweep-away pulse generating means for supplying a discard pulse to the solid-state imaging device, and data for timing of the high-speed drive pulse, and the first pulse when the trigger pulse is input.
And high-speed drive pulse generating means for supplying the high-speed drive pulse to the solid-state imaging device at a timing corresponding to the timing data based on the result of time measurement by the second timing means, and data relating to the timing of the charge read pulse. The charge read pulse is supplied to the solid-state image sensor at a timing corresponding to the timing data based on the measurement result of the time by the first and second timing means when the trigger pulse is input. A random trigger shutter circuit comprising a reading pulse generating means. 2. The second sync pulse has the same cycle as a drive pulse supplied to the transfer means when the image signal is output in synchronization with the first sync pulse. The random trigger shutter circuit according to claim 1. 3. A cycle of the high speed drive pulse is shorter than a cycle of a drive pulse supplied to the transfer means when the image signal is output in synchronization with the first synchronization pulse. Item 2. The random trigger shutter circuit according to item 1. 4. The time from the timing represented by the timing data of the charge sweep pulse to the timing represented by the timing data of the charge read pulse is longer than the time for one cycle of the first synchronization pulse. The random trigger shutter circuit according to claim 1, which is characterized in that. 5. The random trigger shutter circuit according to claim 1, wherein the timing data of the charge read pulse represents a timing in the vicinity of the first synchronization pulse. 6. The light incident on the solid-state imaging device is controlled by a mechanical shutter, and the timing represented by the timing data of the high-speed drive pulse represents the timing immediately after the mechanical shutter is closed. The random trigger shutter circuit according to claim 4. 7. The transfer means is driven during a period corresponding to one cycle of the first synchronization pulse after the first first synchronization pulse after the charge read pulse is supplied to the solid-state imaging device. The random trigger shutter circuit according to claim 1, wherein an image signal is output.