JP7183009B2 - Imaging element and imaging device - Google Patents

Description

The present invention relates to an imaging device and an imaging device.

2. Description of the Related Art Conventionally, an imaging device is known that has a circuit including a vertical counter and a horizontal counter for determining the timing of generating drive pulses for controlling reset operation and readout operation. In order to control the exposure time of the imaging element in such a configuration, it is necessary to appropriately control the timing of resetting the count values of the vertical counter and the horizontal counter. Conventionally, in a configuration in which the count values of a vertical counter and a horizontal counter are reset by a vertical synchronizing signal and a horizontal synchronizing signal respectively input from the outside of an image sensor, there is a method of controlling the output timing of the vertical synchronizing signal and the horizontal synchronizing signal. Proposed.

In Patent Document 1, horizontal scanning is performed based on an asserted horizontal synchronizing signal, and one frame of an image is scanned by asserting the horizontal synchronizing signal a predetermined number of times within one vertical period, which is the interval at which the vertical synchronizing signal is asserted. is disclosed. In the imaging apparatus of Patent Document 1, when there are two types of intervals at which the horizontal synchronization signal is asserted, horizontal periods with long intervals are set between horizontal periods with short intervals. As a result, when smoothed over the entire screen, horizontal scanning can be performed at uniform timing.

In Japanese Patent Laid-Open No. 2002-200002, when the interval of generation of vertical synchronization signals is different from the time required to generate a predetermined number of horizontal synchronization signals, the interval of generation of vertical synchronization signals is set to an integral multiple of the interval of generation of horizontal synchronization signals. discloses an imaging device that changes the generation interval of the horizontal synchronizing signal. In the imaging apparatus of Patent Document 2, all horizontal scanning can be performed in the same time, and the exposure time can be kept uniform within the screen.

Japanese Patent No. 5737921 Japanese Patent No. 5268539

Conventionally, a configuration is known in which a count value is reset and read out in synchronization with a pulse generated by a signal generator that operates with a clock different from that of the counter. In this case, even if exactly the same device is used as a clock source, clock cycle deviation occurs due to individual differences between devices. In a configuration in which the generation timing of a synchronous signal and the reset timing of various counters are controlled by asynchronous clocks, if the count value is reset in synchronization with the input of the synchronous signal, the reset cycle of the count value is shifted. Therefore, it becomes impossible to always control the timing of the read scanning and the reset scanning according to the reset cycle of the count value to a constant timing. As a result, a difference occurs in the exposure time in the screen before and after the synchronization, and an exposure step occurs in the screen. The image capturing apparatuses disclosed in Patent Documents 1 and 2 generate the synchronization signal that governs the timing of resetting the count value from the synchronization signal generation circuit that operates with the same clock as the counter, thereby solving such problems. can't

SUMMARY OF THE INVENTION It is an object of the present invention to provide an imaging device capable of appropriately controlling the timing of reset scanning and readout scanning while performing imaging in synchronization with a vertical synchronization signal input asynchronously with various counters, and an imaging apparatus having the same. and

An imaging device as one aspect of the present invention includes a plurality of pixels arranged in a matrix and a first counter that resets a first count value at a first period or at a first timing outside the first period. a second counter for resetting a second count value at a second timing in the second period or at a second timing outside the second period; detecting means for detecting an externally input vertical synchronizing signal; generating means for generating a pulse for driving the plurality of pixels based on the count value or the second count value, the generating means generating one of the first count value and the second count value, A pulse is generated in synchronization with a count value selected based on a count value of a counter different from the first counter and the second counter.

According to the present invention, it is possible to provide an imaging device capable of appropriately controlling the timing of reset scanning and readout scanning while performing imaging in synchronization with a vertical synchronization signal that is input asynchronously with various counters, and an imaging apparatus having the same. can be done.

1 is a block diagram showing the configuration of an imaging device according to an embodiment of the present invention; FIG. FIG. 2 is an explanatory diagram of an imaging device of Example 1; 4 is a timing chart showing a method of driving a unit pixel; 4 is a timing chart of reset scanning and readout scanning of the pixel array of Example 1. FIG. 4 is a timing chart of reset scanning and readout scanning of a pixel array in multiple frames; FIG. 11 is a circuit block diagram of an imaging device of Example 2; 9 is a timing chart of reset scanning and readout scanning of the pixel array of Example 2. FIG.

Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In each figure, the same reference numerals are given to the same members, and overlapping descriptions are omitted.

FIG. 1 is a block diagram showing the configuration of an imaging device 1 according to an embodiment of the invention. The imaging device 1 has an imaging optical system with one or more lenses. The first lens 100 is arranged on the tip side (subject side) of the imaging optical system. The diaphragm 101 has its aperture diameter controlled by the diaphragm drive circuit 119 via the diaphragm actuator 120, and adjusts the light amount during photographing. The second lens 102 and the third lens 103 are controlled by the focus driving circuit 117 via the focus actuator 118 based on the output of the CPU 110, and move back and forth along the optical axis to adjust the focal position of the imaging optical system.

A focal plane shutter 104 is controlled by a shutter drive circuit 116 to adjust the exposure time during still image shooting. The optical low-pass filter 105 reduces false colors and moire in the captured image. The imaging device 106 photoelectrically converts an optical image of a subject formed by the imaging optical system into an electric signal. The imaging device 106 operates according to the clock generated by the first clock generation circuit 107 and is controlled by the CPU 110 .

A DSP (Digital Signal Processor) 108 is an image processing unit that performs processing such as correction and compression on image data captured by the image sensor 106 . The RAM 109 has the function of signal holding means for holding output data from the image sensor 106, the function of image data storage means for storing image data processed by the DSP 108, and the function of work memory when the CPU 110 operates. . Although these functions are implemented using the RAM 109 in this embodiment, they may be implemented using a memory with a sufficiently high access speed and no problem in operation. Also, in this embodiment, the RAM 109 is provided outside the DSP 108 and the CPU 110 , but part or all of the functions of the RAM 109 may be incorporated in the DSP 108 or the CPU 110 .

The CPU 110 operates according to the clock generated by the second clock generation circuit 111 and controls the operation of the imaging device 1 in a centralized manner. The CPU 110 executes a program for controlling the operation of each section of the imaging device 1 . The CPU 110 also has a function of controlling the imaging timing of the image sensor 106 by outputting a vertical synchronization signal to the image sensor 106 .

The display unit 112 displays captured still images, moving images, menus, and the like. The operation unit 113 sets the CPU 110 for shooting commands, shooting conditions, and the like. The recording medium 114 is a recording medium detachable from the imaging device 1 for recording still image data and moving image data. The ROM 115 stores programs executed by the CPU 110 to control the operation of each unit of the imaging apparatus 1 .

The imaging element 106 of this embodiment will be described with reference to FIG. FIG. 2 is an explanatory diagram of the image sensor 106 of this embodiment.

First, the configuration of the image sensor 106 will be described with reference to FIG. FIG. 2A is a circuit block diagram of the imaging device 106. FIG. A plurality of unit pixels 201 are arranged in a matrix in the pixel array 200 . Specifically, (m+1) unit pixels 201 are arranged in the horizontal direction and (n+1) unit pixels 201 are arranged in the vertical direction. Both m and n are natural numbers. The drive pulse generation circuit 202 generates pulses for resetting the unit pixels 201 and reading pixel signals generated by photoelectric conversion in the unit pixels 201 according to the count value of the first H counter 210 or the second H counter 211. to generate The generated pulse is supplied to the pixel drive circuit 204 . The row selection circuit 203 selects a row (specific row) to which the pulse generated by the drive pulse generation circuit 202 is supplied according to the count value of the first V counter 212 or the second V counter 213 , and the pixel drive circuit 204 set the selected row to . The pixel drive circuit 204 supplies pulses generated by the drive pulse generation circuit 202 to the row set by the row selection circuit 203 .

Pixel signals are output to the vertical output lines 205 row by row according to pulses supplied from the pixel driving circuit 204 . The constant current source 206 forms a source follower circuit in combination with the pixel amplifier transistor 221 . An AD conversion circuit (hereinafter referred to as ADC) 207 converts the analog output output to the vertical output line 205 into a digital value corresponding to the output. The operation timing of ADC 207 is controlled by first H counter 210 or second H counter 211 . Pixel signals converted by the ADC 207 are sequentially selected by the horizontal scanning circuit 208 in synchronization with the count timing of the first H counter 210 or the second H counter 211 and transferred to the output section 209 . The output unit 209 outputs the pixel signal from which the noise signal has been subtracted to the outside.

A synchronous counter 215 has a first H counter 210 , a second H counter 211 , a first V counter 212 , a second V counter 213 and a frame counter 214 , and is generated by the first clock generation circuit 107 . clock. The first H counter 210 counts up the first H count value with the input of the clock. The first H count value is reset when a predetermined period elapses or when the count value of the frame counter 214 counts up to an even number. The second H counter 211 counts up the second H count value with the input of the clock. The second H count value is reset when a predetermined period elapses or when the count value of the frame counter 214 counts up to an odd number. Here, the predetermined period is, for example, a period set by the CPU 110 . The first V counter 212 is a counter that counts up the first V count value in synchronization with the timing at which the first H count value is reset. The first V count value is reset at the timing when the count value of the frame counter 214 counts up to an even number. The second V counter 213 is a counter that counts up the second V count value in synchronization with the timing at which the second H count value is reset. The second V count value is reset when the count value of the frame counter 214 counts up to an odd number. The frame counter 214 is a counter that counts up a count value in synchronization with the timing at which the synchronization signal detection circuit 216 detects the vertical synchronization signal input from the CPU 110 . The count value of the frame counter 214 can transition to at least the first state or the second state. In this embodiment, frame counter 214 functions as a third counter.

Although the pixel drive circuit 204 and the ADC 207 are incorporated in the image sensor 106 in this embodiment, they may be provided in a chip separate from the image sensor 106 .

Next, the circuit configuration of the unit pixel 201 will be described with reference to FIG. 2(b). FIG. 2B is a circuit diagram of the unit pixel 201. As shown in FIG. A photodiode (PD) 217 is an element forming the unit pixel 201 under the microlens, and forms a photoelectric conversion unit. The photoelectric converter transfer switch 218 is controlled by a signal φptx. By setting the value of the signal φptx to High (hereinafter referred to as H), photocharges accumulated in the photoelectric conversion portion can be transferred to the floating diffusion portion (FD) 219 .

Reset switch 220 is controlled by signal φpres to initialize FD 219 . The pixel amplifier transistor 221 is connected to the constant current source 206 via the select switch 222 and the vertical output line 205 . When the value of the input signal φpsel of the select switch 222 becomes H, the pixel amplifier transistor 221 is connected to the constant current source 206 to form a pixel amplifier. Since the FD 219 is connected to this pixel amplifier, the charge transferred from the PD 217 to the FD 219 is converted by the pixel amplifier into a voltage value corresponding to the amount of charge and output to the vertical output line 205 as a pixel signal.

A method of driving the unit pixel 201 will be described below with reference to FIG. FIG. 3 is a timing chart showing how the pixel driving circuit 204 drives the unit pixel 201. As shown in FIG. All of the times described below as pulse change timings are synchronized with the count timing of the first H counter 210 or the second H counter 211 . In the figure, the timing at which 0 is entered as the first H count value of the first H counter 210 or the second H count value of the second H counter 211 corresponds to the first or second H count value. It shows the reset timing. The notation of the first or second H count value other than the reset timing is omitted. In FIG. 3, the H count value at the reset timing, that is, the H count value of 0, is shown larger than the other H count values in order to make the reset timing easier to understand. The H count value is counted up at regular intervals.

FIG. 3(a) is a timing chart showing the reset operation. At time t300, the value of signal φptx is set to H, and PD217 is connected to FD219. At this time, since the value of the signal φpres remains H, the unit pixel 201 is connected to the power supply and enters the reset state. At time t301, the value of the signal φptx is set to Low (hereinafter referred to as L), and the reset state of the unit pixel 201 is released. After time t301, accumulation of the unit pixel 201 is started. The operation corresponding to the timing chart of FIG. 3A is performed in a period shorter than the cycle in which the H count value is reset.

FIG. 3B is a timing chart showing the read operation of one row. At time t302, the value of signal φpsel is set to H and a row is selected. At time t303, the value of the signal φpres is set to L, and the reset of the FD 219 is released. Between time t304 and time t305, the ADC 207 AD-converts the reset level of the FD 219 . Through this AD conversion, an N signal, which is a reset level digital value, is obtained. At time t305, the signal φptx is set to H, the PD 217 is connected to the FD 219, and the photoelectric charges generated by the PD 217 are transferred to the FD 219. At time t306, the value of signal φptx is set to L, and the transfer ends. Here, the H count value at time t305 and the H count value at time t300 in FIG. 3A are set to be the same. Also, the first or second H count value at time t306 and the first or second H count value at time t301 in FIG. 3A are set to be the same. By setting in this way, the accumulation time from the reset of the unit pixel 201 to the readout can be accurately controlled to be an integral multiple of the cycle at which the first or second H count value is reset. can be done.

Between time t306 and time t307, the ADC 207 AD-converts the reset level of the FD 219 . By this AD conversion, an S signal, which is a digital value output according to the photocharge accumulated in the PD 217, is obtained. At time t308, the signal φhsr_0 is set to H. As a result, the ADC 207 in the 0th column of the selected row is connected to the output section 209 . The output unit 209 subtracts the N signal from the S signal and outputs it, thereby obtaining the digital value of the photocharge accumulated in the unit pixel 201 of the 0th column. At time t309, the value of the signal φhsr_0 is set to L, the value of the signal φhsr_1 is set to H, and the digital value of the unit pixel 201 in the first column is obtained. At time t310, the value of the signal φhsr_1 is set to L, and the value of the signal φhsr_2 (not shown) is set to H. Thereafter, horizontal scanning is sequentially performed, and the transfer of the unit pixel 201 of the m-th column is completed between time t311 and time t312, and the horizontal transfer is completed. At the same time when the horizontal transfer ends, the value of the signal φpres is set to H, and the FD 219 of the selected row is reset. At time t313, the value of signal φpsel is set to L, and row selection ends. The operation corresponding to the timing chart of FIG. 3B is performed in a period shorter than the cycle in which the first or second H count value is reset.

As described above, the reset operation and read operation of a predetermined row are performed in a period shorter than the cycle in which the first or second H count value is reset. An image can be acquired by sequentially performing the reset operation and the readout operation from the top row.

Reset scanning and readout scanning of the pixel array 200 when the count value of the frame counter 214 is counted up to an even number will be described below with reference to FIG. FIG. 4 is a timing chart of reset scanning and readout scanning of the pixel array 200. FIG. At time t400, the synchronizing signal detection circuit 216 detects a vertical synchronizing signal (hereinafter referred to as external VD) input from the CPU 110 to the image sensor 106. FIG. The count value of the frame counter 214 is counted up to an even number in synchronization with the detection (input) of the external VD. At this time, the first H count value of the first H counter 210 and the first V count value of the first V counter 212 are reset. At time t401 set by the CPU 110, the reset operation of the 0th row of the pixel array 200 is started. The reset operation is executed according to the timing chart of FIG. 3(a) in synchronization with the first H count value. After a predetermined period has elapsed from time t401, the first H count value is reset, and the first V count value is counted up accordingly. When the first V count value is counted up, the row select circuit 203 selects the next row and reset scanning of the next row is started. In this manner, the reset operation is sequentially performed on a row-by-row basis.

At time t402, the reset operation of the (n-2)th row is started. At time t403, the sync signal detection circuit 216 detects the external VD. The count value of the frame counter 214 is incremented to an odd number in synchronization with the detection of the external VD. Therefore, the second H count value of the second H counter 211 and the second V count value of the second V counter 213 are reset, and the first H count value and the first V count value are not reset. Therefore, the reset operation continues uninterrupted. At time t404, the first H count value is reset. Time t404 is the timing at which the first H count value is reset for the first time after the external VD is detected at time t403. In this embodiment, the read operation is started at this timing. The read operation is performed in synchronization with the first H count value and along the timing chart of FIG. 3(b). The accumulation time is the time difference between the time t401 set by the CPU 110 and the time t404.

By performing such an operation, reset scanning and read scanning are performed in synchronization with the detection of the external VD, and scanning is not interrupted by the next detection of the external VD. As a result, even before and after the detection timing of the external VD, no difference occurs in the exposure time within the screen, and no exposure step occurs within the screen.

When the count value of the frame counter 214 is counted up to an odd number, the roles of the first H counter 210 and the second H counter 211 are switched, and the roles of the first V counter 212 and the second V counter 213 are switched. is replaced.

FIG. 5 is a timing chart of reset scanning and read scanning of the pixel array 200 in a plurality of frames. At time t550, the count value of the frame counter 214 is counted up to 2k (k: natural number), and the first H count value of the first H counter 210 is reset. At time t551, reset scanning 500 is started in synchronization with reset timing of the first H count value. At time t552, the count value of the frame counter 214 is counted up to 2k+1, and the second H count value of the second H counter 211 is reset. At this time, reset scan 500 is not interrupted because the first H count value is not reset. At time t553, read scanning 501 is started in synchronization with the reset timing of the first H count value.

At time t554, reset scanning 502 is started in synchronization with the reset timing of the second H count value. At time t555, the count value of the frame counter 214 is counted up to 2k+2, and the first H count value is reset. At this time, the reset scan 502 is not interrupted because the second H count value is not reset. At time t556, read scanning 503 is started in synchronization with the reset timing of the second H count value.

As described above, according to the configuration of this embodiment, while performing imaging in synchronization with vertical synchronization signals input asynchronously with various counters, the cycles of reset scanning and readout scanning do not change before and after the synchronization. The image pickup device can be driven like this.

In this embodiment, the first H count value of the first H counter 210 and the second H count value of the second H counter 211 are reset in the same period, but they are not necessarily reset in the same period. good too. For example, the reset period of the first H count value is set to the optimum period for reset scanning and readout scanning for moving images, and the reset period of the second H count value is set to the optimum period for reset scanning and readout scanning for still images. You can set it to period. In this case, at the timing when the count value of the frame counter 214 counts up to an even number, reset scanning and read scanning of the moving image are performed according to the first H count value. Also, at the timing when the count value of the frame counter 214 is counted up to an odd number, reset scanning and readout scanning of the still image are performed according to the second H count value. Such control makes it possible to acquire different types of data in successive frames.

Moreover, in this embodiment, the cycles of the first H count value and the second H count value are always constant, but the present invention is not limited to this. The period should be kept constant in the same frame, but it is not necessary to keep the period constant in a plurality of frames. For example, the counter synchronized at the timing when the count value of the frame counter 214 is counted up to 4k, 4k+1, and 4k+2 is set to the period for the moving image, and the counter synchronized at the timing to be counted up to 4k+3 is set to the period for the still image. make it work. With such control, it is possible to obtain a still image in one of the four consecutive frames and to obtain a moving image in the other frames.

The configuration of the imaging device 106 of this embodiment will be described with reference to FIG. FIG. 6 is a circuit block diagram of the imaging device 106 of this embodiment. In this embodiment, the same reference numerals are given to the same constituent elements as in the first embodiment, and detailed description thereof will be omitted. In this embodiment, the first V counter 212 functions as a third counter.

The first H count value of the first H counter 210 is obtained when a predetermined period has elapsed or when the synchronization signal detection circuit 216 detects a vertical synchronization signal (hereinafter referred to as external VD) input from the CPU 110 to the image sensor 106. is reset by The first V counter 212 counts up the first V count value in synchronization with the timing at which the first H count value is reset. The first V count value is reset at the timing when the synchronization signal detection circuit 216 detects the external VD.

The second H count value of the second H counter 211 is reset when a predetermined cycle has elapsed or in synchronization with the timing at which the reset pulse generation circuit 601 generates a reset pulse. The second V counter 213 counts up the second V count value in synchronization with the timing at which the second H count value is reset. The second V count value is reset in synchronization with the timing at which the reset pulse generation circuit 601 generates the reset pulse.

The reset timing setting means 600 holds a value (predetermined value) set by the CPU 110, for example. The reset pulse generation circuit 601 compares the first V count value with the value held by the reset timing setting means 600, and outputs a reset pulse when both match. Therefore, the second H count value and the second V count value are reset in synchronization with the timing when the first V count value and the value held by the reset timing setting means 600 match.

FIG. 7 is a timing chart of reset scanning and readout scanning of the pixel array 200 of this embodiment. As an example, a case where the reset timing setting means 600 holds "p-1" as a set value will be described.

At time t700, sync signal detection circuit 216 detects external VD. The first H count value and the first V count value are reset in synchronization with the detection (input) of the external VD. At time t701 set by the CPU 110, the reset operation of the 0th row of the pixel array 200 is started. The reset operation is executed according to the timing chart of FIG. 3(a) in synchronization with the first H count value. After a predetermined period has elapsed from time t701, the first H count value is reset, and the first V count value is counted up accordingly. When the first V count value is counted up, the row select circuit 203 selects the next row and reset scanning of the next row is started. In this manner, the reset operation is sequentially performed on a row-by-row basis.

At time t 702 , when the first V count value is counted up to “p−1”, it matches the value held by reset timing setting means 600 . Therefore, the reset pulse generation circuit 601 generates a reset pulse, and the second H count value and the second V count value are reset at a timing outside the predetermined cycle. From this timing, the reset operation is performed in synchronization with the second H count value. Row selection is also based on the second Vcount value. After a predetermined period has elapsed from time t702, the second H count value is reset and the second V count value is counted up. When the second V count value is counted up, the row select circuit 203 selects the next row and reset scanning of the next row is started.

At time t703, the sync signal detection circuit 216 detects the external VD. The first H count value is reset outside the predetermined period in synchronization with the detection of external VD. However, since the reset operation at this timing is executed according to the second H count value, the reset operation is not interrupted. At time t704, the read operation is started in synchronization with the reset timing of the second H count value. The read operation is performed according to the timing chart of FIG. 3(b) in synchronization with the second H count value.

As described above, from the start of the reset operation at time t701 to the start of the readout operation at time t704, the scanning period does not change even before and after the detection of the external VD. Therefore, the accumulation time for any row is the time difference between time t701 and time t704 set by the CPU 110, and is a constant accumulation time within the plane. As a result, even before and after synchronization, there is no difference in the exposure time within the screen, and there is no exposure step within the screen.

As described above, according to the configuration of this embodiment, it is possible to appropriately control readout scanning and reset scanning while performing imaging in synchronization with vertical synchronization signals input asynchronously with various counters. become. In addition, since read scanning can always be performed in synchronization with the second H counter 211, the driving pulse generation circuit can be simplified as compared with the configuration of the first embodiment.

Although preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of the gist.

106 image sensor 201 unit pixel 202 drive pulse generation circuit (generation means)
210 first H counter (first counter)
211 second H counter (second counter)
216 synchronization signal detection circuit (detection means)

Claims (9)

a plurality of pixels arranged in a matrix;
a first counter that resets a first count value at a first period or at a first timing outside the first period;
a second counter that resets a second count value at a second period or at a second timing outside the second period;
detection means for detecting a vertical synchronizing signal input from the outside;
generating means for generating a pulse for driving the plurality of pixels based on the first count value or the second count value;
The generating means synchronizes with a count value selected from the first count value or the second count value based on a count value of a counter different from the first counter and the second counter. and generating the pulse. further comprising a third counter that counts up a third count value in synchronization with detection of the vertical synchronization signal by the detection means;
the third count value can transition to at least a first state or a second state;
the first timing is the timing at which the third count value transitions to the first state;
the second timing is the timing at which the third count value transitions to the second state;
a readout operation of a pixel for which a reset operation is performed in synchronization with the first count value among the plurality of pixels is performed in synchronization with the first count value;
2. The method according to claim 1, wherein a readout operation of a pixel for which a reset operation is performed in synchronization with said second count value among said plurality of pixels is performed in synchronization with said second count value. image sensor. the first state is a state in which the third count value is an even number;
3. The imaging device according to claim 2, wherein the second state is a state in which the third count value is an odd number. further comprising a third counter that counts up a third count value at the timing when the first count value is reset;
the first timing is the timing at which the vertical synchronization signal is detected by the detection means;
The second timing is timing when the third count value matches a predetermined value,
The reset operation of the pixels among the plurality of pixels started in synchronization with the first count value is synchronized with the second count value after the second count value is reset at the second timing. 2. The image pickup device according to claim 1, wherein the readout operation of the pixels is performed in synchronization with the second count value. 5. The imaging device according to claim 1, wherein the first period and the second period are the same period. 5. The imaging device according to claim 1, wherein the first period and the second period are different periods. The imaging device according to any one of claims 1 to 6, wherein the first cycle is changed by resetting the first count value at the first timing. The imaging device according to any one of claims 1 to 7, wherein the second period is changed by resetting the second count value at the second timing. An imaging device according to any one of claims 1 to 8;
and generating means for generating the vertical synchronization signal by operating with a clock asynchronous to clocks for operating the first and second counters.

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