JP2003259230A - Drive control circuit of solid-state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a random trigger shutter function with high stability. <P>SOLUTION: A normal drive control part 4 generates a shutter pulse SUB1, a read pulse SG1 and a drive pulse V1 at each cycle of a vertical synchronizing signal VD, and a selection circuit 8 always selects the pulses and supplies the selected pulses to a solid-state image pickup device. When a trigger signal TRIG is inputted, a trigger drive control part 6 enters a trigger drive mode, and a control signal generation circuit 18 generates and outputs a shutter pulse signal SUB2, a read pulse SG2 and a drive pulse V2. Meanwhile, a switching control circuit 20 outputs a select signal 24 for selecting each pulse from the trigger drive control part 6. As a result, the selection circuit 8 selects the respective pulses SUB2, SG2 and V2 outputted by the control signal generation circuit 18 and supplies the selected pulses to the solid-state image pickup device. Since the normal drive control part 4 and the trigger drive control part 6 are independently provided, the system is simple and a logical deficiency hardly occurs. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive control circuit for a solid-state image pickup device, and more particularly to a drive control circuit for a solid-state image pickup device having a random trigger shutter function.

[0002]

2. Description of the Related Art FIG. 5 is a schematic plan view showing an example of a conventional interline solid-state image pickup device having a CCD structure. As shown in FIG. 5, the conventional solid-state imaging device 102
Is a large number of optical sensors 1 provided on the semiconductor substrate 104.
06 (photodiode), vertical charge transfer register 1
08, horizontal charge transfer register 110 and the like. The optical sensors 106 are arranged in a matrix, and the vertical charge transfer registers 108 are the optical sensors 10.
Each of the six columns extends along the column of the optical sensor 106. The horizontal charge transfer register 110 is provided on one end side of the vertical charge transfer register 108 so as to be orthogonal to the vertical charge transfer register 108, that is, in the direction of the row of the photosensor 106, and the charge-voltage conversion is performed at the output end thereof. The floating diffusion unit 112 (FD unit 11
2) is provided. The image signal generated by the FD unit 112 is output to the outside of the solid-state image sensor 102 through the output circuit 114 with low impedance.

On the charge transfer paths of the vertical charge transfer register 108 and the horizontal charge transfer register 110, transfer electrodes (not shown) composed of pairs of transfer electrodes and storage electrodes are arranged in the charge transfer direction in each transfer register. By applying a drive pulse to these electrodes, the signal charges are transferred on the transfer register.

In this example, the signal charge received by each photosensor 106 is generated by applying a read pulse to the transfer electrode of the vertical charge transfer register 108 so that each column of the photosensor 106 has a vertical charge transfer register. 1
The data is simultaneously read out to the vertical charge transfer register 108 through a read-out gate unit (not shown) between the light sensor 08 and the photosensor 106. Then, the vertical charge transfer register 10
8 is driven by applying a drive pulse to its transfer electrode, the signal charges read from the photosensor 106 are sequentially transferred onto the vertical charge transfer register 108 toward the horizontal charge transfer register 110, and the photosensor 1 of 106
The signal charges for each row are supplied to the horizontal charge transfer register 110.

The signal charges for one row of the photosensors supplied to the horizontal charge transfer register 110 are sequentially driven toward the FD section 112 on the horizontal charge transfer register 110 by driving the horizontal charge transfer register 110 with a driving pulse. F is transferred from the end of the horizontal charge transfer register 110.
It is output to the D section 112. The signal charge is converted into a voltage in the FD section 112, and is output from the output circuit 114 as an image signal to the outside with low impedance.

The read pulse is supplied to the vertical charge transfer register 108 in synchronization with the vertical sync signal, and the vertical charge transfer register 108 is synchronized with the vertical sync signal.
The transfer of the signal charge at is started. The vertical synchronizing signal is generated for each predetermined number of horizontal synchronizing signals, and the drive pulse applied to the transfer electrode of the vertical charge transfer register 108 is a pulse of, for example, four phases having the same period as the horizontal synchronizing signal.

The electronic shutter in the solid-state image pickup device 102 is performed by applying a shutter pulse to the substrate 104 and discarding the signal charge accumulated in the optical sensor 106. The shutter pulse is applied to the semiconductor substrate 104 in synchronization with the horizontal synchronizing signal, and the application of the shutter pulse is stopped and the exposure start timing is set after the set time elapses for each cycle of the vertical synchronizing signal. To be done. Then, after stopping the application of the shutter pulse,
The exposure time is the time until the read pulse is supplied to the vertical charge transfer register. During this time, the signal charge accumulated in the photosensor 106 is read out to the vertical charge transfer register 108 side by the application of the read pulse.
Timing of last application of shutter pulse (thus timing of stopping application of shutter pulse)
Is determined by counting the horizontal synchronizing signal, and the exposure time of the optical sensor 106 can be adjusted by setting variously the number of horizontal synchronizing signals to be counted.

[0008]

By the way, when an image of a subject moving at high speed is taken, for example, when the subject enters the image pickup range of the camera, it is necessary to immediately release the shutter. The timing of starting exposure and the timing of ending exposure must be set independently of the vertical synchronization signal. Such functions are factory automation (FA)
It is particularly important in a camera device or the like for use, and is realized as a random trigger function of immediately capturing an image of a subject when a trigger signal is input at any timing.

The shutter pulse and the read pulse as described above are generated by the drive control circuit of the solid-state image pickup device 102, and the conventional drive control circuit always generates the shutter pulse and the read pulse in synchronization with the vertical synchronizing signal. On the other hand, when performing a random trigger shutter,
The operation is changed and the solid-state image sensor 102 is controlled according to the trigger signal.

However, since the timing at which the trigger signal is input is not constant with respect to the vertical synchronizing signal and the horizontal synchronizing signal, various cases must be assumed in the design of the drive control circuit. As a result, the structure of the drive control circuit becomes complicated, which tends to cause a logical defect, and there is room for improvement in terms of stability.

The present invention has been made to solve such a problem, and an object thereof is to provide a drive control circuit for a solid-state image pickup device having a highly stable random trigger shutter function.

[0012]

In order to achieve the above object, the present invention provides a solid-state image pickup device which picks up an image of a subject by a plurality of optical sensors and outputs an image signal representing a picked-up image in synchronization with a first synchronizing signal. On the other hand, in order to supply a signal for driving and controlling the solid-state imaging device, a synchronization signal generating circuit for generating the first synchronization signal and a predetermined timing from the start timing of the same period for each period of the first synchronization signal. A first shutter signal generation circuit that generates a first shutter signal that determines the timing of starting the exposure of the optical sensor when the time has elapsed, and the first shutter signal generation circuit outputs the first shutter signal. And a first read signal generation circuit for generating a first read signal that determines the timing of ending the exposure of the optical sensor when a designated time has elapsed after the generation. A drive control circuit for a solid-state image pickup device, comprising a normal drive control unit, wherein when a trigger signal is input, a second shutter signal that generates a second shutter signal that determines the exposure start timing of the optical sensor A generation circuit and a second read signal that determines the timing of ending the exposure of the optical sensor when a designated time has elapsed after the second shutter signal generation circuit generated the second shutter signal. A trigger drive control unit including a second read signal generation circuit, and any one of the first shutter signal and the first read signal, the second shutter signal and the second read signal. Selecting circuit based on a select signal and supplying the solid-state image sensor with the selection circuit, and the second signal after the trigger signal is input. The second shutter signal and the second read signal until the read signal generation circuit generates the second read signal and the synchronization signal generation circuit first generates the first sync signal. And a switching control circuit that supplies the select signal for selecting to the select circuit.

In the drive control circuit of the solid-state image pickup device according to the present invention, the second shutter signal generation circuit of the trigger drive control section determines the second shutter timing for determining the exposure start timing of the optical sensor when the trigger signal is input. The second read signal generating circuit generates a signal, and the second read signal generating circuit generates the second shutter signal after the second shutter signal generating circuit generates the second shutter signal.
When the designated time has elapsed, a second read signal that determines the timing of the end of exposure of the photosensor is generated. Then, the switching control circuit, after the trigger signal is input,
The second shutter signal and the second read signal are selected until the second read signal generation circuit generates the second read signal and the synchronization signal generation circuit first generates the first sync signal. To the selection circuit, and the selection circuit selects the second shutter signal and the second readout signal according to the selection signal and supplies the selected second shutter signal and the second readout signal to the solid-state imaging device.

Therefore, in the present invention, in the normal state in which the trigger signal is not input, the first shutter signal generating circuit and the first read signal generating circuit of the normal drive control section generate the first shutter signal and the first shutter signal, respectively. The read signal of 1 is supplied to the solid-state image sensor through the selection circuit, and the solid-state image sensor is drive-controlled by these signals. On the other hand, when the trigger signal is input, the second shutter signal and the second read signal generated by the second shutter signal generation circuit and the second read signal generation circuit of the trigger drive control unit are transferred to the solid state through the selection circuit. The solid-state image sensor is supplied to the image sensor, and the solid-state image sensor is driven and controlled by these signals, whereby the random trigger shutter function is realized.

Then, while the solid-state image pickup device is driven and controlled by the signal generated by the trigger drive control unit, the signals generated by the first shutter signal generation circuit and the first read signal generation circuit of the normal drive control unit are Since it is not selected by the selection circuit, the normal drive control unit may operate normally to generate each signal, and switching of the operation is not necessary at all.

As described above, the drive control circuit of the present invention is provided with the trigger drive control section in addition to the normal drive control section, and when the trigger signal is input, the trigger drive is performed from the signal generated by the normal drive control section. Since the configuration is such that the solid-state imaging device is driven by switching to the signal generated by the control unit, the system is simple and clear, and malfunctions due to logical defects are unlikely to occur, and the trigger signal is relative to the first synchronization signal. Stable operation is possible even when input at various timings.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an example of a drive control circuit for a solid-state image sensor according to the present invention, and FIG. 2 is a timing chart showing the operation of the drive control circuit according to the embodiment. The drive control circuit 2 for a solid-state image sensor according to the present embodiment is an example of the solid-state image sensor 10 shown in FIG.
As shown in FIG. 1, the drive control unit 2 includes a normal drive control unit 4, a trigger drive control unit 6, and a selection circuit 8, and further includes a synchronization signal generation circuit 10 and a clock counter 12. .

The normal drive control section 4 includes a control signal generation circuit 14 (first read signal generation circuit according to the present invention) and a shutter pulse generation circuit 16 (first shutter signal generation circuit according to the present invention) which cooperate with each other. ), The control signal generation circuit 14 applies the four-phase drive pulse V1 applied to the transfer electrodes of the vertical charge transfer register 108 (FIG. 5) during normal driving and the signal charge generated by the optical sensor 106 to the vertical charge transfer register. Read out pulse S read out to 108
G1 is generated. On the other hand, the shutter pulse generation circuit 16
Generates a shutter pulse SUB1 to be applied to the semiconductor substrate 104 during normal driving.

The trigger drive control section 6 comprises a control signal generation circuit 18 and a switching control circuit 20 which cooperate with each other.
The control signal generation circuit 18 includes a four-phase drive pulse V2 applied to the transfer electrodes of the vertical charge transfer register 108) in order to discard unnecessary signal charges accumulated in the vertical charge transfer register 108 at the time of trigger driving, and an optical sensor. A read pulse SG2 for reading the signal charge generated by 106 to the vertical charge transfer register 108 and a shutter pulse SUB2 applied to the semiconductor substrate 104 are generated. On the other hand, the switching control circuit 20 supplies the selection signal 24 to the selection circuit 8.

The selection circuit 8 includes the drive pulse V1, the read pulse SG1, the shutter pulse SUB1, the drive pulse V2, and the read pulse SG which are generated by the normal drive control unit 4 and the trigger drive control unit 6, respectively.
2 and the shutter pulse SUB2 are switched based on the select signal 24 from the switching control circuit 20 and are supplied to the solid-state image sensor 102 as the drive pulse V, the read pulse SG, and the shutter pulse SUB.

The synchronizing signal generation circuit 10 uses the vertical synchronizing signal VD.
(First synchronization signal according to the present invention) and horizontal synchronization signal H
D (second synchronization signal according to the present invention) is generated and supplied to the normal drive control unit 4, the trigger drive control unit 6, and the clock counter 12, and the clock counter 12 determines the timing within each cycle of the horizontal synchronization signal. The basic clock is counted in order to measure, and the result is supplied to the normal drive control unit 4 and the trigger drive control unit 6. The normal drive control unit 4 and the trigger drive control unit 6 are supplied with the normal drive setting data 26 and the trigger drive setting data 28, respectively, and the trigger drive control unit 6 is externally supplied with the trigger signal TRIG.

Next, the operation of the drive control circuit 2 of the solid-state image pickup device thus configured will be described with reference to FIG. In the operation example of FIG. 2, the drive control circuit 2 operates in the trigger drive mode in the period of timings T1 and T2, and operates in the normal drive mode in the other periods. First, the operation in the normal drive mode will be described with particular reference to timing T2 and thereafter.

In the normal drive mode, the switching control circuit 20 outputs the low-level select signal 24, which causes the selection circuit 8 to select and output the signal output by the normal drive control unit 4, and thus the solid-state image pickup. The drive of the element 102 is normally controlled by the drive control unit 4. The shutter pulse generation circuit 16 of the normal drive control unit 4 is the synchronization signal generation circuit 1
When the vertical sync signal VD is input from 0, a normal drive data capture pulse is internally generated at the falling timing, and the normal drive setting data 2 is generated at that timing.
Take in 6. This data 26 is stored in the optical sensor 106.
Horizontal sync signal H to determine the timing of the exposure start of
It contains the number of information to count D.

Then, the shutter pulse generation circuit 16
Is a shutter pulse SUB in synchronization with the horizontal synchronizing signal HD.
1 is generated, but after the falling timing of the vertical synchronizing signal VD, the horizontal synchronizing signal HD supplied from the synchronizing signal generating circuit 10 is counted by an internal counter, and the counting result indicates the horizontal value represented by the normal setting drive data 28. When the sync signal HD matches the number to be counted, the output of the shutter pulse SUB1 is stopped, and then the read pulse SG1 (S
After G) is generated, the output of the shutter pulse SUB1 is restarted. The selection circuit 8 has such a shutter pulse S
Solid-state image sensor 1 using UB1 as shutter pulse SUB
Supply to 02. Therefore, signal charges are accumulated in the optical sensor 106 during the period I1 in which the SUB1 is not output, and the shutter pulse SUB1 (SUB) finally output by the shutter pulse generation circuit 16 in each cycle of the vertical synchronization signal VD is generated. , And becomes a signal for determining the timing of starting the exposure of the optical sensor 106.

The control signal generation circuit 14 controls the vertical synchronizing signal V
After the falling edge of D, a predetermined number of horizontal synchronizing signals HD are counted to generate a read pulse SG1, and the selection circuit 8 supplies this pulse to the solid-state image sensor 102 as a read pulse SG. Then, in the solid-state imaging device 102, when the read pulse SG is input, the signal charge accumulated in the photosensor 106 is read to the corresponding vertical charge transfer register 108 side at that timing.

The control signal generation circuit 14 also generates a four-phase drive pulse V1 in synchronization with the horizontal synchronization signal HD, and the selection circuit 8 supplies this to the solid-state image sensor 102 as a drive pulse V. Therefore, in the solid-state image sensor 102,
In each period of the vertical synchronizing signal VD, signal charges are accumulated in each photosensor 106 during the period from the last supplied shutter pulse SUB to the supply of the read pulse SG, and the read pulse SG is input to this signal charge. By the way, the charges are read out to the vertical charge transfer register 108, and the vertical charge transfer register 108 is driven by the drive pulse V to transfer the signal charges. In the normal drive mode, such an operation is basically repeated for each cycle of the vertical synchronizing signal VD, and the subject is imaged.

Next, the operation in the trigger drive mode will be described. When the trigger signal TRIG is input at an arbitrary timing T1 ′, the trigger drive control unit 6
A trigger drive data fetch pulse is internally generated at the timing of the next horizontal synchronizing signal HD, and the trigger drive setting data 28 is fetched at the timing T1 (timing at which the trigger drive mode starts). At this time, the switching control circuit 20 switches the select signal 24 from the low level to the high level, and as a result,
The selection circuit 8 selects the drive pulse V2, the read pulse SG2, and the shutter pulse SUB2 output by the trigger drive control unit 6 and supplies them to the solid-state image sensor 102.

The control signal generation circuit 18 has a timing T1.
Then, a four-phase drive pulse V2 for sweeping out the signal charges accumulated in the vertical charge transfer register 108 is generated for a certain period, and the selection circuit 8 outputs this as a drive pulse V to the solid-state image sensor 102. . The drive pulse V2 has a significantly shorter cycle than the drive pulse V1 generated by the control signal generation circuit 18, and therefore the vertical charge transfer register 1
The signal charge accumulated in 08 is swept out at high speed. The control signal generation circuit 18 sets the period for outputting the drive pulse V2 for high-speed sweeping based on the information contained in the trigger drive setting data 28.

The control signal generating circuit 18 also operates as the second shutter signal generating circuit according to the present invention, and after the timing T1, generates the shutter pulse SUB2 in synchronization with the horizontal synchronizing signal HD, but from the timing T1. The horizontal synchronizing signal HD is counted by an internal counter, and when the count result matches the count value of the horizontal synchronizing signal HD for determining the exposure start timing, which is represented by the trigger drive setting data 28, the output of the shutter pulse SUB2 is stopped. .
The selection circuit 8 supplies this shutter pulse SUB2 as the shutter pulse SUB to the solid-state image sensor 102. Therefore, in the solid-state image sensor 102, after the timing T3 of the last shutter pulse SUB2, each optical sensor 10 is operated.
The exposure of 6 will be started.

The control signal generating circuit 18 also operates as the second read signal generating circuit according to the present invention after the timing T1 to count the horizontal synchronizing signal HD by an internal counter, and the count result is trigger-driven. Setting data 2
When the count value of the horizontal synchronizing signal HD for determining the exposure end timing represented by 8 coincides with the read pulse SG2
To occur. The selection circuit 8 supplies the read pulse SG2 as the read pulse SG to the solid-state image sensor 102, and the solid-state image sensor 102 outputs the read pulse SG2.
Is input, the signal charges accumulated by the photosensors 106 in the exposure period I2 to capture the image of the subject are read out to the vertical charge transfer register 108, and the exposure of the photosensors 106 is completed.

Then, the switching control circuit 20 receives the first vertical synchronizing signal after the control signal generating circuit 18 has generated the read pulse SG2, and thereafter selects the select signal 24 when the predetermined number of horizontal synchronizing signals HD are counted. Back to low level. This ends the trigger drive mode,
The selection circuit 8 selects the drive pulse V1, the read pulse SG1, and the shutter pulse SUB1 generated by the normal drive control unit 4, and supplies them to the solid-state image sensor 102. Here, since the drive pulse V1 is supplied to the solid-state image sensor 102, the signal charge taken into the vertical charge transfer register 108 as an imaging result in the trigger drive mode is generated by the vertical charge transfer register 108 in the subsequent cycle of the vertical synchronization signal. The image signal of the subject that has been transferred and finally captured by trigger driving is output from the solid-state image sensor 102.

Depending on the length of the exposure period I2 and the like, the vertical synchronizing signals VDa and VDb are input within the period of the trigger drive mode as shown in FIG. 2, but as is clear from the above description, Since the trigger drive control unit 6 is affected by the vertical synchronization signal VD only after the read pulse V2 is generated after the timing T1, the vertical synchronization signals VDa and VDb input on the way are invalid for the trigger drive control unit 6. These synchronization signals do not change the operation of the solid-state imaging device 102.

As described above, in the drive control circuit 2 of the solid-state image pickup device 102 of the present embodiment, the shutter pulse generation circuit 16 and the control signal of the normal drive control section 4 are in the normal state where the trigger signal is not input. Generation circuit 1
The shutter pulse and the read pulse generated by 4 are supplied to the solid-state image sensor 102 through the selection circuit 8, and the solid-state image sensor 102 is drive-controlled by these signals. On the other hand, when the trigger signal is input, the shutter pulse and the read pulse generated by the control signal generation circuit 18 of the trigger drive control unit 6 are supplied to the solid-state image sensor 102 through the selection circuit 8 and the solid-state image sensor 102.
Are controlled by these signals to realize a random trigger shutter function.

While the solid-state image pickup device 102 is driven and controlled by the signal generated by the trigger drive control unit 6, the signals generated by the shutter pulse generation circuit and the control signal generation circuit 14 of the normal drive control unit 4 are selected by the selection circuit. Since it is not selected in 8, the normal drive control unit 4 may operate normally to generate each signal, and switching of the operation is not necessary at all.

As described above, the drive control circuit 2 of this embodiment includes the trigger drive control unit 6 in addition to the normal drive control unit 4, and when the trigger signal is input, the normal drive control unit 4 is provided. Is configured to drive the solid-state image sensor 102 by switching from the signal generated by the trigger drive control unit 6 to the signal generated by the trigger drive control unit 6. Therefore, the system is simple and clear, and a malfunction due to a logical defect or the like is unlikely to occur. Even when signals are input at various timings with respect to the vertical synchronizing signal, more stable operation is possible.

Hereinafter, the trigger drive control section 6 which plays an important role in the present embodiment will be described in more detail. FIG. 3 is a block diagram showing in detail the trigger drive control unit 6 that constitutes the drive control circuit 2 of FIG. 1, and FIG. 4 is a timing chart showing the operation of the trigger drive control unit 6. The trigger drive controller 6 can be configured as shown in FIG. 3, and in this example, the trigger signal detection circuit 30, the final count value detection circuit 32, the counter 34, the data comparison circuit 36, the timing generation circuit 38, The control signal generation circuit 18 shown in FIG. 1 includes a switching circuit 40 and the like, and includes a counter 34, a data comparison circuit 36, and a timing generation circuit 38.
Reference numeral 0 includes a counter 34, a data comparison circuit 36, and a switching circuit 40.

In such a structure, in the normal drive mode, the switching circuit 40 has the high level trigger mask signal N.
15 is output, and as a result, the gate 42 and the gate 4 are output.
The counter 34 is reset through 4 and its count value is 0, and the enable signal EN output from the JK flip-flop 46 is at the low level, so the counter 34 stops operating.

Here, as shown in FIG. 4, when the trigger signal TRIG is input at the timing T1 ', the trigger mask signal N15 is at the high level, so that the trigger signal detection circuit 30 causes the trigger signal to fall. It detects and outputs a high-level detection pulse N12, and as a result, J
Since the K flip-flop 46 outputs the enable signal EN of high level, the counter 34 outputs the horizontal synchronizing signal H.
Start counting D. Further, the detection pulse N12 is also input to the switching circuit 40, whereby the switching circuit 40 switches the trigger mask signal N15 to the low level, and further switches the select signal 24 to the high level at the timing of the subsequent horizontal synchronizing signal HD. When the select signal 24 becomes high level, the selection circuit 8 (FIG. 1) selects the signal from the trigger drive control unit 6 to select the solid-state image pickup device 1.
Supply to 02. The counter 34 outputs a timing pulse N8 that becomes high level during one period of the horizontal synchronizing signal when the horizontal synchronizing signal HD is first counted,
The switching circuit 40 switches the select signal 24 to the high level at the rising timing of the pulse N8.

The trigger drive setting data 28 is data provided from a microcomputer (not shown) or the like, and includes high-speed sweep selection data N1, shutter timing data N2, and read timing data N3. High-speed sweep selection data N1
Is data representing the count value of the horizontal synchronization signal HD for designating the period for performing high-speed sweeping in the vertical charge transfer register 108, and the shutter timing data N2 is a measurement of the horizontal synchronization signal HD for determining the exposure start timing. It is data that represents a numerical value. Further, the read timing data N3 is data representing the count value of the flat sync signal HD for determining the timing (timing of ending exposure) of outputting the read pulse SG2.

The data comparison circuit 36 fetches and holds these data N1, N2, N3 at the timing of the horizontal synchronizing signal HD immediately after the fall of the trigger signal TRIG. Then, these data N1, N2, N3 are compared with the count value 48 of the counter 34, and the count value 48
When the count value 48 coincides with the value of the high-speed sweep selection data N1, the timing pulse N4 which becomes the high level for one cycle of the horizontal synchronization signal HD, and when the count value 48 matches the value of the shutter timing data N2, one cycle of the horizontal synchronization signal HD During this period, the timing pulse N5 that is at the high level and the timing pulse N6 that is at the high level during one cycle of the horizontal synchronizing signal HD when the count value 48 matches the value of the read timing data N3 (9 in this example) are generated. It is output to the timing generation circuit 38.

Based on these timing pulses N4, N5, N6, the timing generation circuit 38 uses the count result of the clock counter 12 to drive the drive pulse V2, the shutter pulse SUB2, and the shutter pulse SUB2 with the accuracy of the basic clock.
The read pulse SG2 is generated and supplied to the selection circuit 8.

When the count value of the counter 34 coincides with the largest count value among the high-speed sweep selection data N1, the shutter timing data N2, and the read timing data N3, the data comparison circuit 36 sets it to, for example, a high level. The final count value detection circuit 32 supplies the pulse N19 to the JK flip-flop 46 at this time to switch the enable signal EN output from the JK flip-flop 46 to the low level. Thereby, the unnecessary counting operation of the counter 34 can be stopped.

The trigger drive control section 6 is provided with a vertical sync signal detection circuit (not shown).
Is detected, and the detection signal N13 thereof is supplied to the switching circuit 40. Based on the detection signal N13, the switching circuit 40 switches the select signal 24 to the low level after the read pulse SG2 is generated.
Then, the switching circuit 40 internally generates the VD falling mask signal 49 (FIG. 4) which becomes a low level in the period from the falling of the trigger signal to the falling of the read pulse SG2 as shown in FIG. The detection signal N13 input during the period when this signal is low level is ignored. As a result, the vertical synchronizing signals VDa and VDb shown in FIG. 2 are invalidated. The data comparison circuit 36 generates the timing pulse N7 that becomes high level during one cycle of the horizontal synchronizing signal HD following the timing pulse N6, and the switching circuit 40 uses the timing pulse N7 to generate the mask signal. The timing when 49 is set to the high level is specified.

The switching circuit 40 also generates the trigger mask signal N15 which maintains the low level from timing T1 until the select signal 24 becomes the low level, and supplies it to the trigger signal detection circuit 30. When the trigger mask signal is low level, the trigger signal detection circuit 30 receives the trigger signal TRIG,
This is configured to be ignored, and as a result, even if the trigger signal TRIGa is input again during the period of the trigger drive mode shown in FIG. 2, the trigger drive control unit 6 is prevented from being restarted. it can.

To be exact, the switching circuit 40, together with the select signal 24, selects the select signal 24 as shown in FIG.
A slightly longer shutter pulse select signal 50 is generated. The selection circuit 8 uses the select signal 24 to drive pulses V1 and V2 and read pulses SG1 and SG2.
Shutter pulse SUB1, SUB2 while selecting
Is selected by the shutter pulse select signal 50. By using such a shutter pulse select signal 50, the shutter pulse SUB1 generated by the normal drive control unit 4 is generated in the solid state during the period of one cycle of the next horizontal synchronization signal HD after the period of the trigger drive mode ends. It is prevented from being supplied to the image sensor 102.
Further, the read position signal 51 of the normal drive shown in FIG.
Is a signal internally generated by the normal drive control unit 4, and the read pulse SG1 shown in FIG.
It is generated within a period in which 1 is at a high level. The timing at which the select signal 24 changes to low level coincides with the rising edge of the position signal 51.

[0046]

As described above, in the drive control circuit for a solid-state image pickup device according to the present invention, the second shutter signal generation circuit of the trigger drive control unit starts the exposure of the optical sensor when the trigger signal is input. A second read signal generation circuit generates a second shutter signal that determines the timing, and the second read signal generation circuit outputs a second shutter signal when the designated time elapses after the second shutter signal generation circuit generates the second shutter signal. A second read signal that determines the timing of ending exposure is generated. Then, in the switching control circuit, after the trigger signal is input, the second read signal generation circuit is set to the second read signal generation circuit.
The select signal for selecting the second shutter signal and the second read signal is supplied to the selection circuit until the sync signal generation circuit first generates the first sync signal The selection circuit selects the second shutter signal and the second readout signal according to the selection signal and supplies the second shutter signal and the second readout signal to the solid-state imaging device.

Therefore, in the present invention, in the normal state in which the trigger signal is not input, the first shutter signal generating circuit and the first read signal generating circuit of the normal drive control unit generate the first shutter signal and the first shutter signal, respectively. The read signal of 1 is supplied to the solid-state image sensor through the selection circuit, and the solid-state image sensor is drive-controlled by these signals. On the other hand, when the trigger signal is input, the second shutter signal and the second read signal generated by the second shutter signal generation circuit and the second read signal generation circuit of the trigger drive control unit are transferred to the solid state through the selection circuit. The solid-state image sensor is supplied to the image sensor, and the solid-state image sensor is driven and controlled by these signals, whereby the random trigger shutter function is realized.

While the solid-state image pickup device is being driven and controlled by the signal generated by the trigger drive control unit, the signals generated by the first shutter signal generation circuit and the first read signal generation circuit of the normal drive control unit are Since it is not selected by the selection circuit, the normal drive control unit may operate normally to generate each signal, and switching of the operation is not necessary at all.

As described above, the drive control circuit of the present invention is provided with the trigger drive control unit in addition to the normal drive control unit, and when the trigger signal is input, the trigger drive is performed from the signal generated by the normal drive control unit. Since the configuration is such that the solid-state imaging device is driven by switching to the signal generated by the control unit, the system is simple and clear, and malfunctions due to logical defects are unlikely to occur, and the trigger signal is relative to the first synchronization signal. Stable operation is possible even when input at various timings.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a drive control circuit for a solid-state image sensor according to the present invention.

FIG. 2 is a timing chart showing the operation of the drive control circuit according to the embodiment.

3 is a block diagram showing in detail a trigger drive control unit that constitutes the drive control circuit of FIG.

FIG. 4 is a timing chart showing the operation of the trigger drive control unit.

FIG. 5 is a schematic plan view showing an example of a conventional interline-type solid-state imaging device having a CCD structure.

[Explanation of symbols]

2 ... Drive control circuit, 4 ... Normal drive control unit, 6 ... Trigger drive control unit, 8 ... Selection circuit, 10 ... Synchronous signal generation circuit, 12 ... Clock counter, 14, 18 ...
... control signal generation circuit, 16 ... shutter pulse generation circuit, 20 ... switching control circuit, 26 ... normal drive setting data, 28 ... trigger drive setting data, 30 ... trigger signal detection circuit, 32 ... final total Numerical value detection circuit, 3
4 ... Counter, 36 ... Data comparison circuit, 38 ...
... Timing generation circuit, 40 ... Switching circuit, 102 ...
Solid-state image sensor, 106 ... Photosensor, 108 ... Vertical charge transfer register, 110 ... Horizontal charge transfer register.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yoko Terato             134, Kobe-cho, Hodogaya-ku, Yokohama-shi, Kanagawa               Sony LSI Design Stock Association             In-house F-term (reference) 4M118 AA10 AB01 BA13 DB09                 5C022 AA01 AA14 AB17 AB35 AB64                       AC42 AC69                 5C024 AX01 CX54 CX61 GX02 GY04                       GZ04 GZ18 HX50 JX46

Claims (6)

[Claims] 1. A signal for driving and controlling a solid-state image pickup device is provided to a solid-state image pickup device which picks up an image of a subject by a plurality of optical sensors and outputs an image signal representing the picked-up image in synchronization with a first synchronization signal. Therefore, the synchronization signal generation circuit for generating the first synchronization signal and the exposure start of the photosensor at a timing when a predetermined time has elapsed from the start timing of the same cycle for each cycle of the first synchronization signal. A first shutter signal generation circuit that generates a first shutter signal that determines timing; and the light when a specified time has elapsed after the first shutter signal generation circuit generated the first shutter signal. Drive control of a solid-state image sensor including a normal drive control unit including a first read signal generation circuit that generates a first read signal that determines the timing of exposure end of the sensor A second shutter signal generation circuit that generates a second shutter signal that determines a timing of starting exposure of the optical sensor when a trigger signal is input; and the second shutter signal generation circuit, A trigger drive control unit including a second read signal generation circuit that generates a second read signal that determines a timing of ending exposure of the optical sensor when a designated time has elapsed after the second shutter signal is generated. Further, the first shutter signal, the first read signal, the second shutter signal, and the second shutter signal.
And a selection circuit which supplies one of the read signals of the second read signal to the solid-state image pickup device, and the second read signal generation circuit outputs the second read signal after the trigger signal is input. To the selection circuit for selecting the second shutter signal and the second read signal until the synchronization signal generation circuit first generates the first synchronization signal. A drive control circuit for a solid-state image pickup device, comprising: a switching control circuit for supplying. 2. The synchronization signal generating circuit generates a second synchronization signal, and also generates the first synchronization signal each time a plurality of the second synchronization signals are generated. The second shutter signal generation circuit is the second
The first and second shutter signals are generated in synchronization with the first synchronization signal and the first and second read signal generation circuits are synchronized with the second synchronization signal.
2. The drive control circuit for the solid-state image pickup device according to claim 1, wherein the second read signal is generated. 3. The solid-state imaging device, wherein the photosensors are arranged in a matrix, and a vertical charge transfer register for transferring signal charges generated by the photosensors is provided for each column of the photosensors. The signal charge received and generated by each photosensor is read to the vertical charge transfer register corresponding to each column of the photosensors when the first or second read signal is supplied, and the signal charge is generated by each vertical charge transfer register. 3. The drive control circuit for a solid-state image pickup device according to claim 2, wherein the drive control circuit is transferred in synchronization with the second synchronization signal. 4. The solid-state imaging device has a horizontal charge transfer register at one end of the vertical charge transfer register,
4. The drive control circuit for a solid-state image sensor according to claim 3, wherein the signal charge transferred by the vertical charge transfer register is transferred by the horizontal charge transfer register for each row of the photosensor. 5. A first drive pulse for generating a first drive pulse to be supplied to the vertical charge transfer register to transfer the signal charge read from the photosensor to the vertical charge transfer register by the vertical charge transfer register. A drive pulse generating circuit; and a first drive for supplying signal charges remaining in the vertical charge transfer register to the vertical charge transfer register for high speed transfer and discard when the trigger signal is input. A second drive pulse generation circuit for generating a second drive pulse having a shorter cycle than the pulse, wherein the selection circuit outputs the first drive pulse together with the first shutter signal and the first read signal. The second drive pulse is selected and supplied to the solid-state image sensor, and the second drive pulse is selected together with the second shutter signal and the second read signal. Drive control circuit of the solid-state imaging device according to claim 3, wherein the supplying to said solid state imaging device with. 6. The drive control circuit for a solid-state image sensor according to claim 1, wherein the first and second shutter signals are signals for discarding signal charges accumulated in the photosensor.