JP2003259229A - Exposure time control circuit of solid-state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the scale and cost of a circuit. <P>SOLUTION: A load pulse LD is inputted, for example, in a 13-H (time for 13 cycles of a horizontal synchronizing signal) cycle, and exposure time data SHD is loaded to a 4-bit counter 14. The counter 14 counts the horizontal synchronizing signal, and when a count value becomes 15, an output of a comparator circuit 18 is inverted to generate an edge detection pulse 26, and a basic charge sweeping out pulse HSUB at its timing is outputted as a charge sweeping out pulse SUB from an AND circuit 28. When exposure time data is, for example, 0, an output of the counter 14 is not 15 because the cycle of the load pulse is 13H, and the edge detection pulse 26 is not generated. However, a read control pulse ROUT is inputted to an AND circuit 4 at the same timing as that of the load pulse, an XQ output being at a high level. Therefore, the pulse ROUT is supplied to the AND circuit 28 and the charge sweeping out pulse SUB is outputted. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure time control circuit for a solid-state image sensor.

[0002]

2. Description of the Related Art Solid-state image pickup devices are widely used as image pickup means for video cameras and electronic still cameras. Figure 3
FIG. 3 is a schematic plan view showing an example of this type of solid-state imaging device. The conventional solid-state image sensor 102 shown in FIG.
It is a solid-state image sensor of interline transfer type having a structure, and includes a large number of photosensors 106 (photodiodes) provided on a semiconductor substrate 104, a vertical charge transfer register 108, a horizontal charge transfer register 110, and the like. The photosensors 106 are arranged in a matrix, and the vertical charge transfer registers 108 are provided along the columns of the photosensors 106 for each column of the photosensors 106. The horizontal charge transfer register 110 is provided on one end side of the vertical charge transfer register 108 so as to be orthogonal to the vertical charge transfer register 108, that is, in the direction of the row of the photosensor 106, and the charge-voltage conversion is performed at the output end thereof. Floating diffusion unit 112
The (FD unit 112) is provided. The image signal generated by the FD unit 112 is output to the outside of the solid-state image sensor 102 through the output circuit 114 with low impedance.

On the charge transfer paths of the vertical charge transfer register 108 and the horizontal charge transfer register 110, transfer electrodes (not shown) composed of pairs of transfer electrodes and storage electrodes are arranged in the charge transfer direction in each transfer register. By applying a transfer pulse to these electrodes, the signal charges are transferred on the transfer register.

In this example, the signal charges received by the photosensors 106 are generated by applying a charge read pulse to the transfer electrodes of the vertical charge transfer register 108.
For each column of the photosensors 106, the data is simultaneously read to the vertical charge transfer registers 108 through a read gate unit (not shown) between the vertical charge transfer registers 108 and the photosensors 106. After that, the vertical charge transfer register 108 is driven by applying a transfer pulse to its transfer electrode, so that the signal charges read from the photosensor 106 are directed to the horizontal charge transfer register 110 on the vertical charge transfer register 108. The light sensor 106 is sequentially transferred.
Horizontal charge transfer register 11 for each signal charge of one row
Supplied to zero.

The signal charges for one row of the photosensors supplied to the horizontal charge transfer register 110 are sequentially driven toward the FD section 112 on the horizontal charge transfer register 110 by driving the horizontal charge transfer register 110 with a transfer pulse. F is transferred from the end of the horizontal charge transfer register 110.
It is output to the D section 112. The signal charge is converted into a voltage in the FD section 112, and is output from the output circuit 114 as an image signal to the outside with low impedance.

The charge read pulse is supplied to the vertical charge transfer register 108 in synchronization with the vertical sync signal, and the vertical charge transfer register 1 is synchronized with the vertical sync signal.
The transfer of signal charge at 08 is started. The vertical synchronizing signal is generated for every predetermined number of horizontal synchronizing signals, and the transfer pulse applied to the transfer electrode of the vertical charge transfer register 108 is a pulse of, for example, four phases having the same period as the horizontal synchronizing signal.

In the solid-state image pickup device 102, the electronic shutter is performed by applying a charge sweep pulse to the substrate 104 to discard the signal charge accumulated in the photosensor 106. This charge sweep pulse is applied at the time when a set time elapses from the vertical sync signal in each cycle of the vertical sync signal, and the time from the timing until the charge read pulse is supplied is the exposure time of the optical sensor 106. Becomes Then, during this period, the signal charge accumulated in the photosensor 106 moves to the vertical charge transfer register 108 side by applying a charge read pulse to the transfer electrode of the vertical charge transfer register 108 in synchronization with the vertical synchronization signal.

In the conventional solid-state image pickup device, the charge sweep pulse is applied to each horizontal synchronizing signal in synchronization with the horizontal synchronizing signal for a predetermined period from the vertical synchronizing signal. Due to the improved characteristics of the device, one charge sweeping operation is sufficient as described above.

FIG. 4 is a block diagram showing an example of a circuit for controlling the exposure time in such a solid-state image pickup device 102. 5 and 6 are timing charts showing the operation of the exposure time control circuit of FIG. As shown in FIG. 4, the conventional exposure time control circuit 12 includes a counter 14 that counts horizontal synchronizing signals, a limiting circuit 16 that limits the size of numerical data that represents the exposure time, and supplies the counter 14 with the numerical data. Comparator circuit 18 for comparing the count value of the counter with its maximum value, basic charge sweep-off pulse generation circuit 20
It is configured to include.

Here, as shown in FIG. 5, as an example, it is assumed that 13 horizontal synchronizing signals HD are included in one period of the vertical synchronizing signal VD, and the exposure time data SHD.
It is assumed that (supplied from a control device such as a microcomputer) is 4-bit data, and the counter 14 is a 4-bit counter. The load pulse LD is input to the counter 14 in synchronization with the vertical synchronizing signal VD, and when the load pulse LD is input, the counter 14 is loaded with the exposure time data SHD from the limiting circuit 16. Then, each time the horizontal synchronizing signal HD is input, the counter 14 uses the load value as an initial value to set the horizontal synchronizing signal HD.
Is counted and the count value is updated each time. The load pulse LD is supplied to the counter 14 at substantially the same timing as the charge read pulse SG shown in FIG. Therefore, the exposure time data SHD is loaded to the counter 14 in the cycle of the third horizontal synchronizing signal HD from the vertical synchronizing signal VD in this example.

The comparison circuit 18 and this count value and the maximum value of the count value, that is, Fh (h represents a hexadecimal number)
When the count value reaches Fh, the output is switched from the low level to the high level as an example. As a result, first, the XQ output of the D flip-flop 22, that is, the enable signal EN of the counter 14, changes from the high level to the low level, and as a result, the counter 14
Stops the counting operation until the exposure time data SHD is loaded next. On the other hand, since the output of the comparison circuit 18 has changed to the high level, the edge detection circuit 24 applies the edge detection pulse 26 that maintains the high level to one input terminal of the AND circuit 28 for one cycle of the horizontal synchronizing signal HD. Output.

The basic charge sweep-away pulse generation circuit 20 is
As shown in FIG. 6, for each horizontal synchronizing signal HD, a basic charge sweep-out pulse HSUB is generated at a timing delayed from the horizontal synchronizing signal HD by α time, and is supplied to the other input terminal of the AND circuit 28. There is. Therefore, when the edge detection circuit 24 outputs the edge detection pulse 26 as described above, the AND circuit 28 changes the basic charge sweep-out pulse HSUB output from the basic charge sweep-out pulse generation circuit 20 at that time to the charge sweep-out pulse SUB. Is output to the solid-state image sensor 102.

Since the basic charge sweep-out pulse HSUB is delayed from the horizontal synchronizing signal HD by α time as described above, the charge sweep-out pulse SUB is also a pulse delayed from the horizontal synchronizing signal HD by α time. . However, in FIG. 5, since the delay time is minute, it is ignored and the timing of the charge read pulse SUB is shown.

Since the exposure time control circuit 12 operates as described above, for example, the value of the exposure time data SHD is set to Ah.
In such a case, the count value of the counter 14 becomes maximum when five horizontal synchronizing signals are counted from the position of the charge read pulse SG, and the charge sweep pulse SUB is generated at the timing shown in FIG. In this example, a charge read pulse SG is generated by the charge read pulse generation circuit (not shown) from the vertical sync signal VD to the third horizontal sync signal HD. The exposure time EXP is up to the charge read pulse SG.

FIG. 7 is a graph showing the relationship between the exposure time EXP and the exposure time data SHD. In the figure, the horizontal axis represents the exposure time data SHD, and the vertical axis represents the exposure time EXP. In the exposure time control circuit 12, the exposure time EXP basically increases in proportion to the size of the exposure time data SHD.

The basic charge sweep-off pulse HSUB
More detailed timings of (the charge sweep pulse SUB) and the charge read pulse SG are as shown in FIG. FIG. 6 is an enlarged chart of a part of FIG. 5, in which the basic charge sweep-out pulse HSUB is generated at a timing delayed from the horizontal synchronizing signal HD by a slight time α, while the charge read pulse SG is horizontal synchronizing. When viewed in the period of one cycle of the signal HD, it is generated at a timing delayed by the time β from the basic charge sweep-out pulse HSUB. The basic charge sweep pulse HS
Since the timing relationship between the UB and the charge read pulse SG is as described above, the shortest exposure time is β
Becomes

[0017]

If the exposure time data SHD is set to 0h or 1h in an attempt to set the exposure time to a short time, the counter 14 is loaded with 0h or 1h. 14
When the horizontal synchronizing signal HD of 15 or 14 is counted, the count value becomes maximum. However, in the exposure time control circuit 12 of this example, since the number of horizontal synchronizing signals in one cycle of the vertical synchronizing signal VD is 13, the next load pulse LD is input before the count value of the counter 14 becomes maximum. As a result, the counter 14 is loaded with 0h or 1h again. As a result, the count value of the counter 14 does not reach the maximum value Fh, and the charge sweep-out pulse SUB is not generated.

In order to prevent such a problem, in the conventional exposure time control circuit 12, a limiting circuit 16 is provided to limit the exposure time data SHD and then the counter 14 is used.
To ensure that the charge sweep-off pulse SUB is generated. However, the number of horizontal synchronizing signals in one cycle of the vertical synchronizing signal VD may be changed by mode switching. Therefore, in order to cope with such mode switching, the number of horizontal synchronizing signals in one cycle of the vertical synchronizing signal VD is changed. It is necessary to provide a limiting circuit 16 for each mode according to the number of horizontal synchronizing signals or to switch the operation of the limiting circuit 16 according to the mode. Therefore, in the conventional exposure time control circuit 12, the circuit scale is increased and the cost is increased in relation to the limiting circuit 16.

In the exposure time control circuit 12, the exposure time data SHD is assumed to be 4-bit data, but in reality it is often about 8-bit data, and the limiting circuit 16 has a circuit scale of 4 bits. It's bigger than a bit. Therefore, the influence when the limiting circuit 16 is provided for each mode or when the operation is switched is larger than that in the case of 4 bits. Further, when the exposure time control circuit 12 is tested, the limiting circuit 16 must be tested for each mode, resulting in poor work efficiency. Further, in the circuit design, the design of the limiting circuit must be verified for each mode. It was troublesome.

The present invention has been made to solve such a problem, and its object is to reduce the exposure time of a solid-state image pickup device which realizes reduction of circuit scale and cost, and efficiency of circuit design and test. It is to provide a control circuit.

[0021]

In order to achieve the above object, the present invention provides a solid-state image pickup device which picks up an image of a subject in synchronization with a first synchronizing signal by a plurality of optical sensors and outputs an image signal representing the image pickup result. On the other hand, the charge synchronization pulse for sweeping out the signal charge accumulated in the photosensor and the charge reading pulse for reading out the signal charge accumulated in the photosensor to the transfer means to generate the image signal are synchronized with the first synchronization. An exposure time control circuit for a solid-state imaging device, which is generated in synchronization with a signal and supplies the charge sweep-out pulse and the charge read-out pulse in this order, wherein a value corresponding to the exposure time corresponds to the first synchronization signal. A counter that counts timing pulses that are loaded synchronously and have a shorter cycle than the first synchronization signal, and the count value of the counter reach a reference value. Then, if the count value of the counter does not reach the reference value by the timing at which the counter is loaded next, the first pulse generating means for outputting the charge sweep pulse, and the charge reading A second pulse generating means for generating the electric charge sweeping pulse at a timing immediately before the pulse.

In the exposure time control circuit of the present invention, the value corresponding to the exposure time is loaded into the counter in synchronization with the first synchronizing signal, and the counter then counts the timing pulse. Then, the first pulse generation means is
When the count value of the counter reaches the reference value, the charge sweep-off pulse is output, while the second pulse generating means does not reach the reference value by the time when the counter is next loaded. In this case, the charge sweep pulse is generated immediately before the charge read pulse.

Therefore, since the value corresponding to the exposure time loaded in the counter is inappropriate, the count value of the counter does not reach the reference value by the timing when the counter is next loaded, and Even when the pulse generation means does not output the charge sweep pulse, the second pulse generation means generates the charge sweep pulse at the timing immediately before the charge read pulse. Therefore, in the present invention, it is not necessary to provide a circuit for limiting the value corresponding to the exposure time loaded in the counter. As a result, for example, in the interline transfer type solid-state imaging device, one cycle of the vertical synchronization signal Even if the number of horizontal sync signals during the period is changed by mode switching, the problem of increasing the circuit size of the limiting circuit and increasing the cost does not occur as in the past, and the design and testing of the circuit is troublesome. It does not cause the problem of being overloaded.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an example of an exposure time control circuit of a solid-state image sensor according to the present invention, and FIG. 2 is a timing chart for explaining the operation of the exposure time control circuit of FIG. In FIG. 1, the same elements as those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted here.

As shown in FIG. 1, the exposure time control circuit 2 of the solid-state image pickup device of the embodiment is particularly different from the conventional exposure time control circuit shown in FIG. AND circuit 4 (AND) and OR circuit 6
(OR) is added. In the exposure time control circuit 2 of the present embodiment, the exposure time data SHD is directly input to the counter 14, and when the load pulse LD is input to the counter 14, the exposure time data SHD is received.
D is loaded on the counter 14 as it is. The exposure time data is 4-bit data, and the relationship between the value and the exposure time EXP is as shown in [Table 1]. In [Table 1], "H" represents the time of one cycle of the horizontal synchronizing signal HD, and thus "13H" represents the time of 13 cycles of the horizontal synchronizing signal HD, for example.
“12H” represents the time for 12 cycles of the horizontal synchronizing signal HD. Further, β in the table represents the minimum exposure time described with reference to FIG.

[0026]

[Table 1] As can be seen by referring to [Table 1], the exposure time data S
When HD is 2h, the exposure time is β, and in the range where the exposure time data SHD is larger than 2h, the exposure time EXP increases by 1H each time the exposure time data SHD increases by 1. On the other hand, the exposure time data SHD is 0
In the case of h and 1h, the exposure time EXP is β which is the minimum value.

The relationship between the exposure time data SHD and the exposure time EXP shown in [Table 1] can also be expressed by the following [Equation 1].

[0028] [Equation 1]   EXP = 13- (15-SHD) (SHD = Fh)   EXP = 13− (15−SHD) + β (2h ≦ SHD ≦ Eh)   EXP = β (0h ≦ SHD ≦ 1h)

The exposure time control circuit 2 of the embodiment also includes the AND circuit 4 and the OR circuit 6 as described above, and the XQ output of the D flip-flop 22 is provided to one input of the AND circuit 4. The read control pulse ROUT is supplied to the other input. The output of the AND circuit 4 is connected to one input of the OR circuit 6, and the output of the edge detection circuit 24 is supplied to the other input of the OR circuit 6. Read control pulse R
OUT is generated by a timing generation circuit (not shown), and is synchronized with each load pulse LD as shown in FIG. 2. Specifically, OUT is a period of one cycle of the basic charge sweep pulse HSUB including the load pulse LD. Is at a high level.

In such a configuration, the comparison circuit 18,
The edge detection circuit 24, the OR circuit 6, the basic charge sweep-out pulse generation circuit 20, and the AND circuit 28 constitute the first pulse generation means according to the present invention, and the comparison circuit 18, D
The flip-flop 22, the AND circuit 4, the OR circuit 6, the basic charge sweep-away pulse generation circuit 20, and the AND circuit 28 constitute second pulse generation means according to the present invention.

Next, the operation of the exposure time control circuit 2 will be described in detail. For example, assuming that the value of the exposure time data SHD is Ah, the operation of the exposure time control circuit 2 in this case is basically the same as that of the conventional exposure time control circuit shown in FIG. That is, this exposure time data S
HD is a vertical synchronization signal (first synchronization signal according to the present invention)
When the load pulse LD shown in FIG. 2 is input in synchronization with, the counter 14 is loaded and the counter 14 outputs this value as an initial value. The timing of the load pulse is almost the same as the timing of the charge read pulse SG shown in FIG.

The comparison circuit 18 outputs the output value A of the counter 14.
Although h is compared with the reference value Fh, since these two values do not match, the output of the comparison circuit 18 remains at the low level, and therefore the D flip-flop 22 outputs the high level XQ output signal, that is, the counter. The enable signal EN of 14 is output to the counter 14. Therefore, the counter 14 increments the count value by 1 each time the horizontal synchronizing signal HD (the second synchronizing signal according to the present invention, that is, the timing pulse according to the present invention) is input, and the charge read pulse shown in FIG. The count value of the counter 14 becomes maximum when five horizontal synchronizing signals are counted from the position of SG.

At this time, the comparison circuit 18 uses the counter 14
Since the output value of 1 matches the reference value Fh, the output is switched to the high level. As a result, the edge detection circuit 2
4 outputs an edge detection pulse 26 which maintains a high level for one cycle of the horizontal synchronizing signal HD, and the edge detection pulse 26 is supplied to one input terminal of an AND circuit 28 through the OR circuit 6. Therefore, at the timing of the edge detection pulse 26, the basic charge sweep pulse HSUB generated by the basic charge sweep pulse generation circuit 20 is generated.
However, the charge sweep pulse SUB through the AND circuit 28
(FIG. 5) is supplied to the solid-state image sensor 102. The period from the charge sweep-out pulse SUB to the next charge read pulse SG is the exposure time EXP. This exposure time is 8H + β as shown in [Table 1].
When the count value of the counter 14 reaches the maximum value, the output of the comparison circuit 18 becomes high level, and the XQ output of the D flip-flop 22 becomes low level. Therefore, the read control pulse ROUT passes through the AND circuit 4 and the OR circuit. It is never output to 6.

Next, the exposure time data SHD is 0h.
Alternatively, a case where 1 h is supplied to the counter 14 will be described. When the load pulse LD is input to the counter 14, the counter 14 takes in the exposure time data SHD having a value of 0h or 1h and outputs it as the initial value of the count value, and thereafter, it is counted every time the horizontal synchronization signal HD is input. Increase the value by one. However, the vertical sync signal VD of 1
Since the number of horizontal synchronizing signals during the cycle is 13 in this example, the maximum count value of the counter 14 is 13 or 14, and the maximum count value is before the next load pulse LD is input. It never becomes Fh. Therefore, in this case, the output of the comparison circuit 18 does not become high level, therefore the edge detection circuit 24 does not generate a detection pulse, and the XQ output of the D flip-flop 22 remains high level.

Since the XQ output of the D flip-flop 22 maintains the high level, when the read control pulse ROUT is input to the AND circuit 4 at the same timing as the load pulse LD, the read control pulse RO.
The UT is output to the OR circuit 6 through the AND circuit 4 and then input to the AND circuit 28. Therefore, the basic charge sweep-out pulse HSUB generated by the basic charge sweep-out pulse generation circuit 20 at the timing of the read control pulse ROUT is supplied to the solid-state image sensor 102 as the charge sweep-out pulse SUB through the AND circuit 28.

That is, in the present embodiment, even if the exposure time data SHD (0h, 1h), which originally does not output the charge sweep-out pulse SUB, is input to the counter 14, the charge is always charged at the timing of the next load pulse LD. The sweep-out pulse SUB is output and the minimum exposure time β is set.

Therefore, in the present embodiment, it is not necessary to provide a circuit for limiting the exposure time data SHD loaded in the counter 14, and as a result, the horizontal synchronizing signal during one cycle of the vertical synchronizing signal is obtained. Even when the number of C is changed by mode switching, the problem that the circuit scale of the limiting circuit 16 is increased and the cost is increased unlike the conventional case does not occur, and there is also a problem that it takes time to design and test the circuit. Does not happen.

In the present embodiment, the exposure time data SHD is 4-bit data, and the counter 14
However, the exposure time data and the number of bits of the counter are not limited to 4 bits, and the present invention is effective even if it is 8 bits. Although the comparator circuit 18 compares the count value of the counter 14 with the maximum value thereof, it compares the count value of the counter 14 with a predetermined reference value smaller than the maximum value, and when the count value of the counter 14 reaches the reference value, outputs the output value. Even in the case of inverting, the charge sweep-out pulse SUB can be similarly generated based on the present invention.

[0039]

As described above, in the exposure time control circuit of the present invention, the value corresponding to the exposure time is loaded into the counter in synchronization with the first synchronizing signal, and the counter then counts the timing pulse. . Then, the first pulse generation means outputs the charge sweep-away pulse when the count value of the counter reaches the reference value, while the second pulse generation means
The pulse generation means of (1) generates the charge sweep pulse at the timing immediately before the charge read pulse when the count value of the counter does not reach the reference value by the timing when the counter is next loaded.

Therefore, since the value corresponding to the exposure time loaded in the counter is inappropriate, the count value of the counter does not reach the reference value by the timing when the counter is next loaded, and Even when the pulse generation means does not output the charge sweep pulse, the second pulse generation means generates the charge sweep pulse at the timing immediately before the charge read pulse. Therefore, in the present invention, it is not necessary to provide a circuit for limiting the value corresponding to the exposure time loaded in the counter. As a result, for example, in the interline transfer type solid-state imaging device, one cycle of the vertical synchronization signal Even if the number of horizontal sync signals during the period is changed by mode switching, the problem of increasing the circuit size of the limiting circuit and increasing the cost does not occur as in the past, and the design and testing of the circuit is troublesome. It does not cause the problem of being overloaded.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of an exposure time control circuit for a solid-state image sensor according to the present invention.

FIG. 2 is a timing chart showing the operation of the exposure time control circuit of FIG.

FIG. 3 is a schematic plan view showing an example of a solid-state image sensor.

FIG. 4 is a block diagram showing an example of a conventional circuit that controls an exposure time in a solid-state image sensor.

5 is a timing chart showing the operation of the exposure time control circuit of FIG.

FIG. 6 is an enlarged timing chart of a part of FIG.

FIG. 7 is a graph showing the relationship between exposure time EXP and exposure time data SHD.

[Explanation of symbols]

2, 12 ... Exposure time control circuit, 4, 28 ... AND circuit, 6 ... OR circuit, 14 ... Counter, 16 ... Limiting circuit, 18 ... Comparison circuit, 20 ... Basic charge sweep pulse generation Circuit, 22 ... D flip-flop, 24 ...
... edge detection circuit, 26 ... edge detection pulse, 102
...... Solid-state image sensor, 104 …… Semiconductor substrate, 106 ……
Optical sensor, 108 ... Vertical charge transfer register, 11
0 ... Horizontal charge transfer register.

Claims (6)

[Claims] 1. A solid-state image pickup device which picks up an image of a subject in synchronization with a first synchronizing signal by a plurality of photosensors and outputs an image signal representing a picked-up result, sweeps away signal charges accumulated in the photosensors. The charge sweep pulse and the charge read pulse for reading out the signal charge accumulated in the photosensor to the transfer means to generate the image signal are the first pulse.
An exposure time control circuit for a solid-state imaging device, which is generated in synchronism with a synchronization signal of, and supplies the charge sweeping pulse and the charge reading pulse in this order, wherein a value corresponding to the exposure time is the first synchronization A counter that is loaded in synchronism with a signal and that counts a timing pulse having a shorter cycle than the first synchronization signal; and a counter that outputs the charge sweep pulse when the count value of the counter reaches a reference value. 1 pulse generating means, and when the count value of the counter does not reach the reference value by the time when the counter is next loaded, the charge sweep pulse is generated at the timing immediately before the charge read pulse. An exposure time control circuit for a solid-state image pickup device, comprising: a second pulse generating means for generating. 2. The first pulse generating means includes a comparison circuit for comparing the count value of the counter and the reference value, and the count value of the counter is set to the reference value based on the comparison result by the comparison circuit. The exposure time control circuit for a solid-state image sensor according to claim 1, wherein it is determined whether or not it has arrived. 3. The second pulse generating means includes a comparison circuit for comparing the count value of the counter with the reference value, and the count value of the counter is set to the reference value based on the comparison result by the comparison circuit. The exposure time control circuit for a solid-state image sensor according to claim 1, wherein it is determined whether or not it has arrived. 4. In the solid-state imaging device, the photosensors are arranged in a matrix, and a vertical charge transfer register for transferring signal charges generated by the photosensors is provided for each column of the photosensors. The signal charge received and generated by each photosensor is read to the corresponding vertical charge transfer register for each column of the photosensor when the charge read pulse is supplied, and each vertical charge transfer driven by the transfer pulse is performed. The exposure time control circuit for a solid-state image pickup device according to claim 1, wherein the exposure time control circuit is transferred by a register. 5. The solid-state imaging device has a horizontal charge transfer register at one end of the vertical charge transfer register,
The exposure time control circuit of the solid-state imaging device according to claim 4, wherein the signal charges transferred by the vertical charge transfer register are transferred by the horizontal charge transfer register for each row of the photosensor. 6. The solid state device according to claim 4, wherein the transfer pulse has the same cycle as the second synchronization signal, and the second synchronization signal is supplied to the counter as the timing pulse. Exposure time control circuit for image sensor.