JP2003257977A - Forming method of wiring structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a short circuit between wirings embedded in an insulating film and an ARL film thereon. <P>SOLUTION: After a plurality of trenches 111 for wiring are formed in an FSG film 109 and an ARL film 110 formed on a substrate 100, a barrier metal film (tantalum nitride film 112) and conducting films for wiring (copper films 113 and 114) are deposited in sequence on the ARL film 110, in such a manner that each of the trenches 111 is completely filled. After that, the copper films 113 and 114 outside each of the trenches 111 are eliminated by polishing, and the tantalum nitride film 112 outside each of the trenches 111 is eliminated by polishing. After foreign matters stuck to the substrate 100 in the polishing are eliminated, the surface of the ARL film 110 is polished. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring structure in a semiconductor device.

[0002]

2. Description of the Related Art As a conventional method for forming a wiring structure, for example, the method described in Patent Document 1 has been used. This conventional method of forming a wiring structure will be described with reference to the drawings, taking as an example the case of forming a plug in a hole formed in an insulating film.

9A to 9C are cross-sectional views showing the steps of a conventional method for forming a wiring structure.

First, as shown in FIG. 9A, a silicon oxide film 12 having a thickness of about 1 μm is deposited as an insulating film on a silicon substrate 11, and then the silicon oxide film 12 is formed by a lithography method and a dry etching method. A hole 13 having a diameter of about 0.8 μm and penetrating the oxide film 12 in a predetermined area of
To form.

Next, the silicon oxide film 1 including the holes 13 is formed.
PVD (physical vapor depos
ition) method, a titanium film 14 having a thickness of 30 nm, which is a lower conductive film, and a film having a thickness of 100 n, which is a conductive film of an intermediate layer.
m titanium nitride film 15 is sequentially deposited. Then, CVD (chemical vapor deposition) is performed over the entire surface of the titanium nitride film 15.
or deposition) method, the film thickness of the upper conductive film is 1
A μm tungsten film 16 is deposited. This makes 3
A layered conductive film is deposited. Here, the titanium film 14 and the titanium nitride film 15 are barrier metals.

Next, as shown in FIG. 9B, the tungsten film 16 deposited on the region outside the hole 13 by the chemical mechanical polishing (CMP) method using one abrasive.
And the titanium nitride film 15 is removed. As a result, the titanium film 14 deposited in the region outside the hole 13 is completely exposed.

Next, as shown in FIG. 9C, the titanium film 14 deposited in the region outside the hole 13 is removed by the CMP method using another polishing agent. As a result, the plug 17 made of tungsten is formed in the hole 13 and the silicon oxide film 12 is exposed.

Although the formation of the tungsten plug has been described above as an example, a copper wiring can be formed in the wiring groove formed in the insulating film by the same method.

Further, with the miniaturization of wiring patterns, the spacing between adjacent wirings (wiring spacing) is becoming narrower. Therefore, in the lithography process for forming wiring trenches or via holes, antireflection is prevented. Membrane (hereinafter ARL
(Anti reflection layer) film is being used).

[0010]

[Patent Document 1] Japanese Unexamined Patent Application Publication No. 10-214834

[0011]

However, in the method of forming a wiring using the ARL film based on the above-mentioned conventional method of forming a wiring structure, there is a problem that a short circuit occurs between the wirings.

In view of the above, it is an object of the present invention to prevent a short circuit between wirings embedded in an insulating film and an ARL film on the insulating film.

[0013]

In order to achieve the above object, the inventors of the present invention have investigated the cause of a short circuit between wirings in the above-mentioned conventional method of forming a wiring structure, and as a result, I obtained such knowledge.

That is, when the wiring is formed according to the conventional wiring structure forming method, the barrier metal is locally peeled off during polishing of the barrier metal to become a foreign substance. Since this foreign substance is hard, when an ARL film made of a material weaker than the insulating film is formed on the insulating film existing between the wirings, a minute crack is generated on the surface of the ARL film. When the crack extends from one wiring to another wiring adjacent to the one wiring, a metal (barrier metal or a part of the conductive film for wiring) is embedded in the crack when the wiring is formed. A short circuit occurs between the wiring.

As the wiring structure becomes finer, the distance between the wirings becomes smaller, so that the above-mentioned cracks easily extend between the wirings. Therefore, the metal embedded in the cracks causes a gap between the wirings. A pseudo crosslinked structure is easily formed. That is, a short circuit easily occurs between the wirings.

FIG. 10 is a plan view showing a state in which a metal is embedded in a crack formed in an ARL film between wirings. Figure 10
As shown in FIG. 5, a plurality of copper wirings 22 are embedded in the ARL film 21 so as to extend parallel to each other. Copper wiring 22
A crack 23 is formed in the ARL film 21 between them so as to extend over the wiring. In this crack 23, the copper wiring 22
Copper is embedded during the formation of the copper wire, resulting in a short circuit between the copper wirings 22.

The present invention has been made on the basis of the above findings. Specifically, in the method for forming a wiring structure according to the present invention, after the antireflection film is formed on the insulating film, the antireflection film is formed. A groove forming step of forming a first groove and a second groove adjacent to the first groove in the film and the insulating film, and on the antireflection film so that the first groove and the second groove are filled. After the film deposition step of depositing the barrier metal film and the conductive film, the first polishing step of removing the conductive film outside the first groove and the outside the second groove by polishing, and after the first polishing step. A second polishing step of removing the barrier metal film outside the first groove and the outside of the second groove by polishing, and a foreign matter removing foreign matter attached to the surface to be polished after the second polishing step. And a third polishing step of polishing the surface of the antireflection film after the removal step and the foreign matter removal step. There.

According to the method for forming a wiring structure of the present invention, after the barrier metal film and the conductive film are sequentially embedded in the groove provided in the insulating film and the antireflection film thereon, the conductive film and the barrier metal outside the groove are formed. The film is removed by polishing. afterwards,
After removing foreign matters adhering to the surface to be polished during polishing, the surface of the antireflection film is polished. Therefore, when polishing the barrier metal film, a minute crack is generated on the surface of the antireflection film existing between the grooves (that is, between the wirings), and when the metal is embedded in the crack, the following effects are obtained. Is obtained. That is, since the foreign substances adhering to the surface to be polished are removed after the barrier metal film is polished, the surface of the antireflection film is subjected to final polishing, so that the foreign substances are prevented from newly damaging the surface of the antireflection film. However, the metal embedded in the crack can be removed. Therefore, it is possible to avoid a situation in which the wirings are bridged by the metal embedded in the cracks, and it is possible to reduce the frequency of occurrence of a short circuit between the wirings, so that high-performance wirings can be formed.

In the method for forming a wiring structure of the present invention, a step of removing foreign matters attached to the polishing pad used in the second polishing step is provided between the second polishing step and the third polishing step. Is preferred.

In this way, when the polishing pad used in the second polishing step (polishing the barrier metal film) is also used in the third polishing step (polishing the antireflection film), the surface of the antireflection film is damaged. This can be prevented more reliably. In this case, if the step of removing the foreign matter attached to the polishing pad includes the step of cleaning the polishing pad, it is possible to more reliably prevent the surface of the antireflection film from being damaged. The same effect can be obtained when the step of removing foreign matter attached to the polishing pad includes the step of brushing the surface of the polishing pad with a grindstone.

In the method for forming a wiring structure of the present invention, it is preferable that the second polishing step and the third polishing step are performed using the same polishing apparatus and polishing pad.

In this way, the work efficiency in wiring formation can be improved.

In the method for forming a wiring structure of the present invention, it is preferable that the pressure for pressing the substrate against the polishing pad and the rotation speed of the polishing pad in the third polishing step are the same as those in the second polishing step.

In this way, since it is not necessary to make complicated changes in the polishing conditions when shifting from the second polishing step to the third polishing step, workability in wiring formation can be improved, and This can prevent a decrease in process throughput. At this time, if the polishing time of the third polishing step is shorter than that of the second polishing step, it is possible to prevent the surface of the antireflection film from being largely scraped. Also, at this time, the third
If the above-mentioned pressure and rotation speed in the polishing step are smaller than those in the first polishing step, it is possible to more reliably prevent the antireflection film surface from being largely scraped.

In the method for forming a wiring structure of the present invention, it is preferable that the polishing agent used in the third polishing step is the same as that used in the second polishing step.

In this way, since the conductive film embedded in the groove is not largely polished in the third polishing step, it is possible to prevent an increase in wiring resistance.

In the wiring structure forming method of the present invention, the third polishing step may include a two-step polishing step under different polishing conditions. In this case, the polishing agent used in one stage of the two-step polishing process is the same as the second polishing process, and the polishing agent used in the other stage of the two-step polishing process is the first polishing process. It is preferable that the polishing step is the same as the polishing step. In this way, the yield in wiring formation can be improved.

In the wiring structure forming method of the present invention, the foreign matter removing step preferably includes a step of cleaning the surface to be polished with an organic acid or an organic alkali.

By doing so, the foreign matter attached to the surface to be polished can be surely removed.

In the method for forming a wiring structure of the present invention, when the distance between the first groove and the second groove is 0.25 μm or less, the above-mentioned effects of the present invention are more remarkable than those of the prior art. can get.

In the method for forming a wiring structure of the present invention, the first groove and the second groove may be arranged in parallel with each other.

In the method of forming the wiring structure of the present invention, the wiring formation in the first groove and the second groove may be performed by using the dual damascene method.

In the wiring structure forming method of the present invention, the antireflection film is preferably made of a silicon-containing material.

By doing so, the pattern forming accuracy in the lithography process for forming the groove is surely improved. For example, when KrF excimer laser light (wavelength 248 nm) is used as a light source in a lithography process, a stacked film of a lower layer 75 nm thick SiON film and an upper layer 8 nm thick SiO ₂ film is used for KrF excimer laser light. Since it has a high absorption efficiency, it exhibits excellent performance as an antireflection film. Further, when a silicon compound is used as the material of the antireflection film, the device for opening the antireflection film can be shared with the device for forming holes in the silicon oxide film, thereby reducing the manufacturing cost of the semiconductor device. You can

In the wiring structure forming method of the present invention, it is preferable that the conductive film is a copper film and the barrier metal film is a tantalum film, a tantalum nitride film, or a laminated film of a tantalum film and a tantalum nitride film.

By doing so, a low resistance wiring can be formed. In this case, the wiring formed in the first groove or the second groove may be electrically connected to the plug formed on the lower side of the wiring.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A method for forming a wiring structure according to a first embodiment of the present invention will be described below with reference to the drawings.

1 (a) to 1 (c), FIG. 2 (a),
FIG. 3B, FIG. 3A, FIG. 3B and FIG. 4 are cross-sectional views showing each step of the method for forming the wiring structure according to the first embodiment.

First, as shown in FIG. 1A, a first silicon oxide film 1 is formed on a substrate 100 made of, for example, silicon.
After forming 01, the lower wiring 102 made of, for example, a tungsten film is formed on the first silicon oxide film 101. After that, a second silicon oxide film 103 is deposited on the first silicon oxide film 101 including the lower wiring 102 by, for example, the CVD method.

Next, as shown in FIG. 1B, a via hole 104 reaching the lower wiring 102 is formed in the second silicon oxide film 103 by using the lithography method and the dry etching method.

Next, as shown in FIG. 1C, for example, P
By using the VD method or the CVD method, the titanium (Ti) film 105 and the titanium nitride (TiN) film 10 are formed on the second silicon oxide film 103 so that the via hole 104 is partially filled.
6 are sequentially deposited. After that, for example, using the CVD method,
Titanium nitride film 1 so that the via hole 104 is completely filled
A tungsten film 107 is formed on 06. here,
The titanium film 105 and the titanium nitride film 106 are barrier metals.

Next, as shown in FIG. 2A, for example, C
Using the MP method, the titanium film 105, the titanium nitride film 106, and the tungsten film 107 deposited in the region outside the via hole 104 are removed. As a result, the plug 108 made of tungsten is formed in the via hole 104 in the second silicon oxide film 103 without fail by being protected by the barrier metal.

Next, as shown in FIG. 2B, for example, C
Using the VD method, on the second silicon oxide film 103,
Fluorine-added silicon oxide film (hereinafter referred to as FSG (Fl
uorine Doped Silicate Glass) film) 109 and ARL film 110 are sequentially deposited. Where ARL film 1
Reference numeral 10 has a two-layer structure of, for example, an upper SiON film and a lower SiO ₂ film, and has a function of improving the resolution at the time of exposure in the subsequent lithography process. After that, a plurality of wiring trenches (trench) 111 are formed in the ARL film 110 and the FSG film 109 (and the surface portion of the second silicon oxide film 103) by using the lithography method and the dry etching method. Here, the plurality of wiring grooves 111 include wiring grooves reaching the plug 108. The wiring grooves 111 are arranged, for example, in parallel with each other, and the distance between the wiring grooves 111 is 0.2.
It is about 5 μm.

Next, as shown in FIG. 3A, for example, P
Using the VD method, the tantalum nitride (TaN) film 1 is formed on the ARL film 110 so that each wiring groove 111 is filled in halfway.
12 and the first copper (Cu) film 113 are sequentially deposited. Here, the first copper film 113 functions as a seed layer in the subsequent plating process. In addition, the tantalum nitride film 112
Acts as a barrier layer. Then, a second copper film 114 is deposited on the first copper film 113 by plating, for example, so that each wiring groove 111 is completely filled.

Next, as shown in FIG. 3B, the first copper film 113 deposited on the region outside each wiring groove 111 by the CMP method using a polishing agent (slurry) for Cu polishing.
Then, the second copper film 114 is removed (first polishing step).
As a result, the tantalum nitride film 112 outside the wiring trenches 111 is exposed. Then, the tantalum nitride film 112 deposited on the region outside each wiring groove 111 is removed by a CMP method using a slurry for polishing a barrier layer (TaN) (second polishing step). As a result, each wiring groove 111
A copper wiring (upper layer wiring) 115 having a barrier layer is formed inside the FSG film 109, and the ARL film 11 is formed.
The surface of 0 is exposed. Here, the copper wiring 115 is electrically connected to the plug 108 formed on the lower side thereof.

Here, the first and second polishing steps will be described in detail. In this embodiment, the first and second polishing steps are performed using the same CMP apparatus.

FIG. 5 is a schematic configuration diagram of a CMP apparatus used in the first and second polishing steps.

As shown in FIG. 5, the substrate to be polished (the substrate 10
The wafer 151 of 0) is held by a holder 152 which is rotatable and vertically movable. Also,
The polishing pad 153 for polishing the surface of the wafer 151 is attached to the surface of the polishing surface plate 154 that makes a rotary motion. The slurry 155 is dropped onto the polishing pad 153 from the slurry supply pipe 156. In this state, when the polishing platen 154 is rotated to rotate the polishing pad 153 and the holder 152 is rotated and lowered, the wafer 151 held by the holder 152 and the polishing pad 153 rub against each other, so that the wafer 151
Surface is polished.

In the present embodiment, the polishing conditions such as the type of slurry are changed when shifting from the first polishing step to the second polishing step. Specifically, the pressure for pressing the wafer 151 against the polishing pad 153 and the rotation speed of the polishing pad 153 in the second polishing step are smaller than those in the first polishing step. However, in the present specification, when the wafer 151 rotates together with the holder 152, the rotation speed of the polishing pad 153 means the relative speed of the polishing pad 153 with respect to the wafer 151.

By the way, at the end of the second polishing step using the CMP method as described above, FIG.
As shown in (b), the ARL film 11 between the copper wirings 115 is formed.
The metal 116 such as copper is embedded in the crack generated on the surface of 0. Where the metal 116 embedded in the crack
However, when a pseudo bridge structure is formed between the copper wirings 115, a short circuit occurs between the copper wirings 115.

Therefore, in the present embodiment, the copper wiring 1
In order to reduce the frequency of occurrence of short circuits between the copper wirings 115 while minimizing the reduction in the thickness of the copper film forming the film 15, the method described below was used to fill in the cracks. The metal 116 is removed.

First, after the completion of the second polishing step, the substrate 10
0 (wafer 151) is taken out from the CMP apparatus and substrate 1
The surface of 00 is washed. As a result, shavings (foreign matter) generated in the first polishing step or the second polishing step are removed from the substrate 1
Can be washed from the surface of 00. For cleaning the substrate 100, for example, an organic acid solution or an organic alkali solution is used. Here, it is important to remove shavings that become foreign matter. That is, when the metal 116 embedded in the crack on the surface of the ARL film 110 is removed while leaving the shavings on the substrate 100, the shavings cause new damage to the ARL film 110 or the copper wiring 115. This is because there is a possibility that Specifically, even if the metal 116 embedded in the original crack can be removed, the copper wiring 115 is damaged (that is, the copper film forming the copper wiring 115 becomes thin) or the ARL film 110. There is a possibility that a new crack will occur in the crack and the metal will be embedded in the crack.

In this embodiment, the substrate 100 described above is used.
Cleaning process (foreign matter removal process) for (wafer 151)
Is performed by moving the substrate 100 from the CMP apparatus to the cleaning apparatus. At this time, it is preferable to separately remove the shavings (foreign matter) attached to the polishing pad 153 while cleaning the substrate 100. The reason is the same as in the case of cleaning the substrate 100 described above. That is, by removing the shavings remaining on the polishing pad 153, when the metal 116 embedded in the crack on the surface of the ARL film 110 on the substrate 100 is removed by using the polishing pad 153 continuously, It is possible to more reliably prevent new damage from occurring on the surface or the like of the ARL film 110. Here, the removal of the shavings remaining on the polishing pad 153 is
For example, in the CMP apparatus, while rotating the polishing pad 153, pure water is supplied instead of the slurry to supply the polishing pad 1
This is done by washing 53. Alternatively, the surface of the polishing pad 153 may be brushed with a grindstone to remove the shavings. By these, the shavings adhering to the surface of the polishing pad 153 can be reliably removed.

Next, after the foreign matter removing step, the ARL film 110 is formed.
The surface of the ARL film 110 is polished by the CMP method in order to remove the metal 116 embedded in the minute cracks on the surface of (3) (third polishing step). As a result, as shown in FIG. 4, the metal 11 in the crack, which causes a short circuit between the wirings, is generated.
6 can be removed with cracks.

In this embodiment, the third polishing step is performed using the same CMP apparatus (see FIG. 5) used in the first and second polishing steps. Further, the polishing conditions of the third polishing step except the polishing time are the second polishing step (that is, the polishing step for the tantalum nitride film 112 (barrier metal film)).
The polishing conditions are the same. Specifically, the substrate 100 (wafer 151) in the third polishing process is polished by the polishing pad 15
The pressure applied to 3 and the rotation speed of the polishing pad 153 are the same as in the second polishing step. That is, the third
The above-mentioned pressure and rotation speed in the polishing step are smaller than those in the first polishing step (the polishing steps for the copper films 113 and 114), respectively. Further, the slurry used in the third polishing step is similar to the second polishing step in that the slurry is a barrier layer (TaN).
It is a polishing slurry. On the other hand, the polishing time of the third polishing step is set to be shorter than the polishing time of the barrier metal film in the second polishing step (for example, about 20 seconds).
The reason is that the fragile ARL film 110 is used in the third polishing process.
The purpose is to remove the unnecessary metal 116 embedded in the cracks of the film. For films other than the ARL film 110, for example, a copper film forming the copper wiring 115, it is desired to minimize the film loss. Because. Further, since the polishing conditions of the third polishing step except the polishing time are the same as those of the second polishing step, the ARL film 110 is appropriately polished, and thereby the surface of the ARL film 110 is filled. The removed metal 116 is removed. Further, since the polishing conditions of the third polishing step (pressure for pressing the substrate against the polishing pad, rotation speed of the polishing pad, slurry, polishing time, etc.) are such that copper is hard to be polished, The copper film forming the copper wiring 115 is not greatly polished.

As described above, according to the first embodiment, the FSG film 109 on the substrate 100 and the A on the FSG film 109 are formed.
After the barrier metal film (tantalum nitride film 112) and the conductive film for wiring (copper films 113 and 114) are sequentially embedded in the wiring groove 111 provided in the RL film 110, the wiring groove 1 is formed.
The wiring conductive film and the barrier metal film outside 11 are removed by polishing. Then, after removing foreign matters (shavings) attached to the substrate 100 during polishing, the surface of the ARL film 110 is polished. Therefore, when the barrier metal film is polished, A existing between the wiring trenches 111 (that is, between the copper wirings 115).
When a minute crack is generated on the surface of the RL film 110 and the metal 116 is embedded in the crack, the following effects are obtained. That is, when polishing the barrier metal film, etc., the substrate 1
After the foreign matter adhering to 00 is removed, the surface of the ARL film 110 is subjected to final polishing.
The metal 116 embedded in the crack can be removed while preventing the surface of the L film 110 from being newly damaged. Therefore, it is possible to avoid a situation in which the copper wirings 115 are bridged by the metal 116 embedded in the cracks, so that it is possible to form a wiring structure in which the occurrence of shorts between the wirings is suppressed, that is, a high-performance wiring.

FIG. 6A shows the result of comparing the frequency of occurrence of a short circuit between copper wirings formed by the wiring structure forming method of the present embodiment with that of the prior art. Also, FIG. 6B schematically shows the inter-wiring distance and the wiring width in the wiring structure formed by the wiring structure forming method of the present embodiment. The vertical axis of FIG. 6 (a) represents the number of defects per unit area (1 cm ² ) (the number of scratches (cracks) on the surface of the ARL film, which causes a short circuit).
Is. Further, as shown in FIG. 6B, the FSG film 109 and the ARL are formed by the method of forming the wiring structure of the present embodiment.
The distance between the copper wirings 115 formed on the film 110 is 0.25 μm, and the width of the copper wirings 115 is 0.25 μm.
Is. As shown in FIG. 6A, in this embodiment, after the barrier metal film (tantalum nitride film 112) is polished, the surface of the substrate 100 is cleaned (removal of shavings) and the surface of the ARL film 110 is sequentially polished. By doing so, the number of defects that cause a short circuit can be reduced to about 0.2, which is about 1/50 of that in the conventional technique. That is, the number of defects according to the present embodiment is much lower than 0.5, which is the number of defects that achieves a practically sufficient yield.

In the prior art, as the distance between the wirings adjacent to each other becomes smaller, especially when the distance between the wirings becomes 0.25 μm or less, the short circuit between the wirings becomes remarkable. On the other hand, according to the present embodiment, when the distance between the wirings is 0.25 μm or less, the effect of preventing the short circuit between the wirings can be more significantly obtained.

Further, according to the first embodiment, the substrate 10 in the third polishing step (polishing step of the ARL film 110) is performed.
The pressure for pressing 0 to the polishing pad 153 and the rotation speed of the polishing pad 153 are the same as those in the second polishing step (polishing step of the tantalum nitride film 112). In other words, the polishing conditions for the third polishing step except the polishing time are the second
It is the same as the polishing process of. For this reason, it is not necessary to make a complicated change in the polishing conditions when the second polishing process shifts to the third polishing process, so that the workability in wiring formation can be improved, thereby increasing the process throughput. It can prevent the deterioration. Further, since the polishing time of the third polishing step is shorter than that of the second polishing step, it is possible to prevent the surface of the ARL film 110 from being largely scraped. At this time, the above-mentioned pressure and rotation speed in the third polishing step are respectively the first polishing step (polishing step of the copper films 113 and 114).
When it is smaller than that, it is possible to more reliably prevent the surface of the ARL film 110 from being greatly scraped.

(Second Embodiment) A method of forming a wiring structure according to a second embodiment of the present invention will be described below with reference to the drawings. The second embodiment differs from the first embodiment in that the dual damascene method is used for forming the copper wiring.

FIGS. 7A to 7C and FIG. 8A,
(B) is sectional drawing which shows each process of the formation method of the wiring structure which concerns on 2nd Embodiment.

First, as shown in FIG. 7A, the first silicon oxide film 2 on the substrate 200 made of, for example, silicon.
After forming 01, the lower wiring 202 made of, for example, a tungsten film is formed on the first silicon oxide film 201. After that, the second silicon oxide film 203 and the ARL film 204 are sequentially deposited on the first silicon oxide film 201 including the lower wiring 202 by, for example, the CVD method. Here, the ARL film 204 is, for example, an upper layer of SiON.
It has a two-layer structure of a film and a lower SiO ₂ film, and also has a function of improving the resolution at the time of exposure in the subsequent lithography process. After that, a via hole 205 reaching the lower layer wiring 202 is formed in the ARL film 204 and the second silicon oxide film 203 by using the lithography method and the dry etching method.

Next, as shown in FIG. 7B, the substrate 20
After a resist is applied over the entire surface of 0, a resist pattern 206 having an opening in a wiring groove forming region is formed by using a lithography method.

Next, as shown in FIG. 7C, the ARL film 204 and the second silicon oxide film 203 are dry-etched using the resist pattern 206 as a mask to form a plurality of wiring trenches 207. After that, the resist pattern 206 is removed by ashing. here,
The plurality of wiring grooves 207 include wiring grooves reaching the via holes 205 (formed in a region including the upper portion of the original via holes 205). The wiring grooves 207 are arranged, for example, in parallel with each other, and the distance between the wiring grooves 207 is about 0.25 μm.

Next, as shown in FIG. 8A, a tantalum nitride (TaN) film 208 is formed on the ARL film 204 so that the wiring trenches 207 and the via holes 205 are partially filled.
Deposit. Here, the tantalum nitride film 208 functions as a barrier layer. Then, the tantalum nitride film 208 is formed so that the wiring trenches 207 and the via holes 205 are completely filled.
A copper film 209 is deposited on top.

Next, as shown in FIG. 8B, each wiring groove 207 is formed by a CMP method using a Cu polishing slurry.
And the copper film 2 deposited on the region outside the via hole 205
09 is removed (first polishing step). As a result, the tantalum nitride film 208 outside the wiring grooves 207 and the via holes 205 is exposed. Then, each wiring groove 20 is formed by a CMP method using a slurry for polishing a barrier layer (TaN).
7 and the tantalum nitride film 208 deposited on the region outside the via hole 205 is removed (second polishing step). As a result, a copper wiring (upper layer wiring) 210 having a barrier layer between the wiring groove 207 and the via hole 205 and an insulating film such as the second silicon oxide film 203 is formed.
The surface of the ARL film 204 is exposed. Here, the copper wiring 21
0 is formed in the via hole 205 and the lower layer wiring 20
2 has a plug portion electrically connected to the terminal 2.

Also in this embodiment, as in the first embodiment, the first and second polishing steps are performed using the same CMP apparatus (see FIG. 5). Further, when shifting from the first polishing step to the second polishing step, polishing conditions such as the type of slurry are changed. Specifically, the pressure for pressing the substrate 200 against the polishing pad and the rotation speed of the polishing pad in the second polishing step are smaller than those in the first polishing step.

By the way, at the end of the second polishing step using the CMP method as described above, the copper wiring 2
A metal (not shown) such as copper is embedded in the cracks generated on the surface of the ARL film 204 between 10. Here, when the metal embedded in the crack forms a pseudo bridge structure between the copper wirings 210, a short circuit occurs between the copper wirings 210.

Therefore, in the present embodiment, the copper wiring 2
In order to reduce the occurrence frequency of short circuits between the copper wirings 210 while minimizing the reduction in the film thickness of the copper film forming 10, the method described below was used to fill in the cracks. Remove metal.

First, after the completion of the second polishing step, the substrate 20
0 is taken out from the CMP apparatus and the surface of the substrate 200 is cleaned. Thereby, the shavings (foreign matter) generated in the first polishing step or the second polishing step can be washed away from the surface of the substrate 200. For cleaning the substrate 200, for example,
An organic acid solution or an organic alkali solution is used. Here, it is important to remove shavings that become foreign matter. That is, while leaving the shavings on the substrate 200, the ARL film 2
This is because if the metal embedded in the crack on the surface of 04 is to be removed, the shavings may cause new damage to the ARL film 204 or the copper wiring 210. Specifically, even if the metal embedded in the original crack can be removed, the copper wiring 210 is damaged (that is, the copper film forming the copper wiring 210 becomes thin), or the ARL film 204 is removed. There is a possibility that a new crack will be generated and the metal will be embedded in the crack.

In the present embodiment, the above-mentioned cleaning process (foreign matter removing process) for the substrate 200 is performed by CM of the substrate 200.
It is performed by moving from the P device to the cleaning device. At this time, it is preferable to remove the shavings (foreign matter) attached to the polishing pad while cleaning the substrate 200.
The reason is the same as in the case of cleaning the substrate 200 described above. That is, by removing the shavings remaining on the polishing pad, the ARL film 204 on the substrate 200 is removed.
It is possible to more reliably prevent new damage from occurring on the surface or the like of the ARL film 204 when the metal embedded in the cracks on the surface of is removed by using the polishing pad continuously. Here, the removal of the shavings remaining on the polishing pad is performed, for example, by rotating the polishing pad in a CMP apparatus and supplying pure water instead of slurry to clean the polishing pad. Alternatively, the shavings may be removed by brushing the surface of the polishing pad with a grindstone. By these, the shavings adhering to the surface of the polishing pad can be reliably removed.

Next, after the foreign matter removing step, the ARL film 204
The surface of the ARL film 204 is polished by the CMP method in order to remove the metal embedded in the minute cracks on the surface of (3) (third polishing step). As a result, the metal in the crack, which causes the short circuit between the wirings, can be removed together with the crack.

In the present embodiment as well, similar to the first embodiment, the third polishing step is performed using the same CMP apparatus (see FIG. 5) used in the first and second polishing steps. The polishing conditions of the third polishing step except the polishing time are the second
The polishing conditions are the same as those in the polishing step (that is, the polishing step for the tantalum nitride film 208 (barrier metal film)). Specifically, the pressure at which the substrate 200 is pressed against the polishing pad and the rotation speed of the polishing pad in the third polishing step are the same as those in the second polishing step. That is, the above-mentioned pressure and rotation speed in the third polishing step are smaller than those in the first polishing step (polishing step of the copper film 209), respectively. The slurry used in the third polishing step is a barrier layer (TaN) polishing slurry, as in the second polishing step. On the other hand, the polishing time of the third polishing step is
It is set to a time shorter than the polishing time of the barrier metal film in the polishing step (for example, about 20 seconds). The reason is that the third polishing step aims at removing unnecessary metal embedded in the cracks of the fragile ARL film 204, and forms a film other than the ARL film 204, for example, the copper wiring 210. This is because the reduction of the thickness of the copper film is desired to be minimized. In addition, since the polishing conditions of the third polishing step except the polishing time are the same as those of the second polishing step, A
The RL film 204 is appropriately polished so that the metal embedded on the surface of the ARL film 204 is removed. Further, since the polishing conditions of the third polishing step (pressure for pressing the substrate against the polishing pad, rotation speed of the polishing pad, slurry, polishing time, etc.) are such that copper is hard to be polished, The copper film forming the copper wiring 210 is not greatly polished.

As described above, according to the second embodiment, the barrier metal film (in the wiring groove 207 and the via hole 205 provided in the ARL film 204 and the second silicon oxide film 203 on the substrate 200) is formed. Tantalum nitride 20
8) and the conductive film for wiring (copper film 209) are sequentially buried, and then the conductive film for wiring and the barrier metal film outside the wiring groove 207 and the via hole 205 are removed by polishing. Then, foreign matter (shavings) attached to the substrate 200 during polishing
Then, the surface of the ARL film 204 is polished. Therefore, when the barrier metal film is polished, a minute crack is generated on the surface of the ARL film 204 existing between the wiring grooves 207 (that is, between the copper wirings 210), and the metal is embedded in the crack, The following effects can be obtained. That is, since the foreign substances adhering to the substrate 200 are removed during polishing of the barrier metal film and the like, the surface of the ARL film 204 is subjected to final polishing, so that the foreign substances are prevented from newly damaging the surface of the ARL film 204. However, the metal embedded in the crack can be removed. Therefore, it is possible to avoid a situation in which the copper wirings 210 are bridged by the metal embedded in the cracks, and thus it is possible to form a wiring structure in which the occurrence of a short circuit between the wirings is suppressed, that is, a high-performance wiring.

Further, in the prior art, as the distance between the wirings adjacent to each other becomes smaller, especially when the distance between the wirings becomes 0.25 μm or less, the short circuit between the wirings remarkably occurs. On the other hand, according to the present embodiment, when the distance between the wirings is 0.25 μm or less, the effect of preventing the short circuit between the wirings can be more significantly obtained.

Further, according to the second embodiment, the substrate 20 in the third polishing step (polishing step of the ARL film 204) is performed.
The pressure at which 0 is pressed against the polishing pad and the rotation speed of the polishing pad are respectively set in the second polishing step (the tantalum nitride film 20).
8 polishing step). In other words, the polishing conditions of the third polishing step except the polishing time are the same as those of the second polishing step. For this reason, it is not necessary to make a complicated change in the polishing conditions when the second polishing process shifts to the third polishing process, so that the workability in wiring formation can be improved, thereby increasing the process throughput. It can prevent the deterioration. Further, since the polishing time of the third polishing step is shorter than that of the second polishing step, it is possible to prevent the surface of the ARL film 204 from being largely scraped. At this time, if the above-mentioned pressure and rotation speed in the third polishing step are smaller than those in the first polishing step (polishing step of the copper film 209), respectively, AR
It is possible to more reliably prevent the surface of the L film 204 from being greatly scraped.

In the first or second embodiment, A
The case where the first layer copper wiring is formed by using the RL film is targeted. However, when the multilayer copper wiring is formed by using the ARL film, the copper wiring of the upper layer of the second layer and thereafter is formed. The method of this embodiment may be applied to the formation. Further, the method of the present embodiment may be applied when a wiring is formed by embedding a conductive film other than copper in the wiring groove.

In the first or second embodiment,
The type of the barrier metal film is not particularly limited, but when a copper film is used as the conductive film for wiring, examples of the barrier metal film include a tantalum film, a tantalum nitride film,
Alternatively, it is preferable to use a laminated film of a tantalum film and a tantalum nitride film. Further, the type of insulating film in which the wiring is embedded and the type of ARL film are not particularly limited.

In the first or second embodiment,
In the foreign matter removing step (substrate cleaning step) performed after the second polishing step (polishing the barrier metal film), it is preferable to perform substrate cleaning using an organic acid solution or an organic alkali solution. In this way, foreign matter (shavings) attached to the substrate surface can be reliably removed. At this time, as the organic alkali, for example, hydroxylamine such as TMAH (tetramethylammonium hydride) may be used. Further, as the organic acid, for example, oxalic acid,
Carboxyl group (-COO such as citric acid or malic acid)
A carboxylic acid having two or more H groups) may be used.

In the first or second embodiment,
The type of Cu polishing slurry and the type of barrier layer (TaN) polishing slurry are not particularly limited. For example, C containing hydrogen peroxide solution as an oxidant is used.
A u polishing slurry and, for example, a TaN polishing slurry containing nitric acid (or a derivative thereof) as an oxidizing agent may be used. Alternatively, Cu polishing slurry and TaN polishing slurry having different particle sizes may be used. The type of slurry used in the third polishing step is not particularly limited, but it is preferable to use the barrier layer polishing slurry as in the second polishing step. By doing so, it is possible to prevent the conductive film for wiring from being greatly polished in the third polishing step, and thus it is possible to prevent an increase in wiring resistance. Also, from the second polishing step to the third
It becomes easier to change the polishing conditions when shifting to the polishing step. Further, the third polishing step is performed in two steps, the first polishing step is performed under the same conditions as the first polishing step, and then the third polishing step is performed. Polishing may be performed in two steps under the same conditions as in the second polishing step. By doing so, the yield in wiring formation can be further improved.

In the first or second embodiment,
Although the first to third polishing steps were performed using the same CMP apparatus, instead of this, all polishing steps were performed by separate CMP apparatuses.
The apparatus may be used, or only one polishing step may be performed using another CMP apparatus.
However, it is preferable that the second polishing step and the third polishing step be performed using the same polishing apparatus and polishing pad.
This makes it possible to operate the polishing apparatus efficiently. The CMP apparatus usable in the first to third polishing steps is not limited to the one having one substrate holder and polishing one substrate in one polishing step. That is, a CMP apparatus having a plurality of substrate holders and polishing a plurality of substrates in one polishing process may be used.

[0082]

According to the present invention, when a barrier metal film and a conductive film for wiring are sequentially buried in a wiring groove formed in an insulating film and an antireflection film on the insulating film, a barrier metal film After removing foreign matter adhering to the substrate during polishing or the like, finish polishing is performed on the surface of the antireflection film. Therefore, it is possible to remove the metal embedded in the crack on the surface of the antireflection film while preventing the foreign matter from newly damaging the surface of the antireflection film, thus avoiding the situation where the wiring bridges the metal. it can. Therefore, the frequency of occurrence of short circuit between the wirings can be reduced, and high-performance wiring can be formed.

[Brief description of drawings]

1A to 1C are cross-sectional views showing respective steps of a method for forming a wiring structure according to a first embodiment of the present invention.

2A and 2B are cross-sectional views showing each step of the method for forming the wiring structure according to the first embodiment of the present invention.

3A and 3B are cross-sectional views showing each step of the method for forming the wiring structure according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step of the method for forming the wiring structure according to the first embodiment of the present invention.

FIG. 5 is a schematic configuration diagram of a CMP apparatus used in the method for forming a wiring structure according to the first or second embodiment of the present invention.

FIG. 6A is a diagram showing a result of comparing a short circuit occurrence frequency between copper wirings formed by the method for forming a wiring structure according to the first embodiment of the present invention with that of a conventional technique. FIG. 3B is a diagram schematically showing the inter-wiring distance and the wiring width in the wiring structure formed by the wiring structure forming method according to the first embodiment of the present invention.

7A to 7C are cross-sectional views showing respective steps of a method for forming a wiring structure according to a second embodiment of the present invention.

8A and 8B are cross-sectional views showing each step of the method for forming a wiring structure according to the second embodiment of the present invention.

9A to 9C are cross-sectional views showing respective steps of a conventional method for forming a wiring structure.

FIG. 10 is a diagram for explaining a problem in a conventional method of forming a wiring structure.

[Explanation of symbols]

100 substrates 101 first silicon oxide film 102 Lower layer wiring 103 Second silicon oxide film 104 beer hall 105 titanium film 106 titanium nitride film 107 Tungsten film 108 plug 109 FSG film 110 ARL membrane 111 Wiring groove 112 tantalum nitride film 113 First copper film 114 second copper film 115 Copper wiring (upper layer wiring) 116 Metals embedded in cracks 151 wafers 152 holder 153 polishing pad 154 Polishing surface plate 155 slurry 156 Slurry supply pipe 200 substrates 201 First silicon oxide film 202 Lower layer wiring 203 second silicon oxide film 204 ARL membrane 205 beer hall 206 resist pattern 207 Wiring groove 208 tantalum nitride film 209 copper film 210 Copper wiring (upper layer wiring)

Continued front page    (72) Inventor Masashi Hamanaka             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Takeshi Harada             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F term (reference) 5F033 HH11 HH21 HH32 JJ01 JJ11                       JJ18 JJ19 JJ21 JJ32 JJ33                       KK19 MM01 MM02 MM12 MM13                       NN06 NN07 PP06 PP14 PP26                       QQ04 QQ11 QQ37 QQ48 QQ50                       RR04 RR08 RR11 SS11 TT02                       WW01 XX31

Claims (18)

[Claims] 1. After forming an antireflection film on the insulating film,
A groove forming step of forming a first groove and a second groove adjacent to the first groove in the antireflection film and the insulating film; and so that the first groove and the second groove are filled. A film deposition step of depositing a barrier metal film and a conductive film on the antireflection film, and a first polishing for removing the conductive film outside the first groove and outside the second groove by polishing. And a second polishing step of removing the barrier metal film outside the first groove and outside the second groove by polishing after the first polishing step, After the step, a foreign matter removing step of removing foreign matter adhering to the surface to be polished and a third polishing step of polishing the surface of the antireflection film after the foreign matter removing step are provided. And a method for forming a wiring structure. 2. A step of removing foreign matter adhering to the polishing pad used in the second polishing step is provided between the second polishing step and the third polishing step. The method for forming a wiring structure according to claim 1. 3. The method of forming a wiring structure according to claim 2, wherein the step of removing foreign matter attached to the polishing pad includes a step of cleaning the polishing pad. 4. The method of forming a wiring structure according to claim 2, wherein the step of removing foreign matter attached to the polishing pad includes a step of brushing the surface of the polishing pad with a grindstone. 5. The method of forming a wiring structure according to claim 1, wherein the second polishing step and the third polishing step are performed using the same polishing apparatus and polishing pad. 6. The pressure for pressing the surface to be polished against a polishing pad and the rotation speed of the polishing pad in the third polishing step are the same as those in the second polishing step. A method for forming the described wiring structure. 7. The method for forming a wiring structure according to claim 6, wherein the polishing time of the third polishing step is shorter than that of the second polishing step. 8. The method of forming a wiring structure according to claim 6, wherein the pressure and the rotation speed in the third polishing step are smaller than those in the first polishing step. 9. The method for forming a wiring structure according to claim 1, wherein the polishing agent used in the third polishing step is the same as that used in the second polishing step. 10. The third polishing process includes a two-step polishing process under different polishing conditions.
A method for forming a wiring structure as described in 1. 11. The polishing agent used in one stage of the two-stage polishing process is the same as that used in the second polishing process, and is used in the other stages of the two-stage polishing process. The method for forming a wiring structure according to claim 10, wherein the polishing agent is the same as that used in the first polishing step. 12. The method of forming a wiring structure according to claim 1, wherein the foreign matter removing step includes a step of cleaning the surface to be polished with an organic acid or an organic alkali. 13. The method for forming a wiring structure according to claim 1, wherein the distance between the first groove and the second groove is 0.25 μm or less. 14. The method for forming a wiring structure according to claim 1, wherein the first groove and the second groove are arranged in parallel with each other. 15. The method of forming a wiring structure according to claim 1, wherein the wiring is formed in the first groove and the second groove by using a dual damascene method. 16. The method for forming a wiring structure according to claim 1, wherein the antireflection film is made of a silicon-containing material. 17. The conductive film is a copper film, and the barrier metal film is a tantalum film, a tantalum nitride film, or a laminated film of a tantalum film and a tantalum nitride film. Method of forming wiring structure. 18. The wiring according to claim 17, wherein the wiring formed in the first groove or the second groove is electrically connected to a plug formed under the wiring. A method for forming the described wiring structure.