JP2003243356A5 - - Google Patents

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Publication number
JP2003243356A5
JP2003243356A5 JP2002264135A JP2002264135A JP2003243356A5 JP 2003243356 A5 JP2003243356 A5 JP 2003243356A5 JP 2002264135 A JP2002264135 A JP 2002264135A JP 2002264135 A JP2002264135 A JP 2002264135A JP 2003243356 A5 JP2003243356 A5 JP 2003243356A5
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Japan
Prior art keywords
etching
semiconductor substrate
manufacturing
semiconductor
semiconductor device
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Application number
JP2002264135A
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Japanese (ja)
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JP2003243356A (en
JP3620528B2 (en
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Priority to JP2002264135A priority Critical patent/JP3620528B2/en
Priority claimed from JP2002264135A external-priority patent/JP3620528B2/en
Priority to DE10256985A priority patent/DE10256985B4/en
Priority to US10/310,021 priority patent/US7148125B2/en
Priority to CNB021557314A priority patent/CN1267970C/en
Publication of JP2003243356A publication Critical patent/JP2003243356A/en
Application granted granted Critical
Publication of JP3620528B2 publication Critical patent/JP3620528B2/en
Publication of JP2003243356A5 publication Critical patent/JP2003243356A5/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【0011】
【課題を解決するための手段】
請求項1に記載の半導体装置の製造方法は、半導体基板の一方の表面に半導体素子が形成された半導体装置の製造方法において、半導体基板における半導体素子が形成された面とは反対側の面から研削加工して、半導体基板を所定の厚さにする研削加工工程と、この研削加工工程を実行した後に、半導体基板の反対側の面に対し半導体基板の外周部を残して所定深さまでエッチングして薄くするエッチング工程と、このエッチング工程を実行した後に、半導体基板の反対側の面に電極を形成する電極形成工程とを備えたことを特徴としている
[0011]
[Means for Solving the Problems]
The method of manufacturing a semiconductor device according to claim 1 is a method of manufacturing a semiconductor device in which a semiconductor element is formed on one surface of a semiconductor substrate, from the side of the semiconductor substrate opposite to the side on which the semiconductor element is formed. After the grinding process for grinding the semiconductor substrate to a predetermined thickness and the grinding process, etching is performed to a predetermined depth leaving the outer peripheral portion of the semiconductor substrate on the opposite surface of the semiconductor substrate. And an electrode forming step of forming an electrode on the opposite surface of the semiconductor substrate after the etching step is performed .

【0014】
特に、請求項1に記載の発明では、エッチングによって半導体基板の内部を薄く形成しているので、研磨によって薄肉化した場合のようなダメージ層が発生することが防止できる。従って、請求項1に記載するように、エッチング工程後に、半導体基板のエッチング面に電極を形成する場合、基板と電極との接触抵抗を低減することができる。
[0014]
In particular, according to the first aspect of the invention, since the inside of the semiconductor substrate is formed thin by etching, it is possible to prevent the occurrence of a damaged layer as in the case of thinning by polishing. Therefore, as described in claim 1 , when an electrode is formed on the etching surface of the semiconductor substrate after the etching step, the contact resistance between the substrate and the electrode can be reduced.

Claims (8)

半導体基板の一方の表面に半導体素子が形成された半導体装置の製造方法において、前記半導体基板の一方の面とは反対側の面から研削加工して、前記半導体基板を所定の厚さにする研削加工工程と、前記研削加工工程を実行した後に、前記反対側の面に対し前記半導体基板の外周部を残して所定深さまでエッチングして薄くするエッチング工程と、前記エッチング工程を実行した後に、前記半導体基板の反対側の面に電極を形成する電極形成工程とを備えたことを特徴とする半導体装置の製造方法。In a method of manufacturing a semiconductor device in which a semiconductor element is formed on one surface of a semiconductor substrate, grinding is performed from the surface opposite to the one surface of the semiconductor substrate to a predetermined thickness by grinding the semiconductor substrate. A processing step, an etching step of etching and thinning to a predetermined depth leaving the outer peripheral portion of the semiconductor substrate on the opposite surface after the grinding step is performed, and the etching step; And D. an electrode forming step of forming an electrode on the opposite surface of the semiconductor substrate . 低濃度の半導体基板の一方の表面に半導体素子が形成された半導体装置の製造方法において、前記半導体基板の一方の面とは反対側の面から研削加工して、前記半導体基板を所定の厚さにする研削加工工程と、前記研削加工工程を実行した後に、前記反対側の面に対し前記半導体基板の外周部を残して所定深さまでエッチングして薄くするエッチング工程と、前記エッチング工程を実行した後に、前記エッチングが施された前記低濃度の半導体基板の反対側の面に高濃度層を形成する高濃度層形成工程とを備えたことを特徴とする半導体装置の製造方法。In a method of manufacturing a semiconductor device in which a semiconductor element is formed on one surface of a low concentration semiconductor substrate, the semiconductor substrate is ground from a surface opposite to the one surface of the semiconductor substrate to have a predetermined thickness. A grinding process, an etching process for etching and thinning to a predetermined depth leaving the outer peripheral portion of the semiconductor substrate on the opposite surface after the grinding process, and the etching process And a high concentration layer forming step of forming a high concentration layer on the opposite surface of the low concentration semiconductor substrate which has been subjected to the etching later. 前記エッチング工程では、前記半導体基板の外周部に加えて、その外周部によって囲まれる内部領域の一部も、厚さが厚いまま残すようにエッチングを施すことを特徴とする請求項1または請求項2に記載の半導体装置の製造方法。In the etching step, in addition to the outer peripheral portion of the semiconductor substrate, etching is performed so that a part of the inner region surrounded by the outer peripheral portion is left thick. 2. The method of manufacturing a semiconductor device according to 2. 前記エッチング工程では、そのエッチング加工に用いるエッチング液組成によって、エッチング面の表面粗さを制御することを特徴とする請求項1乃至3のいずれかに記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the surface roughness of the etching surface is controlled by the etching solution composition used for the etching process in the etching step. 請求項2に記載の高濃度層形成工程を実行した後に、前記半導体基板の反対側の面に電極を形成する電極形成工程を付加したことを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device, comprising the step of forming an electrode on the surface opposite to the semiconductor substrate after the high concentration layer forming step according to claim 2 is performed. 前記半導体基板における前記半導体素子が形成された素子形成面に保護部材を設けた状態で前記エッチング工程を実行したことを特徴とする請求項1乃至5の何れか1つに記載の半導体装置の製造方法。The said etching process was performed in the state which provided the protection member in the element formation surface in which the said semiconductor element in the said semiconductor substrate was formed, The manufacturing of the semiconductor device as described in any one of the Claims 1 thru | or 5 characterized by the above-mentioned. Method. 前記エッチング工程は、前記半導体基板におけるエッチングにより薄くなった領域の厚さを測定し所望の厚さとなったときにエッチングを終了させるようにしたことを特徴とする請求項1乃至6の何れか1つに記載の半導体装置の製造方法。7. The etching process according to any one of claims 1 to 6, characterized in that the thickness of a region thinned by etching in the semiconductor substrate is measured, and the etching is terminated when the thickness becomes a desired thickness. Method of manufacturing a semiconductor device according to claim 1. 前記半導体基板におけるエッチングにより薄くなった領域の厚さを200μm未満としたことを特徴とする請求項1乃至7の何れか1つに記載の半導体装置の製造方法。The method of manufacturing a semiconductor device according to any one of claims 1 to 7, wherein a thickness of a region thinned by etching in the semiconductor substrate is less than 200 μm.
JP2002264135A 2001-12-12 2002-09-10 Manufacturing method of semiconductor device Expired - Fee Related JP3620528B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2002264135A JP3620528B2 (en) 2001-12-12 2002-09-10 Manufacturing method of semiconductor device
DE10256985A DE10256985B4 (en) 2001-12-12 2002-12-05 Method for producing a power semiconductor component
US10/310,021 US7148125B2 (en) 2001-12-12 2002-12-05 Method for manufacturing semiconductor power device
CNB021557314A CN1267970C (en) 2001-12-12 2002-12-09 Method for producing semiconductor power device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001378725 2001-12-12
JP2001-378725 2001-12-12
JP2002264135A JP3620528B2 (en) 2001-12-12 2002-09-10 Manufacturing method of semiconductor device

Publications (3)

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JP2003243356A JP2003243356A (en) 2003-08-29
JP3620528B2 JP3620528B2 (en) 2005-02-16
JP2003243356A5 true JP2003243356A5 (en) 2005-03-17

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Publication number Priority date Publication date Assignee Title
WO2006023753A2 (en) * 2004-08-20 2006-03-02 Semitool, Inc. System for thinning a semiconductor workpiece
SG126885A1 (en) * 2005-04-27 2006-11-29 Disco Corp Semiconductor wafer and processing method for same
JP5390740B2 (en) * 2005-04-27 2014-01-15 株式会社ディスコ Wafer processing method
JP5011740B2 (en) * 2006-02-02 2012-08-29 富士電機株式会社 Manufacturing method of semiconductor device
JP4667263B2 (en) * 2006-02-02 2011-04-06 シャープ株式会社 Silicon wafer manufacturing method
JP2007243080A (en) * 2006-03-13 2007-09-20 Fuji Electric Holdings Co Ltd Semiconductor device and its manufacturing method
JP5168920B2 (en) * 2007-01-31 2013-03-27 富士電機株式会社 Semiconductor device manufacturing method and marking device
JP2009096698A (en) * 2007-10-19 2009-05-07 Toshiba Corp Wafer and its manufacturing method
JP5428216B2 (en) * 2008-06-20 2014-02-26 富士電機株式会社 Silicon wafer, semiconductor device, method for manufacturing silicon wafer, and method for manufacturing semiconductor device
JP5668270B2 (en) 2008-12-11 2015-02-12 富士電機株式会社 Manufacturing method of semiconductor device
JP2010205761A (en) * 2009-02-27 2010-09-16 Sanyo Electric Co Ltd Semiconductor device and method for manufacturing the same
JP5431777B2 (en) 2009-04-20 2014-03-05 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP5556431B2 (en) 2010-06-24 2014-07-23 富士電機株式会社 Manufacturing method of semiconductor device
JP2015060852A (en) * 2013-09-17 2015-03-30 株式会社東芝 Method and apparatus for manufacturing semiconductor device
US11342189B2 (en) 2015-09-17 2022-05-24 Semiconductor Components Industries, Llc Semiconductor packages with die including cavities and related methods
US9893058B2 (en) 2015-09-17 2018-02-13 Semiconductor Components Industries, Llc Method of manufacturing a semiconductor device having reduced on-state resistance and structure

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