JP2003242098A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having serial I/O, enhancing the degree of freedom for generating serial transmission data, and improving the memory using efficiency. <P>SOLUTION: This semiconductor integrated circuit has a DMA controller 2 for controlling DMA of a plurality of channels, and serially transmitting transmission data by successively transferring the transmission data to the serial I/O 4 from a memory 3 by the plurality of channels of the DMA according to the setting of a transmission data setting register in order according to designation of an order designating register 9 by using a plurality of DMA channel setting registers for setting transfer information transferred to the serial I/O 4 from the memory 3 in response to the respective channels and the order designating register 9 for setting transfer order of the plurality of these DMA channel setting registers. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a serial I / O.
The present invention relates to a semiconductor integrated circuit having a section.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit, when a plurality of bytes of data are serially transmitted, the following method is used. The software sends the next 1-byte transmission data each time 1-byte transmission is completed, or D
MA (Direct Memory Access) is used to transmit data continuously arranged in the memory.

[0003]

The software transmission has a problem that the processing load of the software is large because the software processing is performed every 1 byte transmission. Further, the method using the DMA has a problem that the degree of freedom in creating transmission data is small. The reason why the degree of freedom in creating transmission data when using DMA is reduced will be described below. The DMA basically operates with three parameters of a source address (transfer source address), a destination address (transfer destination address), and the number of transfer bytes. When this is used for serial transmission, the transmission data is continuously arranged for the number of transmission bytes starting from the source address. Usually, the content of the transmission data is variable, so the transmission data is arranged in the RAM area. If the serial transmission data is divided into a header part and a data part, and the header part is fixed data and the data part is variable data, the fixed data should be arranged in the ROM area and the variable data should be arranged in the RAM area. If so, the memory area of the RAM area can be saved. However, as described above, when attempting to serially transmit the DMA, only one source address can be set. Therefore, when the transmission data is divided into the fixed data portion and the variable data portion, the DMA is activated multiple times. There was a problem of need.

The present invention has been made to solve the above-mentioned problems, and an object thereof is to obtain a semiconductor integrated circuit in which the degree of freedom in creating serial transmission data is increased and the memory use efficiency is improved. To do.

[0005]

In a semiconductor integrated circuit according to the present invention, a memory in which transmission data is stored, a serial I / O unit for serially transmitting the transmission data stored in this memory, and a memory are stored in the memory. DM that controls the DMA that transfers the sent transmission data to the serial I / O unit
A DMA controller having a plurality of channels, each of which transfers transmission data.
A plurality of first registers in which transfer information is set respectively corresponding to a plurality of channels of this DMA, and a second register in which a transfer order of each channel of the DMA to be transferred using this first register is set. In addition to having a register, the DMA is controlled to sequentially execute the transfer by each channel of the DMA according to the transfer order of the second register.

Further, a memory in which transmission data is stored,
The serial I / O unit includes a serial I / O unit configured to transfer the transmission data from the memory and perform serial transmission. The serial I / O unit transfers the transmission data from the memory and performs serial transmission, and a serial access unit for transmitting the transmission data. The memory access control unit has a plurality of first registers in which transfer information used for transfer is respectively set, and a second register in which an order of transfer by the plurality of first registers is set. According to the transfer order set in the second register, the transfer by the plurality of first registers is sequentially executed. Further, the memory and the serial I / O unit are connected by a dedicated bus.

Further, a memory in which transmission data is stored and a serial I / O which is connected to this memory by a dedicated bus and serially transmits the transmission data stored in the memory
And a controller connected to the dedicated bus and configured to transfer the transmission data stored in the memory to the serial I / O unit, and the controller includes a plurality of first registers each having transfer information set therein. A second register in which the order of transfer by the plurality of first registers is set, and a memory access control unit that sequentially executes transfer by the plurality of first registers according to the transfer order set in the second register And have. In addition, serial I /
A plurality of O parts are provided. The source address and the number of transfer bytes of the transmission data to be transferred are set in the first register.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. 1 is a block diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 is a CPU that controls the operation of the semiconductor integrated circuit, and 2 is a DMAC (DMA controller) that has a DMA function of performing data transfer through a bus without going through the CPU 1. A memory 3 stores programs or data, and is composed of a ROM and a RAM. 4 is a serial I / O (serial I / O unit) that performs serial data transmission / reception, and 5 is a C
A timer used for activating the processing of PU1 periodically, 6 is an internal bus to which these 1 to 5 are connected,
1 to 6 are formed on the semiconductor integrated circuit.

FIG. 2 is a diagram showing DMAC data transfer of the semiconductor integrated circuit according to the first embodiment of the present invention.
In FIG. 2, 2 to 4 and 6 are the same as those in FIG. FIG. 3 is a diagram showing the structure of the DMAC of the semiconductor integrated circuit according to the first embodiment of the present invention. In FIG. 3, 7 is a DMA channel 1 setting register (first register) for setting data transfer by the DMA channel 1, and 8 is a DMA channel 2 setting register (first register) for setting data transfer by the DMA channel 2. ), 9 is an order designation register (second register) for designating the execution order of each channel of the DMA of a plurality of channels, 10 is the order set in the order designation register 9, and successively executes each channel of the DMA. It is a DMAC control unit having a function. FIG. 4 is a diagram showing the operation of the DMAC of the semiconductor integrated circuit according to the first embodiment of the present invention. 4, 3, 7 to 9 are the same as those in FIG. Reference numeral 11 is a serial output.

Next, the operation will be described. DMAC2
Performs DMA control, which is a function of performing data transfer from memory to memory or from memory to I / O or the like through the bus without passing through the CPU 1. FIG. 2 shows how data is transferred from the memory 3 to the serial I / O 4. The DMAC 2 is configured as shown in FIG. The DMAC control unit 10 is provided with a function of having the order designation register 9 designated by 1 and capable of continuously executing each channel of the DMA in accordance with the order set in the order designation register 9. This DMAC
The operation will be described with reference to FIG. The source address of the setting register 7 of the DMA channel 1 is 0x8000, the number of transfer bytes is 5, the source address of the setting register 8 of the DMA channel 2 is 0x9000, the number of transfer bytes is 2 (the transfer destination is serial I / O 4 ), D in the order designation register 9
When 1 and 2 for designating the MA channel 1 and the DMA channel 2 are set and the DMAC 2 is activated, the DMAC 2 is DMed.
A channel 1 and DMA channel 2 are executed in this order, and as a result,
A serial signal as indicated by 11 in the figure is output.

According to the first embodiment, since serial transmission data can be divided and arranged on the memory 3 and transmitted, the degree of freedom in data creation is increased and the memory usage efficiency is improved. it can. In addition, once the value is set in the DMA channel setting register of each channel, the channel No. It is possible to change or replace the transmission data by simply changing.

Embodiment 2. FIG. 5 is a diagram showing a structure of a serial I / O of a semiconductor integrated circuit according to a second embodiment of the present invention. In FIG. 5, 4 and 6 are the same as those in FIG. 13 is a transmission data setting register 1 (first register) capable of setting the source address and the number of transfer bytes, and 14 is a transmission data setting register 2 (first register) capable of setting the source address and the number of transfer bytes
A plurality of transmission data setting registers are provided. 1
5 indicates the execution order of the transmission data setting registers 1 and 2 as register No. It is an order designation register (second register) designated by. Reference numeral 16 denotes a memory access control unit capable of acquiring data on the memory via the internal bus 6 and serially transmitting the data. Reference numeral 17 denotes data to be serially transmitted by the memory access control unit 16 and serializing the written data. This is a serial transmission register for transmission. 13 to 17 are provided in the serial I / O 4.
FIG. 6 is a diagram showing an operation of serial I / O of the semiconductor integrated circuit according to the second embodiment of the present invention. In FIG. 6, 13 to 15 are the same as those in FIG.

Next, the operation will be described. FIG. 5 shows an embodiment of the present idea. For example, as shown in FIG. 6, the source address of the transmission data setting register 1 is 0 × 80.
00, the number of transfer bytes is 5, the source address of the transmission data setting register 2 is 0 × 9000, the number of transfer bytes is 2, the order specification register 15 is set to 1 and 2, and the memory access control unit 16 is activated. The access control unit 16 accesses the memory via the internal bus 6, acquires data according to the order set in the order designation register 15, and sequentially performs serial transmission. As a result, the same serial output result as in FIG. 4 is obtained.

According to the second embodiment, the serial transmission data can be divided and arranged in the memory and transmitted without using the DMAC. Therefore, the DMAC can be used for other purposes during the serial transmission. Can be used.
Further, the degree of freedom in creating serial transmission data is increased, and the memory usage efficiency can be improved. Further, once the value is set in each transmission data setting register, the transmission data can be changed or exchanged only by changing the register No. set in the order designation register.

Third Embodiment FIG. 7 shows a memory serial I / O of a semiconductor integrated circuit according to a third embodiment of the present invention.
It is a figure which shows the data transfer between. In FIG. 7, 3,
Reference numerals 4 and 6 are the same as those in FIG. A dedicated bus 18 connects the memory 3 and the serial I / O 4. FIG. 8 is a diagram showing a structure of a serial I / O of a semiconductor integrated circuit according to a third embodiment of the present invention. In FIG. 8, 4, 13 to 17 are the same as those in FIG.
Are the same as those in FIG. 7, respectively.

Next, the operation will be described. In the third embodiment, as shown in FIG. 7, the memory 3 and the serial I / O 4 are connected.
The private buses 18 connect the spaces. Memory access control unit 1
6 acquires the data on the memory 3 via the dedicated bus 18 and serially transmits it. The third embodiment is the second embodiment.
In the same manner as above, if the setting as shown in FIG. 6 is performed, the same serial output result as in FIG. 4 can be obtained.

According to the third embodiment, serial transmission data can be divided and arranged in the memory and transmitted without occupying the internal bus. Further, the degree of freedom in creating serial transmission data is increased, and the memory usage efficiency can be improved. In addition, once a value is set in each transmission data setting register, the channel number set in the order designation register is set. It is possible to change or replace the transmission data by simply changing.

Embodiment 4. FIG. 9 is a diagram showing data transfer of the controller of the semiconductor integrated circuit according to the fourth embodiment of the present invention. 9, 3, 4, 6 and 18 are the same as those in FIG. In FIG. 9, the serial I / O 4 (serial I / O unit) has a plurality of channels and operates independently. 19 is a private bus 1
8 is a controller for controlling 8. FIG. 10 is a diagram showing a structure of a controller of a semiconductor integrated circuit according to a fourth embodiment of the present invention. In FIG. 10, 3, 4, 18,
19 is the same as that in FIG. 13a is a transmission data setting register 1 (first register) for the serial I / O channel 1, 14a is a transmission data setting register 2 (first register) for the serial I / O channel 1, and 15a is a serial I / O. It is an order setting register (second register) for channel 1. 13b is a transmission data setting register 1 (first register) for serial I / O channel 2, 14b is a transmission data setting register 2 (first register) for serial I / O channel 2, 15b
Is a sequence setting register (second register) for the serial I / O channel 2. That is, a plurality of transmission data setting registers and sequence setting registers similar to those in FIG. 8 are provided for each serial I / O channel. Reference numeral 20 is a memory access control unit provided in the controller 19.

Next, the operation will be described. As shown in FIG. 9, a dedicated bus 18 is provided between the memory 3 and the serial I / O 4.
Controller 1 for controlling the dedicated bus 18 by connecting with
Place 9 As shown in FIG. 10, the controller 19 has a memory access control unit 20 that can acquire the data in the memory 3 via the dedicated bus 18 and send it to the serial I / O 4, and also has a source address and the number of transfer bytes. , The transmission data setting register that can set a plurality of sets for each serial I / O channel and the execution order of the transmission data setting register for each serial I / O channel.
It has an order designation register designated by.

According to the fourth embodiment, it is possible to divide serial transmission data in a memory and transmit the divided serial transmission data for a plurality of channels of serial I / O. Also,
The degree of freedom in creating serial transmission data is increased, and the memory usage efficiency can be improved. In addition, once a value is set in each transmission data setting register, the register number. It is possible to change or replace the transmission data by simply changing.

[0021]

Since the present invention is constructed as described above, it has the following effects. A memory that stores transmission data, a serial I / O unit that serially transmits the transmission data stored in the memory, and a DMA controller that controls a DMA that transfers the transmission data stored in the memory to the serial I / O unit Equipped with DMA
The controller has a DMA having a plurality of channels for transferring transmission data, a plurality of first registers in which transfer information is set corresponding to a plurality of channels of the DMA, and a transfer using the first register. DM
And a second register in which the transfer order of each channel of A is set, and according to the transfer order of the second register,
DM to sequentially execute the transfer by each channel of DMA
Since A is controlled, the transmission data can be divided and arranged in the memory, which can be sequentially transferred and transmitted by the DMA controller, and the transmission data can be changed according to the setting of the second register. it can.

Further, a memory in which transmission data is stored,
The serial I / O unit includes a serial I / O unit configured to transfer the transmission data from the memory and perform serial transmission. The serial I / O unit transfers the transmission data from the memory and performs serial transmission, and a serial access unit for transmitting the transmission data. The memory access control unit has a plurality of first registers in which transfer information used for transfer is respectively set, and a second register in which an order of transfer by the plurality of first registers is set. Since the transfer by the plurality of first registers is sequentially executed according to the transfer order set in the second register, the transmission data divided and arranged in the memory is sequentially transferred without using the DMA controller. The data can be transmitted, and the transmission data can be changed according to the setting of the second register. Further, since the memory and the serial I / O unit are connected by a dedicated bus, they can be transferred without using the internal bus.

Further, a memory storing transmission data and a serial I / O which is connected to the memory by a dedicated bus and serially transmits the transmission data stored in the memory.
And a controller connected to the dedicated bus and configured to transfer the transmission data stored in the memory to the serial I / O unit, and the controller includes a plurality of first registers each having transfer information set therein. A second register in which the order of transfer by the plurality of first registers is set, and a memory access control unit that sequentially executes transfer by the plurality of first registers according to the transfer order set in the second register Since it has, the transmission data can be divided and arranged on the memory, and this can be sequentially transferred and transmitted by the controller connected to the dedicated bus.
The transmission data can be changed according to the setting of the second register.

Since a plurality of serial I / O units are provided, a plurality of serial transmissions can be performed.
Also, since the source address and the number of transfer bytes of the transmission data to be transferred are set in the first register,
Transmission data can be transferred by setting the first register.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing data transfer of the DMAC of the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a structure of a DMAC of the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing the operation of the DMAC of the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a structure of a serial I / O of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing an operation of serial I / O of the semiconductor integrated circuit according to the second embodiment of the present invention.

FIG. 7 is a diagram showing data transfer between memory serial I / Os of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a structure of serial I / O of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 9 is a diagram showing data transfer of a controller of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 10 is a diagram showing a structure of a controller of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

[Explanation of symbols]

1 CPU, 2 DMAC, 3 memory, 4 serial I / O, 5 timer, 6 internal bus, 7 DMA channel 1 setting register, 8 DMA channel 2 setting register, 9 sequence designation register, 10 DMAC control unit, 1
1 serial output, 13 transmission data setting register 1,
14 transmission data setting register 2, 15 order designation register, 16 memory access control unit, 17 serial transmission register, 18 dedicated bus, 19 controller, 2
0 Memory access control unit.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B061 DD11                 5B077 BB05 HH02 NN02

Claims (6)

[Claims] 1. A memory that stores transmission data, a serial I / O unit that serially transmits the transmission data stored in the memory, and a DMA that transfers the transmission data stored in the memory to the serial I / O unit. And a DMA controller having a plurality of channels for transferring transmission data, respectively.
A plurality of first registers in which transfer information is set respectively corresponding to a plurality of channels of this DMA, and a second register in which a transfer order of each channel of the DMA to be transferred using this first register is set. A semiconductor integrated circuit having a register and controlling the DMA so as to sequentially execute the transfer by each channel of the DMA according to the transfer order of the second register. 2. A memory storing transmission data, a serial I / O unit configured to transfer the transmission data from the memory for serial transmission, and the serial I / O unit.
The / O unit transfers the transmission data from the memory and serially transmits it, a plurality of first registers in which transfer information used to transfer the transmission data is set, and a plurality of the first registers. A second register in which a transfer order by one register is set, and the memory access control unit performs transfer by the plurality of first registers according to the transfer order set in the second register. A semiconductor integrated circuit characterized by being sequentially executed. 3. The semiconductor integrated circuit according to claim 2, wherein the memory and the serial I / O unit are connected by a dedicated bus. 4. A memory in which transmission data is stored, a serial I / O unit which is connected to this memory by a dedicated bus and serially transmits the transmission data stored in the memory, and which is connected to the dedicated bus and is connected to the memory. The controller is provided with a controller configured to transfer the stored transmission data to the serial I / O unit, and the controller includes a plurality of first registers in which transfer information is set and a plurality of first registers. A second register in which a transfer order is set, and a memory access control unit that sequentially executes transfers by the plurality of first registers according to the transfer order set in the second register. Integrated semiconductor circuit. 5. The semiconductor integrated circuit according to claim 4, wherein a plurality of serial I / O units are provided. 6. The semiconductor integrated device according to claim 1, wherein a source address of transfer data to be transferred and a number of transfer bytes are set in the first register. circuit.