JP2003235270A - Controller for voltage type inverter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a current ripple more uniform and smaller in magnitude. <P>SOLUTION: A controller for a voltage type inverter consisting of a plurality of self-arc-extinguishing switching elements is provided with a voltage vector selecting means for selecting a voltage vector on the basis of a vector angle of the deviation of a reference vector and a detected vector of an output current of an inverter, and a timing control means for controlling an output timing of a switching signal according to the voltage vector selected by the selecting means on the basis of an angle of the deviation vector and increment/decrement of a vector length. With this construction, the self-arc-extinguishing elements are controlled on the basis of the switching signal. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for controlling a voltage type inverter by a pulse width modulation (PWM) control system, and more particularly to a PWM signal based on a follow-up control operation of an instantaneous value of a current to a reference value. Instantaneous current value control type PWM to generate
The present invention relates to a voltage source inverter control device using a control method.

[0002]

2. Description of the Related Art As a conventional example, "Japanese Patent Application Laid-Open No. 10-1744"
No. 53 "and a part of" JP-A-2001-0784 "
FIG. 21 shows a configuration example of a current control device for an induction motor by a PWM control device using "No. 65".

In FIG. 21, 1 is a DC power supply, 2 is a smoothing capacitor for smoothing the output voltage of the DC power supply, and 3 is an inverter for converting the DC voltage output from the DC power supply 1 into a three-phase AC voltage.

The inverter 3 includes an upper self-extinguishing switching element SU, SV, SW for each phase of U, V and W, a lower self-extinguishing switching element SX, SY, SZ, and self-extinguishing switching. Each of the elements SX, SY and SZ is composed of a diode connected in antiparallel.

4 is an induction motor, 5U, 5V and 5W are in
Hall CT for detecting the output current of the barter 3; Hall 6
Output signals from CT5U, 5V, 5W are used by the control circuit
Analog or digital by scaling
Current detection value i_u, I_v, I _wWith a current detector that outputs
is there.

In FIG. 21, three-phase current detection values i _u , i _v ,
i _w is collectively referred to as a vector i.

Reference numeral 7 is a vector subtractor that subtracts the current detection vector i output from the current detector 6 from the current reference vector i ^* to be passed through the induction motor 4 and outputs the current deviation vector Δi. The equation (1) is calculated.

The vector subtractor 7 is a set of three subtractors for subtracting the phase current detection from the phase current reference.

Δi _u = i _u ^* -i _u Δi _v = i _v ^* -i _v ……………………………………………… (1) Δi _w = i _w ^* -i _w 8 from deviation vector .DELTA.i, a vector angle detector for obtaining the angle theta _.DELTA.i.

This vector angle detector 8 is a deviation vector
U, V, W coordinate components Δi of_u, Δi _v, Δi_w The below
According to the equation (2), three-phase two-phase conversion is performed and orthogonal two-phase xy coordinates are obtained.
Component Δi_x, Δi_yConvert to.

[0011]

[Equation 1]

Furthermore, the relational expression between the rectangular coordinates and polar coordinates in the vector

[Equation 2] And the angle θ _{Δi of the} deviation vector is obtained from the signs of Δi _x and Δi _y .

According to the conversion of the above equation (1), when the deviation vector points in the positive direction of the U axis, θ _Δi = 0.

Reference numeral 10 is a switching sequence circuit, and 11
Is a sequence starting circuit.

The switching sequence circuit 10 includes the angle θ _Δi of the current deviation vector and the sequence starting circuit 11
And outputs a switching command vector S _k .

The switching command vector S _k is a vector having the three-phase switching commands swu, swv, sww as components, and S _k = (swu, swv, sww).

Switching commands suu, swv, sww
Has a value of “1” or “zero”, “1” turns on the positive side element of the inverter 3 (the negative side element of the inverter 3 is off), and “zero” turns off the positive side element of the inverter 3 ( This means that the negative side element of the inverter 3 is turned on).

Further, _k of S _k is (swu, swv, s
1 is the binary number obtained by arranging the values of
It is a value converted into a decimal number.

(Swu, swv, sww) = (1, 0,
In the case of (0), it is a binary number “100” when written as it is, and “4” when converted to a decimal number, so S4 means (swu, swv, sww) = (1, 0, 0).

The value of k can be 0 to 7, and there are switching command vectors S0 to S7.

Switching command S_kDrive the inverter 3 with
The output voltage vector at the time of turning is V _kExpress with.

The voltage vector V _k when the DC voltage of the inverter 3 is Ed takes the values shown in Table 1 and is illustrated in FIG. 22.

In the voltage vectors V0 and V7, all three phases have the same potential, and the voltage is zero at any line, so that
The voltage vectors V1 to V6 are referred to as "zero voltage vectors", and the other voltage vectors V1 to V6 have magnitudes, and thus are referred to as "non-zero voltage vectors".

Further, the voltage vectors V0 and V7 and the switching vectors S0 and S7 may be referred to as "zero vector", and the other V1 to V6 and S1 to S6 may be referred to as "non-zero vector".

Since S0 to S7 and V0 to V7 correspond one-to-one, S0 to S7 may be referred to as voltage vectors.

[0026]

[Table 1]

12 is a switching sequence circuit 10.
Based on the PWM signal S _k (n) output from the six switching elements SU, SV, S forming the inverter 3.
This is a logic circuit that appropriately performs signal inversion, dead time processing, etc. in order to obtain signals to be provided to W, SX, SY, and SZ.

Numeral 13 insulates and amplifies the signal given from the logic circuit 12 to provide switching elements SU, SV, SW,
It is a gate circuit that supplies SX, SY, and SZ.

[0029]

[Table 2]

[0030]

[Table 3]

In the current instantaneous value control type PWM system, the alternating current and the current reference are compared at the instantaneous value level, and the output voltage of the inverter 3 is controlled so that the alternating current follows the current reference value.

Since the current change direction when outputting a non-zero vector falls within a predetermined angle range from the angle of the non-zero vector, it is easy to select the non-zero vector that causes the desired current change. .

However, the direction in which the current changes during the zero vector output depends on the induced voltage of the load and is therefore uncertain.

In the current control type PWM control method before the conventional example, the zero vector is used to generate a desired current change by directly or indirectly detecting the induced voltage.

A conventional example "Japanese Patent Laid-Open No. 10-174453"
The principle feature of is in the handling of this zero vector.

In this "JP-A-10-174453", only non-zero vectors are used to reduce the current deviation.

When the current deviation becomes sufficiently small, it is only moved to the zero vector and left as it is.

It does not matter in which direction the current is a zero vector.

The magnitude of the current deviation is monitored, and when the current deviation increases to a predetermined magnitude, the current deviation is controlled again by using only the non-zero vector.

When such control is repeated, the steady state is established in such a manner that the current deviation increases during the zero vector output and the current deviation decreases during the non-zero vector output.

Instead of determining the zero vector output period by the magnitude of the current deviation, if the cycle including the non-zero vector output period and the zero vector output period is controlled to be constant, the modulation frequency is controlled to be constant. It becomes possible.

The first control is to reduce the current deviation.
Non-zero vector → second non-zero vector → zero vector. This is performed by the switching sequence circuit 10.

The sequence starting circuit 11 controls the zero vector output period.

FIG. 23 shows a detailed configuration example of the switching sequence circuit 10.

In FIG. 23, reference numeral 60 denotes a current deviation vector angle θΔi, a switching command vector S _k (n) being output as a PWM signal, and a vector S _k (n used as a PWM signal before S _k (n). -1),
9 is a vector selection table for outputting a vector S _k (n + 1) to be selected when the output is changed next time.

Table 2 shows the contents of the vector selection table 60.
And shown in Table 3.

Table 2 is a table used when the switching command S _k (n) is a zero vector, and Table 3 is a table used when the switching command S _k (n) is a non-zero vector.

FIG. 24 shows an example of a voltage vector selection method from the zero vector.

When the zero vector in the output is v0, it follows FIG. 24 (a), and when it is v7, FIG.
Follow (b) of.

If the zero vector in the output is v0 and the deviation vector angle θΔi = π / 6, the deviation vector is closest to the deviation vector among the non-zero vectors V4, V2, V1 that can be transferred by switching only one phase. An angled non-zero vector V4 is selected.

Table 2 is a table of the above switching commands.

The voltage vector selection method from the non-zero vector is as follows: (1) If the voltage vector having the smallest angular difference from the deviation vector Δi is the voltage vector being output, the same vector as the vector being output is selected. (2) If the voltage vector having the smallest angular difference from the deviation vector Δi moves to either of the adjoining voltage vectors being output, it moves to that vector. (3) The vector being output and the deviation vector Δi If the angle difference of is 90 degrees or more, the zero vector is selected.

FIG. 25 shows an example of a selection method in the case of transition from V4.

In the case of (3) above, the zero vector V0,
Which of v7 should be selected is S _k(N-1) to S
_kDue to the switching performed when shifting to (n)
decide.

[0055] For example, even in S _k (n) is the same S4, if S _k (n-1) is S5, S6, etc., because they migrate off the positive side to S4, S _k Also for (n + 1), S0 that turns off the positive side is selected.

However, if S _k (n-1) is S0, S7 is selected as S _k (n + 1).

In this case, the transition from S4 to S7 causes the two phases to switch simultaneously.

The above is the vector selection logic of Table 3.

As described in (2) above, since the transition from the non-zero vector to the non-zero vector is performed only for the adjacent vector, when S _k (n) is the non-zero vector S4, S _k (n- The only non-zero vectors that may have been used as 1) are S5 and S6.

Similarly, from Table 2, the zero vector that may have been used as S _k (n-1) is S0.
Only.

Therefore, there are some combinations that are actually impossible even if they are used as the address signals of the look-up table.

Data is also written to such an address in the lookup table.

In Table 3, the impossible value of S _k (n-1) is described as "other".

The vector selection table 60 collectively contains the contents shown in Tables 2 and 3.

Reference numerals 61 and 62 denote latch circuits, which rewrite the output by data input at the rising timing of the clock pulse.

The output signal S _k (n + 1) from the vector selection table 60 is input to the data input of the latch circuit 61.
The output signal S _k (n) from the latch circuit 61 is applied to the data input of the latch circuit 62, respectively.

[0067] The output S _k from the latch circuit 61 (n), the output S _k from the latch circuit 62 (n-1) is, as an address signal for selection of Tables 2 and 3, the vector selection table 60 To be fed back.

The sequence activation command from the sequence activation circuit 11 is given to the AND circuit 65.

As the other input signal to the AND circuit 65, the output from the mismatch detector 66 is given.

The mismatch detector 66 checks whether or not the switching command S _k (n) being output as a PWM signal and the output S _k (n + 1) of the vector selection table are the same, and they are different signals. In that case, a logical value "1" is output.

The output signal from the AND circuit 65 is given to the OR circuit 67.

The output signal from the AND circuit 68 is also given to the OR circuit 67.

The AND circuit 68 includes the zero vector detector 6
The output signal from 9 and the output signal from the mismatch detection circuit 66 are ANDed.

The zero vector detector 69 includes a latch circuit 6
If the output from 2 is either S0 or S7, the logical value "1" is output.

The zero vector detector 70 outputs a logical value "1" when the output signal S _k (n + 1) from the vector selection table 60 is a zero vector.

The output signals from the AND circuit 65, the AND circuit 68, and the zero vector detector 70 are ORed by the OR circuit 67, and the result is given as one input signal to the AND circuit 71.

The other input terminal to the AND circuit 71 is
A clock pulse is given from a clock generator (not shown).

The output from the AND circuit 71 is given to the clock input terminals of the latch circuits 61 and 62.

As described above, the AND circuit 71 is the latch circuit.
Outputs the latch timing signal to 61 and 62
Is 1) Output S from the vector selection table 60_k(N +
1) and S being output as a PWM signal_kDifferent from (n)
Signal and a sequence start command is given 2) Output S from the vector selection table 60_k(N +
When 1) is a zero vector 3) Output S from the vector selection table 60_k(N +
1) and S being output as a PWM signal_kDifferent from (n)
Output S from the latch circuit 62 _k(N
-1) is a zero vector Is.

FIG. 26 shows a detailed configuration example of the sequence starting circuit 11.

The sequence starting circuit 11 detects a value whether the current deviation is within a predetermined allowable error range, and if it is not within the predetermined allowable error range, the allowable error comparator which outputs a starting signal to the switching sequence circuit 10 and the switching element A modulation frequency control circuit that outputs a start signal to the switching sequence circuit 10 so that the switching frequency becomes a predetermined modulation frequency.

The permissible error comparator 40 has a function of
01-078465 "and is provided as one input of each of the comparators 41u to 41w and the comparators 41x to 41z, the allowable error setting value 42, the multiplier 43, the AND circuits 44u to 44z, and the NOT circuit 45.
u, 45v, 45w, OR circuit 46, AND circuit 47,
It is composed of multipliers 48u, 48v, 48w, an adder 49, a comparator 50, and a multiplier 51.

The comparators 41u to 41w are provided with the allowable error set value 42 and the comparison level H / 2 given by the multiplier 43.
Is compared with the input, and as a result, if the input exceeds the comparison level, "1" is output.

The comparators 41x to 41z output "1" when the input is below the comparison level -H / 2.

FIG. 27 is a diagram for explaining the allowable error region of the allowable error comparator 40.

In the UVW coordinates in FIG. 27, the current reference is the origin of the coordinates.

The dotted lines of the U-phase, V-phase, and W-phase indicate the coordinates of the zero component of the current deviation, and the hatched lines on both sides thereof indicate the band-shaped permissible error region of width H for each phase. .

If the inverter output voltage is a non-zero vector, the current i _u decreases at swu = 0 and increases at swu = 1.

In FIG. 27, when swu = 0, the current i_uBut
Decrease, current i_uIs below the U-phase band
And i_u<I_u ^* -H / 2, that is, H / 2 <Δi
_u(= I_u ^* -I_u), The comparator 41u
The output from is "1".

Since swu = 0, the output from the NOT circuit 45U is also "1", so the output from the AND circuit 44U becomes "1", indicating that the current deviation does not fall within the allowable error region.

However, when swu = 0, sw
If v and sww are also zero, all the line voltages are zero, so the direction of current change is determined by the phase of the induced voltage.

Therefore, depending on the phase of the induced voltage, sw
Even when u = 0, the current i _u increases.

At this time, even if Δi _u <-H / 2 and the comparator 41x outputs "1", the AND circuit 4
The output from 4x is not "1".

The output from one comparator 41u is
Since it is zero, the output from the AND circuit 44u is also "1".
Does not mean

In this case, no matter how much the current i _u increases, the U-phase AND circuits 44u and 44x do not react.

[0096] However, at this time, i _v, because any of the current i _w is decreasing, the current deviation of the phase is larger than H / 2, of the phase AND circuit (44v, 44
Any one of w) outputs "1" to indicate that the value is out of the allowable error range.

In this way, the case where the inside of the hexagon formed by the intersection of the three-phase band areas becomes the allowable error area and the case where the star-shaped area including the small triangle outside the hexagon becomes the allowable error area There is.

That is, the width of the allowable error region indicated by the output signal from the OR circuit 46 changes.

If the width of the reference allowable error region changes, the magnitude of the current deviation cannot be controlled to be constant.

Therefore, in order to make the size of the allowable error area constant, a circular area having a radius H is used.

The multiplier 48u, 48v, 48w squares the current deviation of each phase, and the adder 49 adds them to obtain the square of the length of the current deviation vector. The square of the allowable error H output from the multiplier 51 is obtained. Is compared with the comparator 50 to determine whether or not the current deviation is included in the circular area.

The AND circuit 47 is used to allow the OR circuit 46 to output "1" as long as it is included in the circular area.

When the current deviation does not fall within the circular area, the current deviation does not fall within the belt-like area in any one of the three phases, and the switching conditions are also met, the sequence start command by the allowable error comparator is It is output from the AND circuit 47.

Here, if the allowable error area is only the circular area, only the switching signal of the specific phase changes at high speed,
Switching loss may destroy the device.

The hexagonal or star-shaped region formed by the intersection of the three-phase band regions is included in the circular region and does not function as the tolerance region, but the width of the band region extending outside the circular region. H functions to limit the upper limit of the switching frequency.

As a result, the switching element can be protected from damage due to switching loss.

The modulation frequency control circuit 52 includes a counter 5
3, comparator 54, cycle setting value 55, AND circuit 5
6, a zero vector detector 57 and a falling detector 58.

The counter 53 counts clock pulses given from a clock generator (not shown) and outputs the count value to the comparator 54.

The comparator 54 compares the count value with the cycle setting value 55, and as a result, when the count value exceeds the cycle setting value, outputs a logical value "1".

The output from the comparator 54 is input to the AND circuit 56.

The zero vector detector 57 outputs the components swu, swv, sww of S _k (n) as a PWM signal.
When all three phases are “0” or all three phases are “1”, a logical value “1” is output.

The output from the zero vector detector 57 is ANDed with the output from the comparator 54 in the AND circuit 56, and is output to the OR circuit 59 as a sequence start command by the modulation frequency.

The output from the zero vector detector 57 is given to the falling detector 58.

The trailing edge detector 58 detects the change timing of S _k (n) from the zero vector to the non-zero vector,
A count value clear signal is output to the counter 53.

As a result, the outputs from the comparator 54 and the AND circuit 56 also return to zero.

The AND circuit 56 is provided to wait for the sequence activation command until the last switching sequence is completed.

If the switching sequence is moved only by the output from the modulation frequency control circuit, the current deviation increases as the rotation speed of the electric motor increases.

This means that the period from the end of the switching sequence to the start of the next switching sequence, that is, the period during which the zero vector is output, becomes short.

In the case of the conventional example, as will be described later, there is a problem in the switching sequence, the pulse intervals of the generated switching signals are different, and the next sequence start command is issued before the switching sequence is completed at high rotation speed. May be given.

When the sequence activation command is given, the switching sequence circuit 10 can switch the switching signal as long as the output S _k (n + 1) from the vector selection table 60 is different from the switching signal S _k (n). Is rewritten to the value of S _k (n + 1).

If the next sequence start command is given before the switching sequence is completed, the switching sequence is disturbed and the current waveform is deteriorated.

The AND circuit 56 delays the output of the sequence start-up command until the end of the previous switching sequence, whereby the operating frequency range can be widened only by the output from the modulation frequency control circuit.

The output from the AND circuit 56 is the OR circuit 5.
After being logically ORed with the output of the allowable error comparator 40 at 9, it is given to the switching sequence circuit 10 as a final start command.

In parallel operation, when the current deviation is small and does not reach the comparison level of the tolerance comparator 40, only the modulation frequency control circuit 52 gives a start command to the switching sequence circuit 10 and the modulation frequency is controlled to be constant. .

When the current deviation is larger than the comparison level of the allowable error comparator 40, the counter 53 of the modulation frequency control circuit is cleared each time the activation command is issued from the allowable error comparator side.

Therefore, if the start command continues to be output from the allowable error comparator side in a cycle shorter than the cycle setting value 55, the start command from the modulation frequency control circuit side will not be output.

That is, during the parallel operation, the modulation frequency control circuit functions as the lower limit of the switching frequency.

In Japanese Patent Laid-Open No. 10-174453, since the pulse waveform changes automatically and stably in accordance with the change in operating frequency, the PWM control with a constant modulation frequency in the stationary state of the electric motor causes A wide operating frequency range of variable speed drive can be covered only by this PWM method up to a square wave 1 pulse operation in a constant output range.
I control, dead time compensation, induced voltage compensation, and other controls that do not require adjustment are required. Strong against DC voltage fluctuations and load motor constant changes, non-sinusoidal current drive is possible, not only motor load, but voltage source inverter It has features such as general applicability.

[0129]

However, the conventional voltage source inverter control device as described above has the following problems.

[First Problem] FIG. 28 shows an example of a simulation waveform according to a conventional example.

Current reference i _u ^* , current i _u , output TR from modulation frequency control circuit, output ER from tolerance comparator, output from AND circuit 71 (latch circuits 61, 6
2 operation clock) RES, switching signal swu,
swv, sww, and the line voltage waveform Vuv are shown.

In the current waveform of FIG. 28, the magnitude of the current ripple is not uniform, and the pulse width of the switching signal is also different.

Regarding these causes, FIG. 29 and FIG.
A description will be given based on 0.

FIG. 29 is a diagram showing a relation of vectors used for explaining the operation of FIG.

The vector indicated by e is the induced voltage, v4, v
5 is a non-zero voltage vector already described, and v0 and v7 are zero voltage vectors.

When the inverter 3 outputs the voltage V _k , the voltage equation of the induction motor 4 which is the load of the inverter 3 is

[Equation 3] And, when the resistance is disregarded and transformed

[0137]

[Equation 4] Is.

From this equation, the current is the vector (V _k -e)
Changes in the same direction as, and changes at a speed of | V _k −e | / L.

That is, the inverter 3 outputs the voltages v4 and v5.
When outputting the current, the current is
4-e), (v5-e).

The current during the output of the zero voltage vectors v0 and v7 changes in the -e direction.

FIG. 30 is a diagram showing the locus of the vector −Δi in which the signs of the current deviation are reversed.

The rear end of the current deviation vector moves along the thick line in FIG. 30, and the front end of the current deviation vector is always at the origin of the coordinates.

In other words, it is the locus of the current in the coordinate space whose origin is the current reference (hereinafter referred to as the current reference coordinate).

In the description of the present invention, the term "current locus" means all loci on the current reference coordinates.

In FIG. 30, for the sake of simplicity of explanation, the current locus is drawn by using the current changing direction shown in FIG. 29 with the current reference and the induced voltage being constant.

The circle is the boundary of the allowable error area.

Further, the angle of the current deviation vector at the boundary for switching the signal output from the vector selection table 60 is shown by a dotted line, and the value of the angle is added from 0 to 11π / 6.

Hereinafter, at the time t0 when the switching sequence is moving by a start command with a constant tolerance and the current is at the origin of the coordinates and the current deviation is 0, the switching sequence circuit causes the zero vector S _k (n) = The operation of the switching sequence will be described while following the current locus after the output of S7.

The current vector is voltage (v7-e) =-e
Changes in the t1 direction in FIG.

The current deviation vector Δi (= i ^* -i) is
Since it extends from the tip of the current vector to the origin of the coordinates (tip of the current reference vector), from time t0 to t1,
The angle θΔi is 5π / 3 <θΔi <11π / 6.

Since this angle and S _k (n) = S7, the vector selection table 60 is based on Table 2.
It outputs S _k (n + 1) = S5.

At time t1, the boundary of the permissible error area is reached and the start signal is given from the sequence start circuit 11.

S _k (n) = S7, S _k (n + 1) = S5
Since the mismatch detection circuit 66 outputs the logical value "1", the logical value "1" is given to the AND circuit 71 through the AND circuit 65 and the OR circuit 67, and the latch circuit 61, 62 operates and S _k (n) =
S5 and S _k (n-1) = S7.

The change from the zero vector to the first non-zero vector S5 causes the current to change at (v5-e) and changes to the position at t2.

During this period, since 5π / 3 <θΔi <11π / 6, the vector selection table 60 is calculated from Table 3 to S5.
Is being output.

S _k (n) = S _k (n + 1) and S _k (n
Since +1) is not a zero vector, the OR circuit 67
Since the output from is zero, no clock pulse is given to the latch circuits 61 and 62.

At time t2, when the current vector reaches the dotted line and enters the region of 11π / 6 <θΔi <2π, S
_k (n + 1) becomes S4, and the output from the mismatch detection circuit 66 changes to "1".

Since S _k (n-1) is S7 and the output from the zero vector detector 69 is also "1", the AND circuit 6
The output from the OR circuit 67 becomes "1" via 8, and the operation clock is given to the latch circuits 61 and 62.

S _k (n) = S4, S _k (n-1) = S5
Will change.

After time t2, the second non-zero vector S4
Causes the current to change to the position of t3 at (v4-e).

Returning to the region where θΔi is smaller than 11π / 6, S _k (n + 1) = S5.

Further, along the way, beyond the dotted line, θΔi is 5
It is smaller than π / 3, but from Table 3, S _k (n + 1)
Remains at S5.

During this time, the mismatch detection circuit 66 outputs "1".
I'm trying, but S_k(N-1), S _k(N + 1) together
Since it is a non-zero vector, the sequence start command
Unless otherwise provided, the clock is applied to the latch circuits 61 and 62.
I can't.

At time t3, when θΔi enters a region smaller than 3π / 2 and S _k (n + 1) = S0, the output from the zero vector detection circuit 70 becomes “1”, and the OR circuit 67, AND gate. Latch circuit 6 via circuit 71
An operation clock is given to 1, 62.

S _k (n) = S0, S _k (n-1) = S4
Change to.

After the time t3, the current changes in the vector -e as in the time t0 to t1.

ΘΔi immediately returns to a region larger than 3π / 2.

The vector selection table 60 outputs S _k (n + 1) = S1 based on Table 2.

Now, the mismatch detection circuit 66 outputs "1", but since both S _k (n-1) and S _k (n + 1) are non-zero vectors, unless a sequence start command is given, No clock is applied to the latch circuits 61 and 62.

At time t4, when the current vector goes out of the allowable error region, the sequence start-up circuit 10 gives a start-up command, and the latch circuits 61 and 62 operate.

S _k (n) = S1, S _k (n-1) = S0
Therefore, the vector selection table 60 is
_k (n + 1) = S5 is output.

Since the mismatch detection circuit 66 and the zero vector detector 69 both output "1", the output from the AND circuit 68 becomes "1", and the latch circuits 61 and 62 operate at the next clock t5. S _k (n) = S5, S _k (n−
1) = S1.

S _k (n) = S1 immediately changes to S _k (n) = S5 only during one clock.

After that, the current changes at (v5-e).

Since S _k (n-1) is a non-zero vector, a start command is given or S _k (n + 1)
Until a zero vector is output by the latch circuit 61, 62.
Does not work.

At time t6, when θΔi exceeds the line of π / 6, S _k (n + 1) = S7 is output from Table 3.

As described above, the output S from the switching sequence circuit is obtained by the two switching sequences from t0 to t6.
_k (n) is as follows: S7 → S5 → S4 → S0 → S1 → S5 → S7. From the state where the positive side element is turned on for all three phases of the inverter 3 (S7), the negative side element is turned on one by one in sequence. Then S0
Then, the positive side element is turned on for each phase, the state is returned to the state of S7, one pulse is output for all the three phases, and the state is returned to the original state.

This corresponds to one cycle of the triangular wave of the triangular wave comparison PWM.

In the current locus of FIG. 30, the locus at the end of the sequence appears twice at t3 and t6, but the current deviation at time t3 is considerably larger than at time t6.

That is, the non-zero voltage vector from the time t1 to the time t3 is not useful for reducing the current deviation as much as the non-zero voltage vector from the time t4 to the time t6.

This is the reason why the current ripple is large relative to the number of times of switching.

The reason why the current ripple is not uniform is that there is a large variation in the position of the current at time t3.

[Second Problem] In the PWM control logic of the conventional example, there is a portion where a reverse pulse is easily generated.

The PWM signal _k at t0 to t6 in FIG.
(N) changes as follows: S7 → S5 → S4 → S0 → S1 → S5 → S7.

FIG. 31 shows an example of a waveform in which this switching order is converted into a PWM signal for each phase, and a line voltage waveform drawn by taking the difference between the PWM signals for each phase.

Each phase signal has one pulse, but two pulses appear in the line voltage waveform.

Here, in the line voltages Vuv and Vvw, 2
Although the two pulses have the same polarity, only the line voltage waveform Vwu has a different polarity.

It is natural that such a pulse appears where the sign of the fundamental wave of the line voltage changes, but the appearance of the pulse without changing the sign of the fundamental wave only increases the harmonics. Is.

The pulse appearing in the reverse direction will be referred to as a reverse pulse hereinafter.

An inverse pulse also appears in the simulation waveform according to the conventional example shown in FIG.

In the output from the PWM control circuit, even if the width of the reverse pulse is narrow, the pulse width may be widened by the minimum width circuit before giving it to the switching element. Should try not to appear as much as possible.

The cause of the reverse pulse is that in the switching sequence of the conventional example, when the first non-zero vector is selected, there is a constraint that it can be selected only from the non-zero vectors that can be transferred by switching one phase from the zero vector. There is something to do.

Although it was not necessary to output S1, it was output only during one sampling due to the restriction of the switching sequence.

[Third Problem] Sequence start-up circuit 11
In the OR circuit 59, the OR circuit 59 logically adds and outputs the sequence start command output from the constant allowable error comparator 40 and the sequence start command output from the modulation frequency control circuit 52.

First, the change of the pulse mode by the sequence starting circuit 11 will be described.

If the rotation speed of the load motor is low, the current deviation can be controlled within the tolerance circle by controlling the modulation frequency constant, so that the sequence start command is not output from the tolerance comparator side.

As the number of revolutions increases, the induced voltage increases and the change in current becomes faster, resulting in a larger current deviation.

When the current deviation exceeds the number of revolutions reaching the allowable error circle, the allowable error comparator 40 outputs a sequence start command, and the current deviation is controlled to fall within the allowable error circle.

At this time, if the sequence activation command is continuously output from the modulation frequency control circuit 52, the switching sequence circuit 10 receives the sequence activation command from both sides, and when the allowable error comparator 40 operates independently. The number of pulses increases.

Therefore, in order to avoid this, the counter 53 of the modulation frequency control circuit is cleared at the change timing from the zero vector to the non-zero vector (start timing of the switching sequence).

As a result, when the frequency of the start command from the allowable error comparator side is higher than the frequency of the start command from the modulation frequency control circuit 41 side, the start command from the modulation frequency side is not output.

As described above, when the rotation speed becomes high, only the allowable error comparator 40 outputs the start command.

In the PWM based on the start command on the allowable error comparator side, the PWM control is performed so as to keep the current deviation within the allowable error range.

As the rotational speed increases and the change in current due to the induced voltage becomes faster, the switching frequency also becomes higher.

However, as the number of revolutions further increases, the difference between the motor terminal voltage and the induced voltage decreases, so that the current change due to the terminal voltage becomes slow and the current cannot follow the current reference change.

Therefore, the current deviation is very long, and the vector does not fall within the tolerance circle as a vector.

The angle change of the current deviation becomes gradual.

It does not shift to the zero vector, and only switches to the adjacent non-zero vector.

[0209] The switching frequency is decreasing more and more,
The number of pulses is reduced.

Here, it is assumed that the operating frequency of the electric motor is 50 Hz and the number of PWM pulses is 5 when the modulation frequency control circuit sets the cycle so that the modulation frequency becomes 2 kHz.

In this case, the frequency on the modulation frequency control circuit side is high, but the start command is not output from the modulation frequency control circuit side.

This is because, even if the output from the comparator 54 of the modulation frequency control circuit becomes "1", the output from the AND circuit 56 does not become "1" unless the zero vector is output.

Therefore, when the rotation speed is high and the number of pulses is small, the switching sequence is moved only by the start command from the allowable error comparator side.

As described above, in the PWM based on the tolerance comparator, the number of pulses automatically changes depending on the magnitude and frequency of the current command.

Particularly, in the region where the number of pulses is small, pulse waveforms synchronized with the frequency of the current command, such as 5 pulses and 7 pulses, can be obtained.

FIG. 32 shows the loci of currents in the current reference coordinates in the case of 5 pulses between lines, in which the U-phase current and each phase PWM signal are
The time waveform of the line voltage is shown in FIG. 33.

At high revolutions where the induced voltage of the load motor is high,
As shown in FIG. 32, it becomes impossible to fit the current in the circular tolerance region.

Therefore, the PWM is performed based on the band-shaped region in which the switching condition is taken into consideration.

As shown in FIGS. 32 and 33, during the short period when the current deviation of one of the phases is close to zero, several times of switching are concentrated by the activation from the tolerance comparator side, After that, the changing direction of the current is changed, and the current deviation of the phase being switched is changed in the opposite direction.

At times t1, t3, and t5 in FIG. 33, sw
Since u = 0, the current i _uIs the negative margin of error
Side boundary, Δi_u(I_u ^*-I_u)> H / 2
It

At this time, since the AND circuit 44u outputs "1", the switching sequence circuit is operated by the start command.

As a result, swu = 1 is changed.

Similarly, at times t2 and t4, suu = 1
As a result, the current i _u reaches the positive side boundary, and the AND circuit 44x outputs "1" to operate the switching sequence circuit, which changes to suu = 0.

However, some time after t5, the direction of current change changes, and the current i _u begins to decrease even though swu = 1.

The current i _u reaches the negative boundary and Δi _u > H
/ 2, and even if the output from the comparator 41u changes to "1", since swu = 1, the AND circuit 44u
The output from is not "1".

The same is true for the other phases, and the component of any phase of the current deviation does not enter the band area, but the allowable error comparator does not output the start command.

Then, during the period in which this activation command is not output, the angle of the deviation vector continues to be slightly less than 60 degrees.

After that, the same series of switching operations as described above are performed in the other phases.

As described above, since all switching is performed based on the width H of the strip-shaped region, the minimum width of the pulse is also determined by the width H.

When the number of pulses decreases such as from 7 pulses to 5 pulses or from 5 pulses to 3 pulses, two pulses disappear, but both of them have a minimum width determined by the width H. have.

If this width is wide, the change in the low-order harmonic component of the voltage is large when the number of pulses changes, and the current waveform is strongly affected by the number of pulses.

Further, since the voltage change due to the two lost pulses is compensated for, the widths of all other pulses change, so that the number of pulses has hysteresis.

Both the voltage change when the number of pulses changes and the hysteresis of the number of pulses are problems.

If the pulse width disappears after being sufficiently narrowed, the change in voltage due to the disappearance becomes small, and the change in the width of other pulses can be small.

As a result, the hysteresis of the pulse number also becomes small.

Therefore, the pulse width can be narrowed by reducing the width H of the permissible error region.

However, this is not preferable because the width of all the pulses becomes narrow and the number of pulses increases all at once.

An object of the present invention is to provide a control device for a voltage source inverter which can make the magnitude of current ripple more uniform and small.

Another object of the present invention is to provide a control device for a voltage source inverter which can reduce the number of reverse pulses as compared with the prior art.

A further object of the present invention is to provide a control apparatus for a voltage source inverter capable of reducing the voltage change at the time of switching the pulse number at the time of high rotation / small number of pulses as compared with the prior art.

[0241]

In order to achieve the above object, in a control device for a voltage type inverter, which is constituted by using a plurality of self-arc-extinguishing type switching elements, a control device for a voltage type inverter is provided.
In the invention corresponding to, based on the angle of the vector of the deviation of the reference vector of the inverter output current and the detection vector, voltage vector selection means for selecting the voltage vector,
Based on the angle of the deviation vector and the increase or decrease of the vector length,
A timing control means for controlling the output timing of the switching signal corresponding to the voltage vector selected by the voltage vector selection means is provided, and the self-extinguishing element is controlled based on the switching signal.

Therefore, in the control device for the voltage source inverter of the invention corresponding to claim 1, the magnitude of the current ripple can be made more uniform and smaller by taking the above means.

In the invention according to claim 2, an angle detecting means for detecting an angle and an increase / decrease detecting means for detecting an increase / decrease in vector length of a vector of a deviation between the reference vector of the inverter output current and the detected vector, A non-zero vector switching signal is output based on the angle of the deviation vector detected by the angle detection means and the increase / decrease detection means and the increase / decrease of the vector length, and switching control is performed, and predetermined termination is performed. When the condition is satisfied, a switching vector generating means for outputting a zero vector switching signal to end a series of sequences, and a sequence starting means for outputting a start command to the switching sequence generating means are provided. Controls the operation mode as PWM control according to how to give a command It has to so that.

Therefore, in the control device for the voltage source inverter of the invention according to claim 2, the magnitude of the current ripple can be made more uniform and smaller by taking the above means.

Further, in the invention according to claim 3, an angle detecting means for detecting an angle and an increase / decrease detecting means for detecting an increase / decrease in the vector length of the vector of the deviation between the reference vector of the inverter output current and the detected vector, A non-zero vector switching signal is output based on the angle of the deviation vector detected by the angle detection means and the increase / decrease detection means and the increase / decrease of the vector length, and switching control is performed, and predetermined termination is performed. When a condition is satisfied, a switching sequence generating means for outputting a zero vector switching signal and ending a series of sequences,
A sequence starter that outputs a start command to the switching sequence generator based on a combination of the current deviation state and the switching signal or a predetermined cycle, and a self-extinguishing type switching element based on the switching signal. I'm trying to control.

Therefore, in the control device for the voltage source inverter of the invention according to claim 3, the magnitude of the current ripple can be made more uniform and smaller by taking the above means.

On the other hand, in the invention corresponding to claim 4, in the control device for the voltage source inverter of the invention according to claim 2 or 3, the switching sequence generating means holds the output history of the switching signal. When the history holding unit and the zero vector switching signal are output, one of the six non-zero vectors is selected based on the output history of the switching signal and the angle of the deviation vector, and the non-zero vector is also selected. When outputting the vector switching signal, if the non-zero vector with the smallest angle difference from the deviation vector is the non-zero vector being output or the non-zero vector adjacent to it, the non-zero vector with the smallest angle difference is output. If you choose a zero vector and the non-zero vector with the smallest angular difference from the deviation vector is none of the above A vector selection unit that selects one of the two zero vectors from the output history held by the history holding unit, an output signal from the vector selection unit, an output history held by the history holding unit, and an external Based on the start command and the vector length increase / decrease detection result,
It comprises a logical operation unit for controlling whether or not the switching signal is changed to a signal corresponding to the vector output by the vector selection unit at that time.

Therefore, in the control device for the voltage source inverter of the invention according to claim 4, the magnitude of the current ripple can be made more uniform and small by taking the above means.

Further, in the invention corresponding to claim 5, in the control device for the voltage source inverter of the invention according to claim 2 or 3, the switching sequence generating means holds the output history of the switching signal. Based on the history holding unit, the history signal output by the history holding unit and the angle of the deviation vector, the vector selection unit that selects the voltage vector, and if the output from the vector selection unit is a zero vector, immediately or When the increase / decrease detection signal indicates an increase in the current deviation vector, and if the output from the vector selection unit is not a zero vector, the previous value held by the output history holding unit is a zero vector and switching during output is in progress. The vector of the signal and the vector output by the vector selection unit are different, and the increase of the current deviation vector is further increased or decreased. The vector output by the vector selection unit at the time indicated by the output signal, or when the vector of the switching signal being output is different from the vector output by the vector selection unit and a start command is given from the outside. And a logical operation unit that outputs a switching signal corresponding to.

Therefore, in the control device for the voltage source inverter of the invention according to the fifth aspect, the magnitude of the current ripple can be made more uniform and small by taking the above means.

As described above, it is possible to obtain the control device for the voltage source inverter which can make the magnitude of the current ripple more uniform and small.

On the other hand, in the invention according to claim 6, in the control device of the voltage source inverter according to the invention according to claim 2, the switching sequence generating means is:
If the output of the switching sequence generating means is a zero vector and only one-phase switching is required when shifting from the previous value held by the output history holding unit to the zero vector, the non-zero vector of the previous value and its adjacent A vector that selects a vector based on the angle of the deviation vector from the three non-zero vectors that have been set, and when two-phase switching is required, from the two adjacent non-zero vectors. It is assumed to have a selection unit.

Therefore, in the control device for the voltage source inverter of the invention according to claim 6, the reverse pulse can be made smaller than in the conventional case by taking the above means.

Further, in the invention corresponding to claim 7, in the control device of the voltage source inverter according to claim 4 or claim 5, the vector selecting unit outputs the zero vector as the switching sequence generating means. If the increase / decrease detection signal indicates an increase in the deviation vector, the previous value held by the output history holding unit is a zero vector, and the zero vector shifts to the switching signal being output. At the time of 1
When only phase switching is required, the vector output by the vector selection unit does not match the vector generated by the switching signal being output, and when the increase / decrease detection signal indicates an increase in the deviation vector, In this case, when the vector output by the vector selection unit does not match the vector output by the switching signal and the vector output by the vector selection unit and the start command is given from the outside, the vector selection at that time point is selected. It is assumed to have a logical operation unit that outputs a switching signal corresponding to the output from the unit.

Therefore, in the control device for the voltage source inverter of the invention according to the seventh aspect, the reverse pulse can be further reduced as compared with the conventional case by taking the above means.

Further, in the invention corresponding to claim 8, in the control device for the voltage source inverter of the invention corresponding to claim 2 or claim 3, the invention corresponding to claim 4 as the switching sequence generating means. And the logical operation unit of the invention corresponding to claim 5 above.

Therefore, in the control device for the voltage source inverter of the invention according to claim 8, the reverse pulse can be further reduced as compared with the conventional case by taking the above means.

As described above, it is possible to obtain the control device for the voltage source inverter which can reduce the reverse pulse as compared with the conventional one.

On the other hand, in the invention corresponding to claim 9, in the control device for the voltage source inverter of the invention according to claim 2 or claim 3, the sequence starting means serves as the predetermined amount ± of the current deviation of each phase. The current deviation is present in the area obtained by the logical sum of the first allowable error area based on H / 2 and the sign of the switching signal and the second allowable error area based on the predetermined amount H of the length of the current deviation vector. Based on the comparison result of whether or not it is included, a permissible error comparison and determination unit that outputs a first start command and a permissible error comparison and determination unit that outputs a signal every time a predetermined time elapses after measuring the time. First from
And a flip-flop that is set by the output signal from the timer and holds the second start signal and is reset each time the switching sequence generating means changes the switching signal. The logical sum of the first start command and the second start command gives the start command to the switching sequence generating means.

Therefore, in the control device for a voltage source inverter of the invention according to claim 9, by taking the above-mentioned means, the voltage change at the time of switching the pulse number at the time of high rotation and a small number of pulses is more than that of the conventional case. It can be reduced.

Further, in the invention corresponding to claim 10, in the control device for the voltage source inverter of the invention according to claim 2 or claim 3, the sequence starting means is a predetermined amount ± of the current deviation of each phase. The current deviation is present in the area obtained by the logical sum of the first allowable error area based on H / 2 and the sign of the switching signal and the second allowable error area based on the predetermined amount H of the length of the current deviation vector. Based on the comparison result of whether or not it is included, a permissible error comparison and determination unit that outputs a first start command and a permissible error comparison and determination unit that outputs a signal every time a predetermined time elapses after measuring time. First from
And a timer initialized by the fall timing detection signal of the second start instruction, and the second start signal which is set by the output signal from the timer and holds the second start signal. And a fall detection unit that detects the fall timing of the second start command, the logical sum of the first start command and the second start command. A starting instruction is given to the generating means.

Therefore, in the control device for a voltage source inverter of the invention according to claim 10, by taking the above-mentioned means, the voltage change at the time of switching the pulse number at the time of high rotation / small number of pulses is higher than that of the prior art. It can be reduced.

As described above, it is possible to obtain the control device of the voltage source inverter which can reduce the voltage change at the time of switching the pulse number at the time of high rotation / small number of pulses as compared with the prior art.

[0264]

BEST MODE FOR CARRYING OUT THE INVENTION First, the concept of the present invention will be described before describing the embodiments of the present invention.

First, the concept of the first invention will be described.

If S5 is continuously output at the time t2 in FIG. 30, the current deviation continues to decrease for a while, but since the current deviation is switched to S4 at the time t2, the current change deviates from the desired direction. There is.

During the subsequent time t2 to t3, the current deviation cannot be reduced so much even if the timing of shifting from S4 to the zero vector is changed.

In order to effectively reduce this current deviation, it is necessary to change the transition timing from the first non-zero vector (S5) to the second non-zero vector (S4).

Then, attention is paid to "change in length of current deviation vector" as a criterion for determining the transition timing from the first non-zero vector to the second non-zero vector.

That is, at time t2, since the deviation vector is shortened by the first non-zero vector, it is not necessary to shift to the second non-zero vector.

It is sufficient to switch to the second non-zero vector at the time when the current goes too far at the shortest point of the deviation vector and the deviation vector begins to become long.

[0272] For this, the selection of S _k (n + 1) is performed by conventional as well as θΔi, but the timing of rewriting the S _k (n) with the value of S _k (n + 1) is the current deviation vector length of Decide by increase or decrease.

FIG. 34 is a diagram for explaining how the locus of the current in the current reference coordinates is changed by this, and it is the same as FIG. 30 from time t0 to time t1.

The time point t2 at which S5 is switched to S4 is changed to the shortest point of the current deviation vector.

This time point can be obtained by plotting by drawing a perpendicular line from the origin of the coordinates on the straight line of the locus of the current after time t1.

The angle of the deviation vector at the shortest point t2 is 0.
Since <θΔi <π / 6, the process proceeds to S4 from Table 3,
S _k (n) = S4 and S _k (n−1) = 5.

The second non-zero vector S4 is continuously output until the angle formed by the voltage vector and the current deviation vector being output is ± 90 degrees or more.

Since the angle of v4 is 0 degree, the angle difference becomes 90 degrees at time t3 when θΔi becomes 3π / 2 in FIG. 34, and the vector shifts to the zero vector v0.

The current changes with -e until time t4 when the boundary of the allowable error region is reached.

The angle of the deviation vector at time t4 is
5π / 3 <θΔi <11π / 6, and from Table 2, the first
S4 is chosen as the non-zero vector of

Also in S4, after the current deviation vector is output until time t5 when it becomes the shortest, it is switched to the second non-zero vector S5.

At time t6, the zero vector is entered,
The switching for one pulse (corresponding to one cycle of the triangular wave) is completed.

The most direct means for obtaining the transition timing for realizing the switching sequence as shown in FIG. 34 is to obtain and store the length of the current deviation vector for each control sampling, and store the previously stored current deviation vector. Compare with the length of the vector.

The same transition timing can be detected based on the angle formed by the current locus and the current deviation vector.

In the process in which the current approaches the reference, the angle formed by the locus of the current and the current deviation vector is 90 degrees or less, which is 90 degrees at the shortest point.
It becomes 0 degrees or more.

Since the angle of the current deviation vector has already been obtained and used, the angle of the current locus, that is, the difference between the previous value and the current value of the current vector is calculated, and that angle is detected to obtain the current deviation vector. Just take the difference.

Since the current vector is also detected, it is only a problem of calculation.

The same transition timing can be detected from the angle change amount of the current deviation vector.

In FIG. 34, the current moves on a straight line at a constant speed from time t1 to time t2.

The angle change of the current deviation vector at that time is
The shorter the current deviation vector, the larger the current deviation vector.

Therefore, the difference Δθ from the previous value of the angle θΔi of the current deviation vector detected for each control sampling is also obtained and stored, and if this difference Δθ becomes smaller than the previous value, the transition timing is set. Good.

Next, the concept of the second invention will be described.

Looking at the voltage vector of FIG. 22, V4
And V1 are 120 degrees apart.

In the conventional example, in the switching sequence of (zero vector) → first non-zero vector → second non-zero vector → zero vector, two non-zero voltage vectors and zero voltage adjacent to each other in FIG. Although the constraint that only the vector is used is provided, no constraint is provided between one switching sequence and the next switching sequence.

For this reason, vectors that are 120 degrees apart have appeared.

Therefore, even between the continuous PWM sequences, at the start of the switching sequence for shifting from the zero vector to the non-zero vector, only the second non-zero vector of the previous sequence or the non-zero vector adjacent to the second non-zero vector. Set a constraint that a vector cannot be selected.

However, when shifting to the non-zero vector adjacent to the previously output non-zero vector, two-phase switching is required.

For example, when the sequence is ended by shifting from S4 to S0 and the next sequence is started at S6, two phases, U phase and V phase, are simultaneously switched.

At this time, in the circuit of FIG. 23, S _k (n
Since −1) is a zero vector only, it is identified whether it is the first or second non-zero vector, so S6 is treated as the first non-zero vector.

In this state, S4 and S2 adjacent to S6
There is a possibility that it will move to any of the vectors.

In the conventional example, 1 is always set at the start of the sequence.
Since only a vector that can be transferred by phase switching is selected, the circuit shown in FIG. 23 is acceptable. However, in the case of performing simultaneous switching of two phases, it should be treated as a transfer from the zero vector to the second non-zero vector immediately. Is.

For this purpose, the zero vector detector 69
Instead of S _k (n-1) is a zero vector, and S _k (n) is a vector that can be transferred from S _k (n-1) by one-phase switching, the first non-vector A discriminator circuit for zero vector is provided.

Next, the concept of the third invention will be described.

In the present invention, the position of the pulse is moved to the end where the influence of the fundamental wave component of the voltage is small, and at the same time, the pulse having a narrow width can be output.

For this reason, not only the allowable error range but also the timer is used to output the start command.

In the PWM in the allowable error region, when the changing speed of the current deviation changes, the pulse width is changed in accordance with it, and the current deviation is contained in the same area.

A non-zero vector whose current changing speed is slow is output for a long time, and a non-zero vector whose current changing speed is fast is output for only a short time.

Looking at FIG. 33, between time t1 and time t2,
Between time t3 and time t4 is wide, between time t2 and time t3,
It is narrow between time t4 and time t5.

[0309] Also, between time t1 and time t2 and between time t3 and.
Compared with time t4, time t3 to time t4 is wider.

On the other hand, between time t1 and time t3 and between time t3 and
Comparing with the time t5, the area is not so different.

During this time, the current deviation fluctuates within a certain allowable error width as shown in FIG.

The above pulse width relationship indicates that the time spent for going and returning the permissible error width is different, but the round-trip time is not so different.

Therefore, the timer measures the time after switching, and the start command is output when a predetermined time has elapsed.

The predetermined time of the timer is set from time t1 to time t
If it is set to be longer than the time of 2 and shorter than the time of time t3 to time t4, the switching from time t1 to time t3 remains as it is, only time t4 approaches time t3, and time t3 to time t4. Time is reduced.

Since the switching at the time t4 is performed before the current deviation changes only by the allowable error, the time t4 to t5 for returning to the opposite side is also shortened.

As a result, the pulse between time t4 and time t5 is moved forward to approach time t3, and at time t4.
~ Time t5 can be shortened.

When the pulse moves forward, the influence on the fundamental wave component of the voltage decreases.

Since the pulse width is also narrowed, the effect on the voltage when the pulse disappears from time t4 to time t5 is reduced by both effects.

When the permissible error width H is narrowed, the number of times of switching increases all at once. However, according to this method, only the width of the pulse approaching disappearance can be selectively narrowed. Is small.

This timer may be newly added, but it can also serve as the timer of the modulation frequency control circuit.

In terms of electric motor control, the modulation frequency control circuit operates in the low rotation speed region, does not operate when the rotation speed becomes high to some extent, and operates on the allowable error comparator side instead.

A new timer is used in a region where the number of rotations becomes higher and the number of pulses becomes smaller.

It is not necessary for the two timers to operate at the same time.

However, when one timer also serves as the timer, the AND circuit 56 must be omitted so that the activation signal can be output from the modulation frequency control circuit side even at high rotation.

Since the AND circuit 56 is provided in order to avoid the deterioration of the current waveform at the high rotation during the control with the constant modulation frequency, it is omitted if the control is switched to the constant allowable error at the high rotation. can do.

According to the first invention proposed at the same time this time, the current waveform is remarkably improved.
Even if it is omitted, the current control can be performed by the control with the constant modulation frequency up to the rotation speed higher than that of the above-mentioned conventional example.

If the timer is cleared every time the switching signal changes, PWM with a constant modulation frequency cannot be performed. Therefore, the timer output is changed from the conventional level to a pulse, and the flip-flop is set by the pulse, and the flip-flop is set. The output is used as the start command from the timer side.

Each time the switching signal changes, the flip-flop is reset instead of clearing the timer.

In the above-mentioned conventional example, the counter of the modulation frequency control circuit is cleared at the start timing of the switching sequence (the change timing from the zero vector to the non-zero vector), but with this method, the clear signal is generated at high rotation. Does not appear.

In the above-mentioned conventional example, the modulation frequency control was used only in the low rotation range, which is all right, but in the present invention, it is necessary to clear the timer even in the high rotation.

For this reason, the timer is cleared by a start command on the allowable error comparator side or is cleared by the logical sum of the start command on the allowable error comparator side and the start command on the timer side (flip-flop output).

Hereinafter, embodiments of the present invention based on the above concept will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a configuration example of a current controller for an induction motor to which a controller for a voltage source inverter according to the present embodiment is applied.
The same components as those in the conventional example described above are designated by the same reference numerals, and the description thereof will be omitted. Here, only different parts will be described.

In FIG. 1, the vector angle detector 8 may be calculated from the current deviation component as in the conventional example described above, but the calculation of the sine wave function imposes a heavy load on the microcomputer, and other factors. The sacrifice of time for processing is sacrificed.

FIG. 2 is a block diagram showing a configuration example of the vector angle detector 8 for detecting an angle at high speed.

As shown in FIG. 2, the comparators 20u,
20v, 20w, 20uw, 20vu, 20wu, subtractors 21uw, 21vu, 21wu, and a logic circuit 22.

The comparators 20u, 20v, 20w are
Phase current deviation Δi_u, Δi _v, Δi_wZero
Compared with bell, if it is greater than zero, logical value "1"
Output.

On the other hand, the comparators 20uw, 20vu,
20 wu are subtractors 21 uw, 21 vu, 21
As a result of taking the difference of the phase currents in wv Δi _u −Δi _w , Δi _v
-Derutaai _u, compared to zero Δi _w -Δi _v, is greater than zero, and outputs a logical value "1".

As a result, the comparators 20uw, 20
vu and 20wu are Δi _u > Δi _w and Δi _v >, respectively.
Δi _u, at the time of the Δi _w> Δi _v, and outputs a logic value "1".

The relationship between the output of this comparator and the angle of the current deviation vector is shown in FIG.

When the three-phase component of the current deviation vector has the uppermost waveform, the angle θΔi is determined by the comparator 20u,
It can be obtained from the combination of outputs from 20v, 20w, 20uw, 20vu, 20wu based on the relationship of FIG.

The logic circuit 22 of FIG. 2 performs the calculation, and QN = Q0 to Q11 based on the following equation.
12 bit signal is output.

N of QN is a value of 0 to 11 described above the angular range in FIG.

UGO in the following equation is an output signal from the comparator 20u which becomes "1" when Δi _u > 0, and VGO
Similarly, GO and WGO are output signals from the comparators 20v and 20w, and UGW is an output signal from the comparator 20uw which becomes “1” when Δi _u > Δi _w .
Similarly, WGV is an output signal from the comparators 20vu and 20wv.

Q0 = UG0 ^* / VG0 ^* / WG0 ^* / U
GW ^* / VGU ^* / WGV Q1 = UG0 ^* VG0 ^* / WG0 ^* UGW ^* / VGU ^*
/ WGV Q2 = UG0 ^* VG0 ^* / WG0 ^* UGW ^* VGU ^* /
WGV Q3 = / UG0 ^* VG0 ^* / WG0 ^* UGW ^* VGU ^*
/ WGV Q4 = / UG0 ^* VG0 ^* / WG0 ^* / UGW ^* VGU
^* / WGV Q5 = / UG0 ^* VG0 ^* / WG0 ^* / UGW ^* VGU
^* / WGV Q6 = / UG0 ^* VG0 ^* WG0 ^* / UGW ^* VGU ^*
WGV Q7 = / UG0 ^* / VG0 ^* WG0 ^* / UGW ^* VGU
^* WGV Q8 = / UG0 ^* / VG0 ^* WG0 ^* / UGW ^* / VG
U ^* WGV Q9 = UG0 ^* / VG0 ^* WG0 ^* / UGW ^* / VGU
^* WGV Q10 = UG0 ^* / VG0 ^* WG0 ^* UGW ^* / VGU
^* WGV Q11 = UG0 ^* / VG0 ^* WG0 ^* UGW ^* / VGU
^* WGV The logic circuit 22 also outputs the LE signal of the following formula.

LE = Q0 + Q1 + Q2 + Q3 + Q4 + Q
5 + Q6 + Q7 + Q8 + Q9 + Q10 + Q11 From the above formula, when the electrical angle θΔi is 0 to π / 6, Q
Only 0 becomes "1".

The same is true for others, and only one of the twelve output signals outputs the logical value "1".

Since six signals are input to the logic circuit 22, the number of states by the combination is 64.

On the other hand, only 12 states are effective as the electrical angle detection.

The LE signal outputs "1" only when the output signal from the logic circuit 22 is valid data, and the logic circuit 22 is illegal due to a current detection error, noise on the current detection signal, or the like. It is used to discard the data when it outputs such data.

The encoder 23 outputs the 12-bit signal Q0.
~ 4-bit electrical angle signal θΔ from Q11 according to electrical angle
i = 0 to 11 is output.

The latch circuit 24 latches the output from the encoder 23 with a clock pulse.

The AND circuit 25 takes the AND of the LE signal output from the logic circuit 22 and the clock supplied from the clock pulse generator (not shown), and the AND circuit 25
Give clock to 4.

If the method of FIG. 2 is implemented as software as the vector angle detector 8, detection can be performed at high speed, and the burden on the microcomputer can be reduced.

If hardware is used, detection can be performed at a higher speed, so that control sampling can be speeded up and the resolution of pulse width control can be increased.

A configuration example of the increase / decrease detection circuit 9 is shown in FIG.

In FIG. 4, the multipliers 30u, 30v, 3
The square of the length of the current deviation vector is obtained by calculating the square of each phase component Δi _u , Δi _v , Δi _w of the current deviation at 0w and adding the three phases by the adder 31.

The latch circuit 32 latches the output from the adder 31 and supplies it to the comparator 33.

Since the output from the adder 31 is given to the other input to the comparator 33, the comparator 33 compares the square of the length of the current deviation vector with the previous value, and the increase / decrease detection signal INC. Is output.

The increase / decrease detection signal INC is a logical value signal of "1" if the vector length is increased.

[0361]

[Table 4]

The deviation vector angle θ _Δi and the vector length increase signal Inc are input to the switching sequence circuit 10a.

The switching sequence circuit 10a is similar to the above-described conventional example in that the voltage vector is selected on the basis of the current deviation vector angle θ _Δi .
Use of the vector length increase signal Inc for determining the transition timing to the selected voltage vector (corresponding to the first invention)
Are very different.

In order to make it difficult for the reverse pulse to appear,
The vector selection table is also revised (corresponding to the second invention).

It should be noted that the switching sequence circuit 10a
The detailed operation of the above will be described after the explanation of the entire components.

The current deviation vector is also input to the sequence starting circuit 11a.

A detailed configuration example of the sequence starting circuit 11a is shown in FIG.

In FIG. 5, the allowable error comparator 40
The configuration of is the same as that of the conventional example described above.

The modulation frequency control circuit 52a comprises a timer counter 53a, a cycle set value 55, and an RS flip-flop 63.

The timer counter 53a operates by a clock pulse supplied from a clock generator (not shown), repeatedly counts from zero to the cycle setting value 55, and outputs a pulse when the cycle setting value is reached.

With the output "1" from the allowable error comparator 40, the timer counter 53a is cleared and starts counting from zero.

The RS flip-flop 63 is set by the output pulse from the timer counter 53a and reset by the switching operation signal fed back from the switching sequence circuit 10a.

The output signal ER from the permissible error comparator 40 and the output TR from the modulation frequency control circuit 52a are logically ORed by the OR circuit 59 and given to the switching sequence circuit 10a as a start command.

FIG. 6 shows a detailed configuration example of the switching sequence circuit 10a.

In FIG. 6, 61, 62, 65 to 67,
Since 70 and 71 are the same constituent elements as the above-mentioned conventional example, the description thereof is omitted here.

Reference numeral 60a is a vector selection table, but the contents of the table are different from those of the conventional example described above.

FIG. 7 shows an example of the selection logic from the zero vector corresponding to FIG. 24 of the above-mentioned conventional example.

In FIG. 7A, the previous sequence is v4 → v.
It is used when the sequence has ended at 0, and FIG. 7B is used when the previous sequence ends at v4 → v7.

A total of three vectors, which are the non-zero vector output before the transition to the zero vector and the two non-zero vectors adjacent to both sides of the non-zero vector, are selection candidates.

(1) In the previous sequence, when the second non-zero vector was changed to the zero vector, that is, when the zero vector was changed by one-phase switching, the current deviation vector and the original non-zero vector were changed. If the angle difference with the vector is within ± 60 degrees, the original non-zero vector is selected, and at other times, the angle difference with the current deviation vector of the two non-zero vectors adjacent to the original non-zero vector is selected. Select a few nonzero vectors.

FIG. 7A shows this relationship.

(2) In the previous sequence, when the first non-zero vector was transited to the zero vector, that is, when the two vectors were simultaneously switched to the zero vector, the original non-zero vector Of the two non-zero vectors adjacent to, a non-zero vector having a small angle difference from the current deviation vector is selected.

FIG. 7B shows this relationship.

Of the above, (1) v0 → v5, v0 →
In the v6 vector transfer, two-phase simultaneous switching is performed.

The above (2) is a logic for providing a constraint that, when two-phase simultaneous switching is performed in a certain switching sequence, the two-phase simultaneous switching is not permitted in the immediately following switching sequence.

According to the above-described concept of the second invention, simply,
It has been explained that when shifting from a zero vector to a non-zero vector, it is selected from the non-zero vector used before shifting to the zero vector in the previous sequence and the non-zero vectors on both sides thereof.

However, with this alone, simultaneous switching of two phases is likely to occur frequently, which may cause a new problem not found in the conventional example described above.

Therefore, as described above, it is divided into the case where the return to the original non-zero vector is permitted and the case where it is prohibited.

Details of these will be described in the section of operation.

The transition from the non-zero vector is the same as in the conventional example described above.

Table 4 collectively shows the above.

The vector selection table 60a is S
_{k (n), S k (} n-1), is addressed in Shitaderutaai, it outputs a value of the corresponding S _k (n + 1).

The vector angle detector 8 of the present embodiment is 0
Since a region signal of θΔi is output at ˜11, Table 4 also shows 12 columns for each angular range of the current deviation, correspondingly.

In the circuit 68a, the AND circuit, which has two inputs in the above-mentioned conventional 68, has three inputs, and the current increase / decrease detection signal INC is added as an input signal.

69a is the zero vector detector 6 of the conventional example.
9 is an alternative to the switching signal S being output.
_k (n) is a logic circuit for detecting whether or not _k (n) is the first non-zero vector.

FIG. 8 shows a detailed configuration example of the first non-zero vector detection logic circuit.

In FIG. 8, 80-83, 85-89,
Reference numeral 91 is an AND circuit, and 84, 90, 92 are OR circuits.

AND circuits 80 to 83, 85 to 89, 91
The circle at the input terminal of indicates that it is low level active.

The AND circuit 80 uses S _k (n-1) = S7.
"1" is output only when.

The AND circuits 81, 82 and 83 output "1" when S _k (n) is S6, S5 and S3, respectively.

The AND circuit 81, 8 in the OR circuit 84.
An AND circuit 85 ANDs the outputs from the OR circuit 84 and the AND circuit 80.

As a result, in the AND circuit 85, the switching sequence circuit 10a is currently in the nonzero vector S.
"1" is output only when any one of S6, S5 and S3 is output and the zero vector S7 is output before that.
Is output.

That is, the non-zero vectors S6 and S that can be transferred from the zero vector S7 by switching only one phase.
Logical value "1" only when either of S5 and S3
Is output.

Similarly, the AND circuit 91 outputs the logical value "1" only when the zero vector S0 shifts to any of the non-zero vectors S4, S2, S1 which can shift by switching only one phase.

The outputs from the AND circuits 85 and 91 are logically ORed by the OR circuit 92 to obtain the output signal from the logic circuit 69a.

In the PWM control circuit of the present invention, there are a set value of the period of the modulation frequency control circuit and a set value of the allowable error as changeable settings for coping with various uses. It is assumed that it is set by a host control circuit (not shown).

Next, the operation of the control device for the voltage source inverter according to the present embodiment configured as described above will be described.

(Operation of the Embodiment Corresponding to the First Invention) At time t0 when the current is at the origin of the current reference coordinates in FIG. 9, as described in the concept of the first invention.
And the switching sequence circuit is the zero vector S
The operation of the switching sequence will be described while following the current locus from the output of _k (n) = S7.

It is also assumed that the relationship between voltage vectors is as shown in FIG.

From time t0 to t1, the current is the same as in FIG. 30, and the current changes according to (v7-e) =-e.

The deviation vector angle is 5π /
3 <θΔi <11π / 6.

Assuming that S _k (n-1) = S5, the vector selection table 60a is S based on Table 4.
_It outputs _k (n + 1) = S5.

Since S _k (n + 1) is not a zero vector, the output from the zero vector detector 70 is 0, S _k (n
Since -1) is not a zero vector, the output from the logic circuit 69a is also zero.

Therefore, the remaining input signal of the OR circuit 67,
If the output from the AND circuit 65 does not become "1", the latch circuits 61 and 62 do not operate.

The output from the mismatch detection circuit 66, which is one input to the AND circuit 65, is S _k (n) = S7, S _k.
Since (n + 1) = S5 is “1”, the activation command, which is the other input, may be “1”.

At time t1, the sequence starting circuit 11a
When the allowable error comparator side outputs the start command, the latch circuits 61 and 62 operate via the OR circuit 64, the AND circuit 65, the OR circuit 67, and the AND circuit 71, and S _k
(N) = S5, S _k (n−1) = S7, and the switching sequence is started.

The switching sequence circuit 10a outputs S5 as the first non-zero vector.

At this time t1, since the deviation vector angle cannot change suddenly, it is in the range of π / 3 <θΔi <11π / 6, and the vector selection table 60a shows that S _k from Table 4
(N + 1) = S5 is output.

Since S _k (n + 1) = S _k (n),
The output from the non-coincidence detection circuit 66 becomes "0", and the AND circuit 65 cannot accept the activation command from the outside.

On the other hand, S _k (n-1) = S7, S _k (n)
= S5, the logic circuit 69a outputs the logic value "1" as the identification signal of the first non-zero vector.

The current changes according to the locus between time t1 and time t2 in FIG. 9 by the voltage (v5-e) determined by the first non-zero vector.

On the way, the deviation vector angle exceeds 11 beyond the dotted line.
When entering the region of π / 6 <θΔi <2π, the output from the vector selection table 60a changes from S5 to S4, and the mismatch detection circuit 66 outputs "1".

At this point, two of the three inputs of the AND circuit 68a are already "1", but the remaining one input is zero because the current deviation is still short due to the increase / decrease detection signal INC. Is.

At time t2, the current deviation starts to increase and IN
When C becomes "1", the AND circuit 68a outputs "1" and the latch circuits 61 and 62 operate.

At this time, the deviation vector angle is 0 <θΔi
Since S _k (n + 1) output from the vector selection table 60a from Table 4 is S4 in the region of <π / 6,
_k (n) = S4 and _Sk (n-1) = S5.

The switching sequence circuit outputs the second non-zero vector S4.

The deviation vector angle is in the range of 0 <θΔi <π / 6. Therefore, from Table 4, it is invariable at S _k (n + 1) = S4.

The current varies depending on the voltage (V4-e) determined by the non-zero vector S4 from time t2 to time t in FIG.
It changes according to the locus between 3.

At time t2, S _k (n + 1) = S _k
Since it is (n), the output from the mismatch detection circuit 66 is “0” and S _k (n−1) = S5.
Since the output from 9a is also “0” and S _k (n + 1) = S4, the output from the zero vector detection circuit 70 is also “0”.

When the output from the logic circuit 69a becomes "0", unless a sequence start command is given from the outside,
The switching sequence circuit 10a continues to output the second non-zero vector until the zero vector detection circuit 70 outputs "1".

Due to the current change by (V4-e), the angle of the current deviation vector is 11 from the region of 0 <θΔi <π / 6.
Region of π / 6 <θΔi <2π, 5π / 3 <θΔi <11
The region moves to the region of π / 6, and the region of 3π / 2 <θΔi <5π / 3.

In the middle of this, the vector selection table 60a
Output changes from S4 to S5.

As a result, the output from the mismatch detection circuit 66 becomes "1", but the current deviation is within the permissible error circle and the start command is not given. Therefore, the latch circuit 6
1, 62 never operate.

At time t3, the deviation vector angle is 3π / 2.
Becomes smaller than, the vector selection table 60a becomes
From Table 4, S0 is output.

Accordingly, the zero vector detector 70
Outputs "1" and outputs it through the OR circuit 67 and the AND circuit 71.
Then, the latch circuits 61 and 62 operate and S_k(N) = S
0, S _k(N-1) = S4.

The vector selection table 60a outputs S5 from Table 4.

Since S _k (n + 1) = S5, the output from the zero vector detector 70 is "0", S _k (n-1).
= S4, the output from the logic circuit 69a is also zero.

Only the mismatch detection circuit 66 outputs "1".

The switching sequence circuit 10a outputs the zero vector S0 and ends the sequence.

Thereafter, the switching sequence is started at time t4 when the magnitude of the current deviation reaches the permissible error circle.

At time t4, the angle of the current deviation vector is in the region of 5π / 3 <θΔi <11π / 6, and from Table 4, the vector selection table 60a outputs S4. It starts by outputting S4 as a non-zero vector of 1.

S4 is also switched to the second non-zero vector S5 after being output until time t5 when the current deviation vector becomes the shortest.

At time t6, the zero vector is entered,
The switching for one cycle of the triangular wave is completed.

As described above, FIG. 9 obtained by this embodiment.
The current locus of is compared with that of the conventional FIG.

Since all of them are controls with a constant tolerance, the magnitude of the current ripple should be the same.

However, in FIG. 9, the current returns to the vicinity of the origin at every switching corresponding to a half cycle of the triangular wave.

Since the current deviation can be effectively reduced by the non-zero voltage vector between time t1 and time t3, the current deviation at time t3 is smaller than that in FIG.

As a result, the current locus from t3 to t4 outputting the zero vector S0 is longer in FIG.

Since the lengths from the first time t0 to t1 are the same, it means that the period during which the zero vector is output becomes longer in the period in which the switching corresponding to one cycle of the triangular wave is performed.

That is, the switching cycle is long when the current ripples are controlled to the same magnitude.

Therefore, if the switching frequency is the same, the current ripple is smaller in FIG.

Further, since it returns to near the origin at the end of each switching sequence, it is expected that a similar trajectory will be drawn in the next cycle after time t6, and the uniformity of the current ripple can be improved. .

(Modification 1) The timing of the shortest point of the current deviation vector can also be detected from the angle formed by the current deviation vector and the current deviation vector in the current reference coordinates.

From FIG. 9, the angle formed by the direction of change of the current and the deviation vector is 90 degrees at the shortest point, smaller than 90 degrees when the current approaches the reference, and larger than 90 degrees when the current starts to move away.

The direction of current change in the current reference coordinates is
Current value of reverse direction vector of current deviation −Δin = − (in
^* -In) to the previous value -Δin-1 =-(in-1 ^*
Vector obtained by subtracting −in−1), Δin−1−
The angle of Δin should be calculated.

In the present embodiment, the angle of the current deviation vector is obtained as a region signal for each 30 electrical degrees, but in this modification, it is necessary to be able to detect the electrical angle more finely.

Therefore, both the current change direction and the angle of the current deviation vector are calculated from the sign of the vector component and the expression (2) according to the angle detection method of the conventional example described above.

In this modification, the calculation for obtaining the current change direction is not required, but the calculation for obtaining the length of the current deviation vector is not required.

The obtained timing is the same as that of this embodiment.

(Modification 2) The same transition timing can be detected from the angle change amount of the current deviation vector.

In FIG. 9, the current is moving on a straight line at a constant speed from time t1 to time t2.

The angle change of the current deviation vector at that time is
The shorter the current deviation vector, the larger the current deviation vector.

Therefore, the difference Δθ from the previous value of the angle θΔi of the current deviation vector detected for each control sampling is also obtained and stored, and when Δθ becomes smaller than the previous value, the transition timing may be set.

Also in this modification, the same timing as that of the present embodiment can be obtained without any calculation relating to the length of the current deviation vector.

Instead, it is necessary to calculate the amount of change in angle of the current deviation vector. However, as in the conventional example described above,
When the deviation vector angle is detected with high resolution based on the equation (2), the transition timing can be detected only by storing the detection result and comparing it with the detection result at the next control timing. it can.

(Modification 3) In the present embodiment, the timing is determined from the increase / decrease of the vector length only when the first non-zero vector is changed to the second non-zero vector. The timing may be determined by increasing or decreasing the length of the vector even when the transition is made from the non-zero vector to the zero vector.

For this purpose, an AND circuit is added between the zero vector detector 70 and the OR circuit 67 in FIG. 6, and the zero vector detector 7 is operated by the increase / decrease detection signal INC.
The output signal from 0 may be gated.

The method of the embodiment in which the second vector is shifted to the zero vector by the angle difference between the non-zero vector and the deviation vector tends to shift to the zero vector slightly earlier than the shortest point of the current deviation. In general, this modification is
The current deviation can be further reduced.

(Operation of the Embodiment Corresponding to the Second Invention) In the case of FIG. 30, when the switching sequence is performed from the beginning, it becomes FIG. Since the pulse does not appear, the current will change to the position at time t3 in FIG. 30 and shift to the zero vector for some reason, and the subsequent operation will be described with reference to FIG.

In the locus of FIG. 10, the position with time t0 corresponds to the position with time t3 in FIG.

At time t0 in FIG. 10, when the second non-zero vector S4 shifts to the zero vector S0, the current changes at v0-e = -e and reaches the boundary of the tolerance circle at time t1.

In Table 4, S _k (n) = S0, S _k (n-
Looking at the line 1) = S4, the vector selection table 60a
Is an original non-zero vector S4 or a non-zero vector S adjacent to the original non-zero vector S4 depending on the electrical angle.
5 and S6 are output.

The angle of the current deviation vector at time t1 is
Since it is in the region of 3π / 2 <θΔi <5π / 3, from Table 4, the vector selection table 60a outputs S5 as S _k (n + 1).

Therefore, immediately at time t1, S _k (n) =
The process moves to S5.

Although S _k (n-1) becomes S0, the output from the vector selection table 60a is S _k (n +
1) = S5 remains.

Therefore, the output from the mismatch detection circuit 66 is "0", and the output from the zero vector detector 70 is "0".

Since S _k (n-1) = S0,
The AND circuit 86 in FIG. 8 outputs "1", but S
_{Since k} (n) = 5, the AND circuits 87 to 89 all output "0".

Therefore, the output from the logic circuit 69a is also zero.

That is, S _k (n) = S5 in the output is
It outputs a signal that is not the first non-zero vector.

As a result, the inputs to the OR circuit 67 are all zero.

The current changes to the position at time t2 in FIG. 10 at v5-e.

On the way, crossing the vector selection boundary indicated by the dotted line in FIG. 10, from the region of 3π / 2 <θΔi <5π / 3 to the region of 5π / 3 <θΔi <11π / 6, 11π / 6
The region moves to the region of <θΔi <2π and the region of 0 <θΔi <π / 6.

When moving from the region of 5π / 3 <θΔi <11π / 6 to the region of 11π / 6 <θΔi <2π, the output from the vector selection table 60a changes to S4.

As a result, the mismatch detection circuit 66 is set to "1".
However, since the current deviation is within the tolerance circle and the sequence start command is not given, the latch circuit 61,
62 does not operate and the current continues to change.

At time t2, when moving to the region of π / 6 <θΔi <π / 3, the vector selection table 60a outputs S7 and the zero vector detector 70 outputs "1".

As a result, the latch circuits 61 and 62 operate and S _k (n) = S7 and S _k (n−1) = S5.

The current changes at V7-e = -e and reaches the boundary of the permissible error circle at time t3.

Thereafter, the switching sequence operates and the current changes to the position at time t8 in FIG. 10 as already described in the operation part of the embodiment corresponding to the first invention.

If the switching sequence ends at a point where the current deviation has a relatively large error, such as at time t0 in FIG. 10, for some reason, in the above-described conventional example, it is unnecessary to give priority to vector transfer with a small number of switching times. Since the limitation was added, the unnecessary reverse pulse was output. However, according to the operation corresponding to the second aspect of the present invention, the current deviation is output without outputting the reverse pulse by the two-phase simultaneous switching. It can be returned to near the origin (reference) of the coordinates, and in the next switching sequence, normal operation can be restored.

In FIG. 10, among the first non-zero vector selection methods described in the section of the concept of the second invention,
Only the method shown in FIG. 7A is used.

Now, the necessity of the selection method of FIG. 7B will be described with reference to FIGS. 11 and 12.

FIG. 11 is a voltage relational diagram when the induced voltage vector e of the load and the voltage vector v4 of the inverter are close to each other in angle.

As shown in FIG. 11, when the induced voltage has an angle close to one of the non-zero voltage vectors that can be output by the inverter, the two-phase pulse of the three-phase output of the inverter has almost the same width. Become.

When the first non-zero vector causes the current to go almost straight toward the current reference and pass by a small distance, the deviation vector is suddenly short because the length of the deviation vector is very short. Rotate.

If the angle difference between the output voltage vector and the deviation vector is ± within one cycle of the control sampling.
When it suddenly changes from within 30 degrees to ± 90 degrees or more, it directly shifts to the zero vector without passing through the second non-zero vector.

The phenomenon in such a case will be described by following the current locus (current locus in current reference coordinates) shown in FIG. 12 using the voltage relationship shown in FIG.

First, when shifting from a zero vector to a non-zero vector, “a current deviation vector is simply selected from the non-zero vector output before shifting to the zero vector in the previous sequence and the non-zero vectors on both sides thereof. Select the vector that has the closest angle to.

At time t0 in FIG. 12, the zero vector S0 is output, the current deviation increases up to time t1 due to the voltage V0-e, and at time t1, S _k (n) = S0 changes to the non-zero vector S4. And

After that, the current changes at v4-e, but at the time t2, the angle θΔi of the current deviation vector becomes smaller than 3π / 2 at the time t2 due to the relation with the sampling time, and the angle difference from the non-zero vector v4 becomes. It shall be 90 degrees or more.

From the angle of the deviation vector, the second non-zero vector is not moved, but the zero vector is directly transferred.

Since S _k (n-1) = S0, the process changes to S7 at time t2.

Here, two-phase simultaneous switching is performed.

After that, the current changes by v7-e,
The permissible error circle is reached at time t3.

Here, the angle θΔi of the current deviation vector
Is 11π / 6 <θΔi <2π, so v4 is selected according to the logic that the non-zero vector is determined only from the angle of the current deviation.

Here again, two-phase simultaneous switching is performed.

Since the non-zero vector that has been subjected to the two-phase simultaneous switching is treated as the second non-zero vector, the current is v4 until time t4 when the angle θΔi of the current deviation vector becomes smaller than 3π / 2. Change with -e.

S _k (n-1) = S7, S _k (n) = S4
Therefore, S _k (n) changes to S0 at time t4.

Here, only one phase of switching is performed.

The current changes at v0-e until time t5, and shifts to the non-zero vector again. At this time as well, the original non-zero vector S4 is selected only from the angle of the current deviation vector.

After that, the current changes at v4-e.

At time t6, if it can be detected that the shortest point of the current deviation has been exceeded, it changes to the second non-zero vector v5 as shown in FIG. 12, and changes to time t7 at v5-e. Afterwards, it shifts to the zero vector.

However, due to the sampling, it cannot be changed to v5 at time t6,
When the angle θΔi of the current deviation vector becomes smaller than 3π / 2, the two-phase simultaneous switching is performed again, and the current deviation further increases as compared with FIG.

In FIG. 12, the switching sequence using only v4 as the non-zero vector is repeated many times, and the end times t2, t4,
The current deviation at t6 is gradually increasing.

Moreover, the two-phase simultaneous switching is repeatedly performed and the switching frequency is increased.

In order to avoid the above problems, in the operation of the embodiment corresponding to the second invention, (1) the second non-zero vector is shifted to the zero vector in the previous sequence. If the angular difference between the current deviation vector and the original non-zero vector is within ± 60 degrees, the original non-zero vector is selected. Sometimes, of the two non-zero vectors adjacent to the original non-zero vector, the non-zero vector with the smaller angle difference from the current deviation vector is selected (2) In the previous sequence, the first non-zero vector to the zero vector is selected. When the transition was made to, that is, when transitioning to the zero vector by simultaneous switching of two phases, the current of the two non-zero vectors adjacent to the original non-zero vector And to choose a non-zero vector small angular difference between the difference vector.

In the switching from the non-zero vector in the operation of the embodiment corresponding to the second aspect of the present invention, originally, it is intended to sequentially switch the phases one by one and make the vector transition, and the simultaneous switching of the two phases is performed. Is performed only if the angular deviation of the current deviation between control samplings is too large.

In the above (2), originally, the first non-zero vector of the next switching sequence should be selected based on the previous second non-zero vector, but unintended two-phase simultaneous switching occurs. If that is not possible, then one of the two vectors adjacent to the previous first non-zero vector is selected.

This is because either of these two vectors is the vector that should originally be output as the second non-zero vector, and which one of them is determined by the angle of the current deviation vector.

That is, at time t2 in FIG. 12, since the transition is made from the first non-zero vector S4 to the zero vector S7, it corresponds to (2) above.

Therefore, at time t3, not S4 but S5.
Was selected and changed to the position at time t'4,
Since the current deviation starts to increase, it changes to the second non-zero vector S4, and the current changes by v4-e until time t'5.

The current deviation at the time t'5 is already smaller than the current deviation at the times t4 and t6, and the number of times of switching is only two.

By dividing the selection at the time of transition from the zero vector to the non-zero vector as in the above cases (1) and (2), the current deviation can be effectively reduced with a small number of switching times.

The two-phase simultaneous switching from the first non-zero vector to the zero vector is performed when the tolerance circle is set to be very small or when the constant modulation frequency is controlled at a low operating frequency of the load motor. For example, while a pulse width control of a very narrow width is required, this often occurs when the control circuit does not have a control resolution of only that.

Even in such a case, according to the operation of the embodiment corresponding to the second aspect of the present invention, an abnormal pulse such as between time t3 and time t6 in FIG. 12 is generated and the switching frequency becomes high. In addition, it is possible to avoid the disadvantage that the current deviation cannot be controlled small.

Therefore, by the operation of the embodiment corresponding to the second aspect of the present invention, the PWM that does not issue the reverse pulse to the smaller tolerance circle with the same control sampling or does not issue the reverse pulse to the lower rotation speed of the electric motor. It becomes possible to control.

(Operation of the Embodiment Corresponding to the Third Invention) Regarding the operation of the embodiment corresponding to the third invention,
This will be described with reference to the circuit configuration diagrams of FIGS. 5 and 6, the vector locus of FIG. 13 and the corresponding time waveform of FIG.

In FIG. 14, the current reference i _u ^* , the current i _u , the count value of the timer counter 53a, the output TR from the modulation frequency control circuit, and the output E from the tolerance comparator.
R, reset input RES of flip-flop 63, switching signals swu, swv, sww, line voltage waveform V
The waveform of uv is shown.

RES is a signal which becomes "1" every time the output S _k (n) from the switching sequence changes.

In the high rotation / low pulse number region, as shown in FIG. 13, the length of the current deviation vector is always larger than the radius of the permissible error circle.

For this reason, since the comparator 50 in FIG. 5 always outputs "1", as long as the OR circuit 46 for judging the band-shaped area outputs "1", the start command on the allowable error comparator side is issued. ER is output.

The timer counter 53a repeatedly counts from zero to the cycle set value 55, and outputs a pulse of "1" every time the cycle set value is reached.

The output (start command with constant modulation frequency) TR from the flip-flop 63 set by the output from the timer counter 53a is ORed with the start command ER on the allowable error comparator side in the OR circuit 59, It is output to the switching sequence circuit 10a as a start command.

The timer counter 53a includes an AND circuit 4
The output from 7 clears to zero.

In FIG. 14, at time t1, the PWM signals are swu = 0, swv = 0, sww = 1 (S _k (n)
= S1), the U-phase current has reached the current reference.

At this time, from FIG. 13, since the angle θΔi of the deviation vector becomes larger than 3π / 2, the output from the vector selection table 60a changes from S1 to S5.

S _k (n) = S1, S _k (n + 1) = S5
Therefore, the mismatch detection circuit 66 outputs "1".

As shown in FIG. 14, at time t1, the start command TR from the timer side has already become "1". Therefore, when the mismatch detection circuit 66 outputs "1", the OR circuit 67a and the AND circuit Via the latch circuit 61,
62 operates, S _k (n) = S5, S _k (n-1) = S
It becomes 1.

As a result, the flip-flop 63 is reset and TR becomes zero.

At this time, the timer 53a is not cleared.

From Table 4, the values of S _k (n) are S1 to S5.
Since the output S _k (n + 1) from the vector selection table 60a remains S5 at the time of changing to, the output from the mismatch detection circuit 66 temporarily changes to “0”.

However, since the current changing direction changes, the angle of the deviation vector immediately becomes smaller than 3π / 2.

S _k (n + 1) becomes S1, and the output from the mismatch detection circuit 66 returns to "1".

At time t2, when the current i _u reaches the allowable error width and becomes (i _u > i _u ^* + H / 2), the output from the OR circuit 46 on the allowable error comparator side becomes “1”, and The start command ER is output from the error comparator side.

Thus, S _k (n) = S1, S _k (n
-1) = S5.

At this time, the flip-flop 63 is reset and the timer counter 53a is cleared at the same time.

Until time t5, the current deviation reaches the permissible error width and the start command ER is output before the timer counter 53a counts up to the set period, and S1 and S5 are alternately output, each time. Timer counter 5
3a has been cleared.

However, the current change in the period of swu = 1 is gradually gradual, and the timer counter 53a counts up to the set period before the current deviation reaches the boundary of the allowable error at time t6. finish.

As a result, the start command T from the timer is issued.
R is output.

At time t7, the current deviation returns to the boundary on the opposite side of the allowable error area, and S _k (n) = S5, S _k (n + 1)
= S5.

After time t7, the direction of current change changes after a while.

[0551] Even if the U-phase current comes out of the band-shaped region,
Since the sign of the current deviation is opposite to the previous one, the start command E
R is not output.

In this case, the timer counter 53a is not cleared for a long period of time.
3a will certainly continue counting to the cycle set value.

At time t8, the start command TR is output from the timer side, but S _k (n) = S5, S _k (n +
1) = S5, since the output from the mismatch detection circuit 66 is zero, the latch circuits 61 and 62 do not operate.

At time t9 when the angle of the deviation vector becomes larger than 11π / 6, the latch circuits 61 and 62 operate similarly to time t1, and S _k (n) = S4, S _k (n-
1) = S5.

Thereafter, PWM is similarly performed.

As described above, by the operation of the embodiment corresponding to the third aspect of the present invention, from time t2 to time t5,
Similar to the conventional example described above, switching is performed based on the tolerance, but at time t6, switching is performed by the timer.

At time t6, the current deviation has not reached the boundary of the allowable error.

Therefore, the time t6 to the time t7 until the current returns to the boundary on the opposite side of the allowable error region is also shortened, and the pulse width is narrower than that due to the allowable error.

Looking at the line voltage waveform, time t6 to time t
The 7th pulse is a pulse located at the innermost position and disappears when the number of pulses decreases.

By moving the pulse forward, the influence of the line voltage of the pulse on the fundamental wave component is reduced, and by narrowing the pulse width, the voltage change amount when the pulse disappears is reduced. There is.

This simulation waveform is shown in FIG.

In addition to the signals shown in FIG. 14, FIG. 15 also shows the waveform of the current deviation vector angle θΔi.

The output from the modulation control circuit (output from the flip-flop 63) TR has a long period of "1" because it takes a long time to wait for a change in the output from the vector selection table 60a.

In this system, the timer is not cleared at the first timing of a series of switching for every 60 electrical degrees, such as at time t1.

Therefore, immediately after the output TR from the modulation control circuit is reset and returns to zero, the timer counter 53a reaches the set period and the output T from the modulation control circuit is reached.
R may become "1" again.

For this reason, the first pulse for every 60 electrical degrees is not necessarily the width determined by H / 2, and a very narrow pulse can be output.

This narrow pulse is generated when the timer is not cleared at the first timing of every 60 electrical degrees.

Since the leading end of the narrow pulse is the angle of the deviation vector and the trailing end is the timer, the timing is fixed regardless of the allowable error, which is useful for reducing the hysteresis of the pulse number.

In this system, even when the timer counter 53a reaches the set period and outputs the output TR from the modulation control circuit, the non-zero vector shifts (switching).
Is not unconditional.

It is confirmed that the output from the vector selection table 60a has changed depending on the angle of the current deviation vector, that is, the most effective vector for reducing the current deviation has changed. Wait, then the transition will take place.

Therefore, the current waveform is extremely stable even when the pulse width is changed by the timer in such a high rotation and low pulse number region.

In the above-described conventional example, since the minimum width of the pulse is determined by the setting H of the allowable error, the fine adjustment of the current cannot be performed like the operation of the embodiment corresponding to the third aspect of the invention. .

Since the limit of positioning the pulse at the end of the voltage waveform is also determined by the setting of the allowable error, the change of the fundamental wave component of the voltage depending on the number of pulses can be carried out in accordance with the third invention. Is greater than the effect of the form of

By the operation of the embodiment corresponding to the third invention, while avoiding an abnormal increase in the number of switching times,
It becomes possible to output a pulse having a very narrow width.

At the same time, by concentrating the switching at the ends of the voltage waveform, it is effective in reducing low-order harmonics,
It is possible to obtain a PWM waveform with a slight influence on the fundamental wave component, and it is possible to reduce the voltage change when the number of pulses changes.

(Modification) FIG. 16 shows a modification of the sequence starting circuit.

That is, the fall detection circuit 80 is added to the circuit of FIG.

In the circuit of FIG. 5, immediately after the output TR from the modulation control circuit returns to zero, the timer counter 53a reaches the set period and then the output TR from the modulation control circuit again.
16 may be set to "1", but in the circuit shown in FIG.
The falling edge detection circuit outputs a pulse to clear the timer counter 53a.

Immediately after the output TRTR from the modulation control circuit becomes zero, the output TRTR does not become "1" again, and the time of the set cycle is secured.

In actual operation, the width of the first pulse for every 60 electrical degrees is often equal to H / 2.

The simulation waveform is shown in FIG.

From FIG. 15, almost identical repetitive waveforms having uniform pulse widths can be obtained.

The circuit shown in FIG. 16 can output a pulse having a narrower width than that of the conventional example described above, and the circuit shown in FIG.
A more stable PWM waveform can be obtained than the circuit of No. 5.

(Modification) As described in the section of the concept of the third invention, timers may be provided for the modulation frequency control and for the high rotation / small pulse time.

In this case, a switch for switching between the output from another timer counter having different cycle setting values and the output from two timer counters may be provided.

The switching signal to this switching unit is given from the host control circuit.

Normally, a timer counter for controlling the modulation frequency is used, and the timer counter is switched to a dedicated timer counter only at high revolutions and few pulses.

As for the clear signal of the timer counter, ER may be used as in the case of the modulation frequency control.

As described above, the voltage source inverter control device according to the embodiments corresponding to the first to third inventions can obtain the following effects.

(Effect of Embodiment Corresponding to First Invention) FIGS. 18 to 20 show simulation results according to the embodiment corresponding to the first invention.

FIG. 18 shows a control with a constant allowable error under the same conditions as the simulation result of the conventional example described above (FIG. 28).

In the above-mentioned conventional example shown in FIG. 28, the pulse arrangement is non-uniform and the pulse width changes in a non-uniform manner, whereas in FIG. 18 of the embodiment corresponding to the first aspect of the present invention. , The pulses are evenly arranged, and the pulse width can be continuously changed according to the phase.

Further, the widths of the paired pulses in the line voltage waveform are more uniform in FIG.

As a result, the number of pulses of the switching signal per one cycle of the current reference was a little less than 70 in FIG. 28, whereas in FIG. Become.

Further, since the pulse widths are uniform, it is possible to perform control with a constant modulation frequency up to a higher operating frequency than before.

In the conventional example described above, the positions of the current deviations in the vector space at the time of the zero vector transition are different between the first and second switching sequences, whereas the first The effect that the current deviation occupies almost the same position in the vector space and then shifts to the zero vector in each switching sequence by the embodiment corresponding to the invention of FIG.

The switching sequence circuit of the embodiment corresponding to the first aspect of the present invention selects the switching signal to be transferred next based on the angle of the deviation vector, and the deviation vector determines the minimum value due to the switching signal being output. When it has passed, the output is switched to the previously selected switching signal.

The angle of the current deviation vector and the minimum value of the vector length are both relative amounts of the current deviation and not the magnitude of the current deviation itself.

It is only that a non-zero vector is selected and switched based on these two quantities to change the current in the direction in which the current deviation is always reduced.

Therefore, the mode of the PWM control operation will be arbitrary depending on the way of giving the start command from the outside.

If it is desired to keep the current deviation within the allowable error range,
The start command may be given when the current deviation becomes larger than the allowable error, or the start command may be given in a fixed cycle when the switching frequency is set to a predetermined frequency.

Before the switching sequence is completed, that is, when the start command is given during the non-zero vector output, from the angle of the current deviation vector at that time, PWM between adjacent non-zero vectors, Since it moves to the next non-zero vector one after another, (a) In the transient state where the current deviation does not fall within the allowable error due to the sudden change of the current reference or the load, the current deviation vector is output while the start command by the allowable error is output. Since the necessary non-zero vector is continuously output based on the angle of, the current can be made to quickly follow the reference.

(B) When the induced voltage of the load is high and the current deviation does not fall within the permissible error, such as when the motor is rotating at high speed, switching between adjacent non-zero vectors may be used to perform PWM or small pulse PWM. It becomes possible to realize a one-pulse square wave.

In the combination of dp-axis current control and triangular wave comparison PWM, only sinusoidal current control can be performed, whereas according to the embodiment corresponding to the first aspect of the invention, 12
The current control of 0 degree square wave is also possible from the above (a).

(Effect of the Embodiment Corresponding to the Second Invention) In the vicinity of zero volt where the sign of the fundamental wave of the line voltage changes, a very narrow pulse is applied to the line voltage in order to output a low voltage. Must output.

At this time, the difference in the required pulse width depending on the phase is very small, and the control is difficult.

Therefore, in FIG. 28, many reverse pulses appear in the line voltage waveform.

On the other hand, in FIG. 18, the reverse pulse does not appear even near the line voltage of zero volt.

This is because the switching signals of the two phases have exactly the same widths and no longer appear as pulses in the line voltage. Therefore, according to the embodiment corresponding to the second aspect of the present invention, the zero vector becomes the second non-zero value. This is the effect of moving directly to the vector.

FIG. 19 shows a frequency in which a start command with a constant tolerance and a start command with a constant modulation frequency coexist, and FIG. It is a simulation result.

The embodiment corresponding to the second aspect of the present invention prevents the reverse pulse from being generated even at such a low frequency.

(Effects of the Embodiment Corresponding to the Third Invention) At the time of high revolution and small number of pulses, the above-mentioned conventional example (FIG. 3).
(2, FIG. 33), a pulse with a width narrower than the width determined by the allowable error cannot be output, so that the change of the fundamental wave component of the voltage with the number of pulses is large.

Also, due to the same reason, the number of pulses has hysteresis.

Therefore, although the load conditions are the same and the current reference is the same, the current waveform differs depending on the number of pulses.

On the other hand, in the embodiment corresponding to the third aspect of the present invention, as described with reference to FIGS. 13 to 17, the pulse inside the voltage waveform which will disappear when the number of pulses decreases. Only with respect to the above, the width can be selectively narrowed and the position thereof can be shifted forward so that the voltage change at the time of switching the pulse number can be reduced without significantly increasing the switching number.

Therefore, the difference between the current waveforms when the number of pulses is switched is small, and the hysteresis of the number of pulses is also small.

Since it is based on the current instantaneous value comparison, the current waveform is extremely stable even with such a small number of pulses.

It is understood from FIGS. 18 to 20 that the control with the constant tolerance and the control with the constant modulation frequency are automatically switched.

In particular, in FIG. 19, although the two control modes are switched at random, there is no abrupt change in the pulse width and the current is controlled uniformly.

The sequence activation circuit of the embodiment (FIG. 5) corresponding to the first aspect of the present invention automatically switches from the constant modulation frequency to the control with the constant error, and even in the control with the constant error, Waveforms such as 7 pulses, 5 pulses, 3 pulses, etc. at the time of high rotation small pulse from PWM waveform of
Further, it is possible to perform a PWM control in which the number of pulses is changed automatically with a square wave and the voltage change is small when the number of pulses changes.

(Other Embodiments) It should be noted that the present invention is not limited to the above-mentioned respective embodiments, and can be variously modified and carried out within a range not departing from the gist of the invention at an implementation stage. Is. In each of the above-described embodiments, the current control of the electric motor has been described as an example, but the present invention is not limited to the inverter for controlling the electric motor.

In other words, the PWM control can be applied to all voltage source inverters that perform instantaneous current value control because it does not require detection of induced voltage.

Further, the respective embodiments may be combined as appropriate as much as possible, and in that case, the combined effects can be obtained. Further, the above-described embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent features. For example, even if some constituent features are deleted from all the constituent features shown in the embodiment, the problem (at least one) described in the section of the problem to be solved by the invention can be solved, and If the effect (at least one of the effects) described in the section is obtained, the configuration in which this constituent element is deleted can be extracted as the invention.

[0624]

As described above, according to the control device of the voltage type inverter of the present invention, the magnitude of the current ripple can be made more uniform and smaller.

Further, according to the control device for a voltage source inverter of the present invention, it is possible to reduce the reverse pulse as compared with the conventional one.

Further, according to the control device of the voltage source inverter of the present invention, it is possible to reduce the voltage change at the time of switching the pulse number at the time of high rotation / small number of pulses, compared with the conventional case.

As described above, the following various ripple effects can be obtained.

(A) The pulse mode can be changed automatically and continuously to cover the entire operating frequency range of the inverter.

(B) The current response can be speeded up.

In the steady state, even when the control with the constant modulation frequency is performed, if the current deviation becomes large, the control shifts to the control with the constant allowable error, and the current can be made to follow at high speed.

Therefore, in the GTO inverter or the like, since the switching element is slow, high-speed current control can be performed even when the switching element is used at a modulation frequency of several hundred Hz.

(C) Resistant to DC voltage fluctuations and load constant changes.

It is suitable for a control device using a battery with large voltage fluctuations as a power source, such as an electric vehicle.

(D) PI control, dead time compensation, induced voltage compensation, and other compensation control that requires adjustment can be eliminated.

Therefore, the device can be realized at a low cost because of no adjustment.

(E) It becomes possible to perform non-sinusoidal wave current control.

A high torque output is possible by the square wave current control.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a current controller for an induction motor to which a controller for a voltage source inverter according to the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of a vector angle detector 8 in the same embodiment.

FIG. 3 is a diagram showing a relationship between a comparator output and an angle of a current deviation vector in the same embodiment.

FIG. 4 is a block diagram showing a configuration example of an increase / decrease detection circuit 9 in the same embodiment.

FIG. 5 is a sequence starting circuit 1 in the same embodiment.
The block diagram which shows the detailed structural example of 1a.

FIG. 6 is a block diagram showing a detailed configuration example of a switching sequence circuit 10a in the same embodiment.

FIG. 7 is a diagram showing an example of selection logic from zero vectors in the same embodiment.

FIG. 8 is a block diagram showing a detailed configuration example of a first non-zero vector detection logic circuit in the same embodiment.

FIG. 9 is a view for explaining the operation of the embodiment corresponding to the first invention.

FIG. 10 is a view for explaining the operation of the embodiment corresponding to the second invention.

11 is a diagram showing the relationship of voltage vectors for drawing a current locus at the current reference coordinates in FIG.

FIG. 12 is a supplementary explanatory diagram showing the necessity of a non-zero vector selecting method according to the embodiment corresponding to the second invention.

FIG. 13 is a current trajectory diagram in current reference coordinates for explaining the operation of the embodiment corresponding to the third invention.

14 is a diagram showing a time waveform corresponding to FIG.

FIG. 15 is a diagram showing a simulation result for explaining the operation and effect of the embodiment corresponding to the third invention.

FIG. 16 is a configuration diagram showing a modified example of a sequence starting circuit.

FIG. 17 is a diagram showing simulation results for explaining the operation and effect of the modification of the embodiment corresponding to the third invention.

FIG. 18 is a diagram showing simulation results for explaining effects of the embodiments corresponding to the first and second inventions.

FIG. 19 is a diagram showing simulation results for explaining the effects of the embodiments corresponding to the first and second inventions.

FIG. 20 is a diagram showing simulation results for explaining the effects of the embodiments corresponding to the first and second inventions.

FIG. 21 is a block diagram showing a configuration example of a current control device for an induction motor by a conventional PWM control device.

FIG. 22 is an explanatory diagram of a voltage vector that can be output by the inverter.

FIG. 23 is a block diagram showing a detailed configuration example of a conventional switching sequence circuit 10.

FIG. 24 is a diagram for explaining an example of a conventional voltage vector selection method from a zero vector.

FIG. 25 is a diagram for explaining an example of a conventional voltage vector selection method from non-zero vectors.

FIG. 26 is a block diagram showing a detailed configuration example of a conventional sequence activation circuit 11.

FIG. 27 is a diagram for explaining an allowable error region of the allowable error comparator 40.

FIG. 28 is a diagram showing a simulation waveform according to a conventional example for explaining the first and second problems.

29 is a diagram showing the relationship between voltage vectors used to explain the operation of FIG. 30.

FIG. 30 is a diagram showing a current locus (current reference coordinates) according to a conventional example for explaining the first problem.

FIG. 31 is a pulse waveform chart for explaining the reverse pulse of the second problem.

FIG. 32 is a diagram showing a current locus (current reference coordinates) according to a conventional example for explaining the third problem.

33 is a diagram showing a time waveform corresponding to FIG. 32.

FIG. 34 is a diagram showing a current locus (current reference coordinates) for explaining the concept of the first invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... DC power supply, 2 ... Smoothing capacitor, 3 ... Inverter, 4 ... Induction motor, 5U, 5V, 5W ... Hall CT, 6 ... Current detector, 7 ... Vector subtractor, 8 ... Vector angle detector, 9 ... Vector Length increase / decrease detection circuit, 10 ... Switching sequence circuit, 10a ... Switching sequence circuit, 11 ... Sequence activation circuit, 11a ... Sequence activation circuit, 12 ... Logic circuit, 13 ... Gate circuit, 20u, 20v, 20w, 20uw, 20vu, 20w
v ... Comparator, 21uw, 21vu, 21wv ... Subtractor, 22 ... Logic circuit, 23 ... Encoder, 24 ... Latch circuit, 25 ... AND circuit, 40 ... Allowable error comparator, 41u, 41v, 41w, 41x, 41y, 41w ... Comparator, 42 ... Allowable error setting value, 43 ... Magnifier, 44u, 44v, 44w, 44x, 44y, 44w ... AND circuit, 45u, 45v, 45w ... NOT circuit, 46 ... OR circuit, 47 ... AND circuit, 48u, 48v, 48w ... Multiplier, 49 ... Adder, 50 ... Comparator, 51 ... Multiplier, 52 ... Modulation frequency control circuit, 53 ... Counter, 54 ... Comparator, 55 ... Cycle set value, 56 ... AND circuit, 57 ... Zero Vector detector, 58 ... Fall detection circuit, 59 ... OR circuit, 60 ... Vector selection circuit Bull, 61 ... Latch circuit, 62 ... Latch circuit, 65 ... AND circuit, 66 ... Mismatch detector, 67 ... OR circuit, 68 ... AND circuit, 69 ... Zero vector detector, 70 ... Zero vector detector, 71 ... AND circuit.

Claims (10)

[Claims] 1. A control device for a voltage source inverter comprising a plurality of self-extinguishing type switching elements, wherein a voltage vector is determined based on an angle of a deviation vector between a reference vector of an inverter output current and a detection vector. A voltage vector selecting means for selecting, and a timing control means for controlling the output timing of the switching signal corresponding to the voltage vector selected by the voltage vector selecting means, based on the angle of the deviation vector and the increase or decrease of the vector length. A control device for a voltage source inverter, comprising: controlling the self-extinguishing element based on the switching signal. 2. A voltage-source inverter control device comprising a plurality of self-turn-off switching elements, wherein an angle detecting means for detecting an angle of a deviation vector between a reference vector of the inverter output current and a detection vector. And an increase / decrease detecting means for detecting an increase / decrease in the vector length, and a non-zero vector of A switching sequence generator that outputs a switching signal, controls switching, and outputs a zero-vector switching signal when a predetermined termination condition is satisfied to terminate a series of sequences, and a start command to the switching sequence generator. A sequence starting means for outputting, Depending on the starting way of giving a command from the control device of the voltage source inverter, characterized in that so as to control the operation mode of the PWM control. 3. A voltage source inverter control device comprising a plurality of self-extinguishing type switching elements, wherein an angle detecting means for detecting an angle of a vector of a deviation between a reference vector of an inverter output current and a detection vector. And an increase / decrease detecting means for detecting an increase / decrease in the vector length, and a non-zero vector of A switching sequence generating means for outputting and switching control a switching signal, and outputting a zero-vector switching signal when a predetermined termination condition is satisfied to terminate a series of sequences, and a combination of a current deviation state and the switching signal. , Or based on a predetermined cycle, the switching sequence generation means And a sequence starting means for outputting a start command to control the self-extinguishing type switching element based on the switching signal. 4. The voltage source inverter control device according to claim 2 or 3, wherein the switching sequence generating means includes a history holding unit that holds an output history of the switching signal, and a zero vector of the zero vector. When outputting the switching signal, one of the six non-zero vectors is selected based on the output history of the switching signal and the angle of the deviation vector, and the switching signal of the non-zero vector is selected. When outputting, if the non-zero vector with the smallest angular difference from the deviation vector is the non-zero vector being output or the non-zero vector adjacent to it,
If the non-zero vector with the smallest angle difference is selected and the deviation vector and the non-zero vector with the smallest angle difference are none of the above, one of the two zero vectors is set by the history holding unit. A vector selection unit that selects from the held output history, an output signal from the vector selection unit, an output history held by the history holding unit, an external start command, and an increase / decrease detection result of the vector length. A voltage operation inverter control device comprising: a logic operation unit that controls whether or not the switching signal is changed to a signal corresponding to a vector output by the vector selection unit at that time. 5. The voltage source inverter control device according to claim 2 or 3, wherein the switching sequence generation means includes a history holding unit that holds an output history of the switching signal, and the history holding unit. Based on the history signal output by the and the angle of the deviation vector, a vector selection unit that selects a voltage vector, and if the output from the vector selection unit is a zero vector, immediately or increase the current deviation vector. At the time when the increase / decrease detection signal indicates, and when the output from the vector selection unit is not a zero vector, the previous value held by the output history holding unit is a zero vector, and the vector of the switching signal being output. The vector output from the vector selection unit is different from that of the current deviation vector. At the time indicated by, or when the vector of the switching signal being output and the vector output by the vector selection unit are different and a start command is given from the outside, the vector output by the vector selection unit at the time A voltage source inverter control device comprising: a logical operation unit that outputs a switching signal corresponding to the following. 6. The control device for a voltage source inverter according to claim 2, wherein the switching sequence generating means is such that the output of the switching sequence generating means is a zero vector, and the output history holding section holds the previous value. When only one-phase switching is required for the transition to the zero vector, two-phase switching is performed from among the three vectors, the non-zero vector of the previous value and two non-zero vectors adjacent to the previous value. The control device for the voltage source inverter, which has a vector selection unit that selects a vector from the two adjacent non-zero vectors based on the angle of the deviation vector when necessary. 7. The control device for a voltage source inverter according to claim 4 or 5, wherein the switching sequence generating means immediately or immediately when the vector selecting section outputs a zero vector. At the time when the increase / decrease detection signal indicates an increase in the deviation vector, the previous value held by the output history holding unit is a zero vector, and only one-phase switching is performed when the zero vector shifts to the switching signal being output. If not required, the vector output by the vector selection unit does not match the vector due to the switching signal being output and at the time when the increase / decrease detection signal indicates the increase of the deviation vector, and in other cases. The vector output by the vector selection unit is a vector based on the switching signal being output. And a vector output by the vector selection unit does not match and a start command is given from the outside, a logical operation unit that outputs a switching signal corresponding to the output from the vector selection unit at that time is provided. A control device for a voltage-source inverter, which has: 8. The control device for a voltage source inverter according to claim 2 or 3, wherein the switching sequence generation means is the vector selection unit according to claim 4.
And a logic operation unit according to claim 1. 9. The control device for a voltage source inverter according to claim 2 or 3, wherein the sequence starting means includes a predetermined amount of current deviation of each phase ± H / 2 and a sign of the switching signal. Comparison of whether or not the current deviation is included in the area obtained by the logical sum of the first permissible error area based on the above and the second permissible error area based on the predetermined amount H of the length of the current deviation vector. Based on the result, a permissible error comparison and determination unit that outputs a first start command, and outputs a signal every time a predetermined time elapses after measuring time.
A timer initialized by a first start command from the allowable error comparison / determination unit and a second start signal set by an output signal from the timer are held, and the switching sequence generation means changes the switching signal. And a flip-flop that is reset each time the switching sequence is generated. The startup command is given to the switching sequence generation means by a logical sum of the first startup command and the second startup command. Voltage source inverter control device. 10. The control device for a voltage source inverter according to claim 2 or 3, wherein the sequence starting means includes a predetermined amount of current deviation of each phase ± H / 2 and a sign of a switching signal. A result of comparison of whether or not the current deviation is included in the area obtained by the logical sum of the first allowable error area based on the predetermined amount H of the current deviation vector and the second allowable error area based on the predetermined amount H of the current deviation vector. Based on, the allowable error comparison and determination unit that outputs a first start command, and outputs a signal every time a predetermined time elapses after measuring time.
A timer initialized by the falling timing detection signal of the first start command and the second start command from the allowable error comparison and determination unit; and the second start signal set by the output signal from the timer. And a falling detection unit that detects a falling timing of the second start command, the flip-flop being reset every time the switching sequence generating means changes the switching signal, and the first start command. A control method and a control device for a voltage type inverter, wherein a start command is given to the switching sequence generating means by a logical sum of the above and a second start command.