JP2003234439A - Insulative resin composite - Google Patents
Insulative resin compositeInfo
- Publication number
- JP2003234439A JP2003234439A JP2002031307A JP2002031307A JP2003234439A JP 2003234439 A JP2003234439 A JP 2003234439A JP 2002031307 A JP2002031307 A JP 2002031307A JP 2002031307 A JP2002031307 A JP 2002031307A JP 2003234439 A JP2003234439 A JP 2003234439A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wiring board
- electronic component
- resin composition
- insulating resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Compositions Of Macromolecular Compounds (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Inorganic Insulating Materials (AREA)
- Organic Insulating Materials (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、電子部品を封止す
るに適した絶縁性樹脂組成物に関する。特に、表面に各
種電子部品を実装するための配線板の絶縁層の内部に半
導体チップ等の電子部品を内蔵させるために使用する絶
縁性樹脂組成物に関する。TECHNICAL FIELD The present invention relates to an insulating resin composition suitable for sealing electronic parts. In particular, the present invention relates to an insulating resin composition used for incorporating an electronic component such as a semiconductor chip inside an insulating layer of a wiring board for mounting various electronic components on the surface.
【0002】[0002]
【従来の技術】従来より、半導体チップなどの各種電子
部品を実装するための配線板の実装密度を向上させるた
めに、配線に関しては、配線板の表面方向の配線ルール
を微細化することや、厚み方向に配線を積層することが
行われている。また、半導体チップに関しては、ベアチ
ップをフリップチップ方式で配線板にダイレクトにリー
ドレスで接続することが行われている。2. Description of the Related Art Conventionally, in order to improve the mounting density of a wiring board for mounting various electronic components such as semiconductor chips, regarding wiring, the wiring rule in the surface direction of the wiring board is made finer, Wiring is stacked in the thickness direction. Regarding semiconductor chips, a bare chip is directly connected to a wiring board in a leadless manner by a flip chip method.
【0003】しかし、配線板の表面の実装スペースには
限りがあり、多数の半導体チップ等の電子部品を配線板
表面に高密度で実装することが困難になっている。However, the mounting space on the surface of the wiring board is limited, and it is difficult to mount a large number of electronic components such as semiconductor chips on the surface of the wiring board at high density.
【0004】そこで、最近では、配線板の表面に実装さ
れていた半導体チップ等の電子部品を配線板の絶縁層に
内蔵させることが試みられている(特開2001−77
536号公報)。このような電子部品内蔵配線板の一例
の概略断面図を図3に示す。この電子部品内蔵配線板
は、ガラスエポキシ基板31の下層銅配線32に接着剤
33で接続された電子部品34と、電子部品34を封止
するようにソルダーレジスト層35を被覆する絶縁層3
6と、その上にエポキシ系樹脂層37を介して形成され
た上層銅配線38と、下層銅配線32と上層銅配線38
とを接続するバイアホール39(バイアホール用孔40
の内壁に銅メッキ層41が形成されたもの)から構成さ
れている。Therefore, recently, it has been attempted to incorporate an electronic component such as a semiconductor chip mounted on the surface of the wiring board in the insulating layer of the wiring board (Japanese Patent Laid-Open No. 2001-77).
No. 536). A schematic sectional view of an example of such a wiring board with built-in electronic components is shown in FIG. This wiring board with a built-in electronic component includes an electronic component 34 connected to a lower copper wiring 32 of a glass epoxy substrate 31 with an adhesive 33, and an insulating layer 3 covering a solder resist layer 35 so as to seal the electronic component 34.
6, an upper layer copper wiring 38 formed thereon via an epoxy resin layer 37, a lower layer copper wiring 32, and an upper layer copper wiring 38.
Via hole 39 for connecting to (hole 40 for via hole
Inner wall of which the copper plating layer 41 is formed).
【0005】ところで、電子部品内蔵配線板を作製する
際に用いられている従来の封止用絶縁性樹脂組成物に
は、使用する絶縁性樹脂であるエポキシ樹脂の比較的大
きな硬化収縮や熱膨張率を緩和するためにシリカ微粒子
などの非導電性フィラが60〜90重量%配合されてい
る。By the way, in the conventional insulating resin composition for encapsulation used for producing a wiring board with a built-in electronic component, the epoxy resin which is the insulating resin used has a relatively large curing shrinkage and thermal expansion. A non-conductive filler such as silica fine particles is added in an amount of 60 to 90% by weight in order to reduce the rate.
【0006】[0006]
【発明が解決すべき問題点】しかしながら、図3の電子
部品内蔵配線板に使用されている従来の封止用絶縁性樹
脂組成物は、配線板上の半導体チップを単に封止するた
めのものであるため、バイアホール用孔の形成時のレー
ザ加工性(レーザ加工により意図した形状・大きさの孔
を形成できる性質)を考慮しておらず、また、バイアホ
ール用孔内面のメッキ性(無電解メッキ金属が析出可能
な性質)も考慮していない。このため、図4に示すよう
にレーザ加工時にバイアホール用孔40の内面にえぐれ
42が生じ、その結果、バイアホール用孔内面のメッキ
密着性が低下することが懸念される。However, the conventional insulating resin composition for sealing used in the wiring board with a built-in electronic component shown in FIG. 3 is for simply sealing the semiconductor chip on the wiring board. Therefore, the laser processability when forming the via hole hole (the property that a hole having the intended shape and size can be formed by laser processing) is not taken into consideration, and the plating property of the inner surface of the via hole hole ( The property that electroless plating metal can be deposited is not considered. For this reason, as shown in FIG. 4, a recess 42 is formed on the inner surface of the via hole hole 40 during laser processing, and as a result, there is a concern that the plating adhesion of the inner surface of the via hole hole may deteriorate.
【0007】本発明は、以上の従来の技術の問題を解決
しようとするものであり、電子部品内蔵配線板に使用可
能な封止用の絶縁性樹脂組成物に対し、良好なレーザ加
工性を付与することを目的とする。The present invention is intended to solve the above-mentioned problems of the prior art, and provides a good laser processability to an insulating resin composition for sealing which can be used for a wiring board with a built-in electronic component. The purpose is to give.
【0008】[0008]
【課題を解決するための手段】本発明者らは、従来の封
止用絶縁性樹脂組成物のレーザ加工性の問題が、添加さ
れている非導電性フィラの平均粒径と比較的大きな粒径
のフィラの含有割合とに大きく依存していることを知見
し、その知見に基づき本発明を完成させた。SUMMARY OF THE INVENTION The present inventors have found that the problem of the laser processability of conventional encapsulating insulating resin compositions is that the average particle size of the non-conductive filler added is relatively large. The present invention was completed based on the finding that it largely depends on the content ratio of the diameter of the filler.
【0009】即ち、本発明は、熱硬化性成分中に、非導
電性フィラが分散してなる絶縁性樹脂組成物において、
該非導電性フィラの平均粒径が0.3〜20μmであ
り、全非導電性フィラに占める粒径64μm以上の非導
電性フィラの割合が5.0重量%以下であることを特徴
とする絶縁性樹脂組成物を提供する。That is, the present invention provides an insulating resin composition comprising a non-conductive filler dispersed in a thermosetting component,
The non-conductive filler has an average particle size of 0.3 to 20 μm, and the ratio of the non-conductive filler having a particle size of 64 μm or more in all the non-conductive filler is 5.0% by weight or less. A resin composition is provided.
【0010】また、本発明は、第1基材の少なくとも片
面に第1配線が形成されている第1配線基板と、第1配
線基板上で該第1配線に接続されている電子部品と、該
電子部品を封止する絶縁層と、該絶縁層上に設けられて
いる、第2基材の少なくとも片面に第2配線が形成され
ている第2配線基板と、第1配線と第2配線とを接続し
ているバイアホールと、からなる電子部品内蔵配線板に
おいて、該絶縁層が、熱硬化性成分中に非導電性フィラ
が分散してなる絶縁性樹脂組成物から形成されたもので
あって、該非導電性フィラの平均粒径が0.3〜20μ
mであり、全非導電性フィラに占める粒径64μm以上
の非導電性フィラの割合が5.0重量%以下であること
を特徴とする電子部品内蔵配線板を提供する。Further, according to the present invention, there is provided a first wiring board having a first wiring formed on at least one surface of a first base material, and an electronic component connected to the first wiring on the first wiring board. An insulating layer for encapsulating the electronic component, a second wiring substrate provided on the insulating layer and having second wiring formed on at least one surface of a second base material, first wiring, and second wiring In a wiring board with a built-in electronic component, which comprises a via hole connecting to and, the insulating layer is formed from an insulating resin composition in which a non-conductive filler is dispersed in a thermosetting component. And the average particle size of the non-conductive filler is 0.3 to 20 μm.
The present invention provides a wiring board with a built-in electronic component, characterized in that the proportion of non-conductive fillers having a particle size of 64 μm or more in all non-conductive fillers is 5.0% by weight or less.
【0011】[0011]
【発明の実施の形態】本発明の絶縁性樹脂組成物は、熱
硬化性成分中に、非導電性フィラが分散したものであ
る。ここで、非導電性フィラとして、平均粒径が0.3
〜20μm、好ましくは3〜15μmのものであって、
全非導電性フィラに占める粒径64μm以上の非導電性
フィラの割合が5.0重量%以下、好ましくは3.5重
量%以下のものを使用する。平均粒径が0.3μmを下
回るものは入手が困難であり、また20μmを超えるも
のはレーザ加工面にえぐれを生じさせ、レーザ加工性が
低下し過ぎるので好ましくない。また、全非導電性フィ
ラに占める粒径64μm以上の非導電性フィラの割合が
5.0重量%を超えるものは、平均粒径が20μm以下
であってもレーザ加工性が低下し過ぎるので好ましくな
い。BEST MODE FOR CARRYING OUT THE INVENTION The insulating resin composition of the present invention has a non-conductive filler dispersed in a thermosetting component. Here, the non-conductive filler has an average particle size of 0.3.
˜20 μm, preferably 3 to 15 μm,
A non-conductive filler having a particle size of 64 μm or more in the total non-conductive filler is 5.0% by weight or less, preferably 3.5% by weight or less. Those having an average particle size of less than 0.3 μm are difficult to obtain, and those having an average particle size of more than 20 μm are not preferable because they cause the laser-machined surface to be engraved and the laser-machinability is deteriorated too much. Further, it is preferable that the ratio of the non-conductive filler having a particle size of 64 μm or more in all the non-conductive fillers exceeds 5.0% by weight because the laser processability is excessively lowered even if the average particle size is 20 μm or less. Absent.
【0012】なお、粒径64μm以上の非導電性フィラ
の割合は、レーザ散乱法粒径測定装置(例えば、CIL
AS MODEL 715、CILAS MODEL
920(いずれもCILAS社))で測定することがで
きる。The ratio of the non-conductive filler having a particle size of 64 μm or more is determined by a laser scattering particle size measuring device (for example, CIL).
AS MODEL 715, CILAS MODEL
920 (both are manufactured by CILAS).
【0013】このような非導電性フィラとしては、平均
粒径並びに全非導電性フィラに占める粒径64μm以上
の非導電性フィラの割合が上述した範囲を満たしている
公知の非導電性フィラを使用することができる。中でも
吸湿性、熱膨張率、絶縁性の点でシリカ微粒子を好まし
く使用することができる。As such a non-conductive filler, a known non-conductive filler in which the average particle size and the proportion of the non-conductive filler having a particle size of 64 μm or more in all the non-conductive fillers satisfy the above-mentioned ranges. Can be used. Among them, silica fine particles can be preferably used in terms of hygroscopicity, thermal expansion coefficient, and insulating property.
【0014】非導電性フィラの絶縁性樹脂組成物中の含
有量は、少なすぎると硬化収縮や熱膨張係数を有効に制
御することができず、多すぎると組成物の粘度が高くな
りすぎるので、好ましくは60〜90重量%、より好ま
しくは70〜85重量%である。If the content of the non-conductive filler in the insulating resin composition is too small, the curing shrinkage and the thermal expansion coefficient cannot be effectively controlled, and if it is too large, the viscosity of the composition becomes too high. %, Preferably 60 to 90% by weight, more preferably 70 to 85% by weight.
【0015】本発明で使用する熱硬化性成分としては、
従来の封止用の絶縁性樹脂組成物において用いられてい
る熱硬化性成分を使用することができる。中でも、経済
性と性能とのバランスの点から重合性エポキシ系化合物
と硬化剤と必要に応じて硬化助剤とを含有する熱硬化性
成分を好ましく使用できる。The thermosetting component used in the present invention includes
The thermosetting component used in the conventional insulating resin composition for sealing can be used. Above all, a thermosetting component containing a polymerizable epoxy compound, a curing agent and, if necessary, a curing aid can be preferably used from the viewpoint of a balance between economic efficiency and performance.
【0016】このような重合性エポキシ系化合物として
は、分子量(重量平均分子量)10000以下のエポキ
シ系モノマーもしくはオリゴマーを好ましく挙げること
ができる。例えば、ビスフェノールA、ビスフェノール
F、レゾルシノール、フェノールノボラック、クレゾー
ルノボラックなどのフェノール類のグリシジルエーテ
ル;ブタンジオール、ポリエチレングリコール、ポリプ
ロピレングリコールなどのアルコール類のグリシジルエ
ーテル;フタル酸、イソフタル酸、テトラヒドロフタル
酸などのカルボン酸のグリシジルエステル等のエポキシ
モノマーやこれらのオリゴマーもしくは脂環型エポキシ
ドを挙げることができる。中でも、ビスフェノールAグ
リシジルエーテルモノマーもしくはオリゴマーを好まし
く使用できる。具体的には、油化シェル社製造のエピコ
ート828(分子量380)、エピコート834(分子
量470)、エピコート1001(分子量900)、エ
ピコート1002(分子量1060)、エピコート10
55(分子量1350)、エピコート1007(分子量
2900)等を使用することができる。これらは、単独
で、あるいは2種以上を併用することもできる。As such a polymerizable epoxy compound, an epoxy monomer or oligomer having a molecular weight (weight average molecular weight) of 10,000 or less can be preferably mentioned. For example, glycidyl ethers of phenols such as bisphenol A, bisphenol F, resorcinol, phenol novolac, and cresol novolac; glycidyl ethers of alcohols such as butanediol, polyethylene glycol, polypropylene glycol; phthalic acid, isophthalic acid, tetrahydrophthalic acid, etc. Examples thereof include epoxy monomers such as glycidyl ester of carboxylic acid, oligomers thereof, and alicyclic epoxides. Among them, bisphenol A glycidyl ether monomer or oligomer can be preferably used. Specifically, Epicoat 828 (molecular weight 380), Epicoat 834 (molecular weight 470), Epicoat 1001 (molecular weight 900), Epicoat 1002 (molecular weight 1060), Epicoat 10 manufactured by Yuka Shell Co., Ltd.
55 (molecular weight 1350), Epicoat 1007 (molecular weight 2900) and the like can be used. These may be used alone or in combination of two or more.
【0017】硬化剤としては、公知のものを使用するこ
とができ、例えば、酸無水物系硬化剤(例えば、無水フ
タル酸、無水マレイン酸等)、アミン系硬化剤(例え
ば、エチレンジアミン、メンセンジアミン、ジアミノジ
フェニルメタン等)、ポリアミド系硬化剤、フェノール
系硬化剤(例えば、フェノールノボラック等)、ポリメ
ルカプタン系硬化剤等を使用することができる。As the curing agent, known ones can be used, for example, acid anhydride type curing agents (eg phthalic anhydride, maleic anhydride etc.), amine type curing agents (eg ethylenediamine, menthene). Diamine, diaminodiphenylmethane, etc.), polyamide-based curing agents, phenol-based curing agents (eg, phenol novolac, etc.), polymercaptan-based curing agents, etc. can be used.
【0018】硬化剤の使用量は、重合性エポキシ系化合
物のエポキシ当量より計算した化学理論量に対し50〜
150%である。The amount of the curing agent used is 50 to 50 relative to the stoichiometric amount calculated from the epoxy equivalent of the polymerizable epoxy compound.
It is 150%.
【0019】また、硬化助剤(促進剤)としては、アミ
ン系硬化助剤(例えば、トリエチレンジアミン、ベンジ
ルジメチルアミン等)、イミダゾール系硬化助剤(例え
ば、2−メチルイミダゾール、2−フェニルイミダゾー
ル等)、ホスフィン系硬化助剤(例えば、トリフェニル
ホスフィン、トリブチルホスフィン等)、ホスホニウム
塩系硬化助剤、金属キレート系硬化助剤等を使用するこ
とができる。As the curing aid (accelerator), an amine-based curing aid (eg, triethylenediamine, benzyldimethylamine, etc.), an imidazole-based curing aid (eg, 2-methylimidazole, 2-phenylimidazole, etc.) ), Phosphine-based curing aids (eg, triphenylphosphine, tributylphosphine, etc.), phosphonium salt-based curing aids, metal chelate-based curing aids, and the like.
【0020】硬化助剤の使用量は、重合性エポキシ系化
合物100重量部に対し、好ましくは0.01〜10重
量部である。The amount of the curing aid used is preferably 0.01 to 10 parts by weight with respect to 100 parts by weight of the polymerizable epoxy compound.
【0021】本発明の絶縁性樹脂組成物には、上述した
成分に加えて、架橋剤、各種ゴム成分、カップリング
剤、レベリング剤、粘度調整剤、酸化防止剤等を必要に
応じて適宜配合することができる。但し、本発明の絶縁
性樹脂組成物には、可塑剤として広く用いられているシ
リコーンオイルを使用しないことが好ましい。シリコー
ンオイルを配合した場合には、バイアホール用孔内面に
メッキ金属が析出しないという問題や、析出したとして
も密着性が不十分であるという問題、更には絶縁性樹脂
組成物から形成される絶縁層とそれに隣接する層との間
の密着性が不十分になるという問題も生ずるので好まし
くない。In the insulating resin composition of the present invention, in addition to the above-mentioned components, a cross-linking agent, various rubber components, a coupling agent, a leveling agent, a viscosity modifier, an antioxidant, etc. are appropriately blended. can do. However, it is preferable not to use silicone oil widely used as a plasticizer in the insulating resin composition of the present invention. When silicone oil is blended, the problem that the plating metal does not deposit on the inner surface of the via hole hole, the problem that the adhesion is insufficient even if it deposits, and the insulation formed from the insulating resin composition This is not preferable because it causes a problem of insufficient adhesion between the layer and the layer adjacent thereto.
【0022】本発明の絶縁性樹脂組成物は、熱硬化性成
分、非導電性フィラ及び必要に応じて添加される各種添
加剤とを、常法により均一に混合することにより調製す
ることができる。この絶縁性樹脂組成物は、使用する原
料の種類や量比により異なるが、液状もしくはペースト
状の形態として用いられる。The insulative resin composition of the present invention can be prepared by uniformly mixing the thermosetting component, the non-conductive filler, and various additives which are added as necessary, by a conventional method. . This insulating resin composition is used in the form of a liquid or a paste, although it varies depending on the type and amount ratio of the raw materials used.
【0023】本発明の絶縁性樹脂組成物は、従来の半導
体チップの封止用樹脂組成物と同様に使用することがで
きるが、良好なレーザ加工性を示すので、電子部品内蔵
配線板の電子部品の封止層且つ絶縁層として使用するこ
とができる。The insulating resin composition of the present invention can be used in the same manner as the conventional resin composition for sealing a semiconductor chip, but since it exhibits good laser processability, it can be used as an electronic component of a wiring board with a built-in electronic component. It can be used as a sealing layer and an insulating layer for components.
【0024】本発明の絶縁性樹脂組成物を使用して得ら
れる電子部品内蔵配線板の基本的な構造は、図1に示す
ように、第1基材1(ガラスエポキシ基材等)の少なく
とも片面に第1配線2(銅配線等)が形成されている第
1配線基板3(片面銅張ガラスエポキシ基板等)と、第
1配線基板3上で第1配線2に接続されている電子部品
4(半導体チップ、コンデンサ、抵抗等)と、電子部品
4を封止する絶縁層5と、絶縁層5上に設けられてい
る、第2基材6(エポキシ系樹脂層等)の少なくとも片
面に第2配線7(銅配線等)が形成されている第2配線
基板8(片面銅張フレキシブル基板等)と、第1配線2
と第2配線7とを接続しているバイアホール9とから構
成されている。ここで、絶縁層5が、好ましくは、シリ
コーンオイルを含有していない本発明の絶縁性樹脂組成
物から形成されたものである。また、第1配線基板3と
絶縁層5との間には、ソルダーレジスト層10が形成さ
れていてもよい。また、第1配線2と電子部品4とは、
異方性導電接着フィルム11を介して接続されていても
よい。The basic structure of a wiring board with a built-in electronic component obtained by using the insulating resin composition of the present invention is, as shown in FIG. 1, at least the first substrate 1 (glass epoxy substrate or the like). A first wiring board 3 (a single-sided copper-clad glass epoxy board or the like) having a first wiring 2 (copper wiring or the like) formed on one surface thereof, and an electronic component connected to the first wiring 2 on the first wiring board 3. 4 (semiconductor chip, capacitor, resistor, etc.), insulating layer 5 for sealing electronic component 4, and second substrate 6 (epoxy resin layer, etc.) provided on insulating layer 5 on at least one surface A second wiring board 8 (a single-sided copper-clad flexible board or the like) on which a second wiring 7 (copper wiring or the like) is formed, and a first wiring 2
And a via hole 9 connecting the second wiring 7 to the second wiring 7. Here, the insulating layer 5 is preferably formed from the insulating resin composition of the present invention containing no silicone oil. A solder resist layer 10 may be formed between the first wiring board 3 and the insulating layer 5. The first wiring 2 and the electronic component 4 are
It may be connected via the anisotropic conductive adhesive film 11.
【0025】図1の電子部品内蔵配線板は、図2に示す
ように製造することができる。The electronic component built-in wiring board of FIG. 1 can be manufactured as shown in FIG.
【0026】まず、第1基材1の片面に第1配線2が形
成されている第1配線基板3上に、スクリーン印刷によ
り、電子部品4を接続すべき第1配線2の領域を露出さ
せておくように、ソルダーレジスト層10を設ける(図
2(a))。First, the area of the first wiring 2 to which the electronic component 4 is to be connected is exposed by screen printing on the first wiring board 3 having the first wiring 2 formed on one surface of the first base material 1. As described above, the solder resist layer 10 is provided (FIG. 2A).
【0027】次に、第1配線2に電子部品4を、例えば
異方性導電接着フィルム11を介してフリップチップ接
続する(図2(b))。Next, the electronic component 4 is flip-chip connected to the first wiring 2 via, for example, the anisotropic conductive adhesive film 11 (FIG. 2B).
【0028】次に、封止用絶縁性樹脂組成物を、電子部
品4を封止するようにソルダーレジスト層10の全面に
塗布し、その封止用絶縁性樹脂組成物の塗布膜に、第2
配線基板8の片面に形成された銅箔等の配線用金属層
7’を、その第2基材6側から積層し、全体を加熱加圧
することにより塗布膜を硬化させて絶縁層5とすると共
に全体を一体化する(図2(c))。Next, the sealing insulating resin composition is applied to the entire surface of the solder resist layer 10 so as to seal the electronic component 4, and a coating film of the sealing insulating resin composition is applied to Two
A wiring metal layer 7 ′ such as a copper foil formed on one surface of the wiring board 8 is laminated from the side of the second base material 6 and the whole is heated and pressed to cure the coating film to form the insulating layer 5. Together with the whole (FIG. 2 (c)).
【0029】更に、配線用金属層7’にバイアホール用
窓をエッチングにより形成し、そこにレーザ光を第1配
線2が露出するまで照射することにより穿孔し、バイア
ホール用孔12を形成する(図2(d))。続いて必要
に応じてデスミア処理を行うことが好ましい。Further, a via hole window is formed in the wiring metal layer 7 ′ by etching, and a laser beam is irradiated therethrough until the first wiring 2 is exposed to make a hole, thereby forming a via hole hole 12. (FIG. 2 (d)). Then, it is preferable to perform desmear processing as needed.
【0030】次に、無電解メッキ、続いて電解メッキを
施すことによりバイアホール用孔12の内面に銅メッキ
などの接続用金属層13を形成することにより、第1配
線2と配線用金属層7’とを電気的に導通するバイアホ
ール9を形成し、常法に従って配線用金属層7’をパタ
ーニングすることにより第2配線7を形成し、電子部品
内蔵配線板を得る(図2(e))。Next, electroless plating is performed, and then electrolytic plating is performed to form a connection metal layer 13 such as copper plating on the inner surface of the via hole 12 to form the first wiring 2 and the wiring metal layer. 7'and the via hole 9 electrically connected to it is formed, and the second wiring 7 is formed by patterning the wiring metal layer 7'according to a conventional method to obtain the electronic component built-in wiring board (FIG. 2 (e )).
【0031】[0031]
【実施例】以下、本発明を実施例により、具体的に説明
する。EXAMPLES The present invention will be specifically described below with reference to examples.
【0032】実施例1〜6及び比較例1〜6
表1及び表2に示した配合表の各成分を、プラネタリー
ミキサー(井上製作所)で撹拌し、更に、三本ロールタ
イプの混練機(ノリタケカンパニーリミテッド)で混練
りすることにより表1及び表2に示す粘度(レオメータ
による剪断速度γ=100S-1の領域における粘度)の
絶縁性樹脂組成物を調製した。Examples 1 to 6 and Comparative Examples 1 to 6 Each component of the compounding table shown in Table 1 and Table 2 was stirred by a planetary mixer (Inoue Seisakusho), and further, a three-roll type kneader ( By kneading with Noritake Co., Ltd., an insulating resin composition having the viscosities shown in Tables 1 and 2 (viscosity in the region of shear rate γ = 100 S −1 by a rheometer) was prepared.
【0033】得られた絶縁性樹脂組成物を使用して、図
2に示す様に半導体チップ内蔵配線板を作製した。A wiring board with a built-in semiconductor chip was prepared as shown in FIG. 2 using the obtained insulating resin composition.
【0034】まず、ガラスエポキシ基材の片面に形成さ
れた厚さ400μmの下層銅配線上に20μm厚のソル
ダーレジスト層(CCR−510、アサヒ化研社)を設
けた後、半導体チップを接続すべき銅配線の領域のソル
ダーレジスト層を除去したものに対し、異方性導電接着
フィルム(FP4011K、ソニーケミカル社)を介し
て半導体チップ(サイズ:6.3mm四方、0.4mm
厚)をフリップチップ接続した。First, a solder resist layer (CCR-510, Asahi Kaken Co., Ltd.) having a thickness of 20 μm is provided on a lower copper wiring having a thickness of 400 μm formed on one surface of a glass epoxy substrate, and then a semiconductor chip is connected. The semiconductor chip (size: 6.3 mm square, 0.4 mm) with an anisotropic conductive adhesive film (FP4011K, Sony Chemical Co.) removed from the solder resist layer in the copper wiring region
Thickness) was flip-chip bonded.
【0035】次に、各実施例及び比較例の絶縁性樹脂組
成物を、半導体チップを封止するようにソルダーレジス
ト層の全面に180μm厚となるようにスキージで塗布
し、全体を加熱加圧(100℃で1時間、その後150
℃で1時間の加熱)することにより塗布膜を硬化させて
絶縁層とした。その絶縁層上に、片面に80μm厚のエ
ポキシ樹脂層が形成された12μm厚の銅箔(RCC
(resin coated copper);APL−4001 2X、
住友ベークライト社)を、そのエポキシ樹脂層側から積
層し、加熱加圧(180℃、392N/cm2)するこ
とにより硬化した。Next, the insulating resin compositions of Examples and Comparative Examples were applied to the entire surface of the solder resist layer with a squeegee so as to have a thickness of 180 μm so as to seal the semiconductor chip, and the whole was heated and pressed. (1 hour at 100 ° C, then 150
The coating film was cured by heating at 0 ° C. for 1 hour to form an insulating layer. A 12 μm thick copper foil (RCC) with an 80 μm thick epoxy resin layer formed on one surface on the insulating layer.
(Resin coated copper); APL-4001 2X,
Sumitomo Bakelite Co., Ltd.) was laminated from the epoxy resin layer side, and heated and pressed (180 ° C., 392 N / cm 2 ) to cure.
【0036】次に、RCC表面の銅箔にバイアホール用
窓をエッチングにより形成し、そこに炭酸ガスレーザ光
(LC−1C21/1C、日立ビアメカニクス社)を用
いて、ガラスエポキシ基材上の下層銅配線が露出するま
で照射することにより穿孔して直径300μmのバイア
ホール用孔を形成した。Next, a via hole window is formed by etching on the copper foil on the RCC surface, and a carbon dioxide gas laser beam (LC-1C21 / 1C, Hitachi Via Mechanics Co., Ltd.) is used to form a lower layer on the glass epoxy substrate. Irradiation was performed until the copper wiring was exposed to form a via hole having a diameter of 300 μm.
【0037】次に、RCC表面の銅箔上にメッキレジス
ト層を形成した後、常法に従って無電解銅メッキ(メッ
キ浴:PB−555、荏原ユージライト社)、更に電解
銅メッキ(メッキ浴:EX2、荏原ユージライト社)を
行い、バイアホール用孔の内壁に15μm厚の銅層を形
成し、下層銅配線と表面の銅箔とを接続した。Next, after forming a plating resist layer on the copper foil on the RCC surface, electroless copper plating (plating bath: PB-555, Ebara-Eugelite Co., Ltd.) and electrolytic copper plating (plating bath: plating bath: EX2, Ebara Eugelite Co., Ltd.) was performed to form a 15 μm thick copper layer on the inner wall of the via hole hole, and the lower copper wiring and the copper foil on the surface were connected.
【0038】最後に、常法に従って銅箔をパターニング
して上層銅配線を形成することにより半導体チップ内蔵
配線板を作製した。Finally, a copper foil was patterned according to a conventional method to form an upper layer copper wiring, whereby a wiring board with a built-in semiconductor chip was produced.
【0039】得られた半導体チップ内蔵配線板につい
て、以下に説明するように、レーザ加工性、絶縁層と硬
化したエポキシ樹脂層との密着性、反り、メッキ性につ
いて測定評価した。得られた結果を表1及び表2に示
す。The obtained wiring board with a built-in semiconductor chip was measured and evaluated for laser processability, adhesion between the insulating layer and the cured epoxy resin layer, warpage, and plating property, as described below. The obtained results are shown in Tables 1 and 2.
【0040】レーザ加工性
レーザ加工後により形成されたバイアホール用孔を縦方
向に切断し、切断面を光学顕微鏡にて観察した。えぐれ
が生じていない場合を良好と判定し、表中「○」と記載
した。えぐれが生じた場合を不良と判定し、表中「×」
と記載した。 Laser Machinability Holes for via holes formed by laser machining were vertically cut, and the cut surface was observed with an optical microscope. The case where no scooping occurred was judged to be good, and was marked as “◯” in the table. If a cut-out occurs, it is judged as a defect and "X" in the table
It was described.
【0041】密着性
絶縁層に対してRCCを90度の方向に、50mm/分
の速度で引き剥がした。その際の引き剥がしに要した力
(N/cm)を引っ張り試験機で測定した。 Adhesion RCC was peeled off from the insulating layer in the direction of 90 degrees at a speed of 50 mm / min. The force (N / cm) required for peeling at that time was measured by a tensile tester.
【0042】反り
120mm四方のガラスエポキシ基材内の75mm四方
の領域に絶縁層を形成した配線板を平らな定盤に置き、
その端部と定盤との距離を測定した。その距離(反り)
が1mm未満である場合を良好と判定し、表中「○」と
記載した。反りが2mm以上である場合を不良と判定
し、表中「×」と記載した。反りがそれらの中間、即ち
1mm以上2未満である場合を、表中「△」と記載し
た。A wiring board having an insulating layer formed in an area of 75 mm square in a glass epoxy base material of 120 mm square warp is placed on a flat surface plate,
The distance between the edge and the surface plate was measured. That distance (warpage)
Was less than 1 mm, it was determined to be good, and was described as “◯” in the table. When the warp was 2 mm or more, it was determined to be defective, and was described as “x” in the table. The case where the warp is between them, that is, 1 mm or more and less than 2 is described as “Δ” in the table.
【0043】メッキ性
電解メッキ後のバイアホールを縦方向に切断し、切断面
を光学顕微鏡にて観察した。メッキ層が形成されている
場合を良好と判定し、表中「○」と記載した。メッキ層
が形成されていない場合を不良と判定し、表中「×」と
記載した。The via holes after the plating of electroless plating was cut longitudinally, to observe the cut surface with an optical microscope. The case where the plating layer was formed was judged to be good, and was marked as “◯” in the table. The case where the plating layer was not formed was determined to be defective, and was marked as “x” in the table.
【0044】なお、以下の表1及び表2において使用し
た成分は以下の通りである。
*1:ビスフェノールA型エポキシ樹脂(EP828、
油化シェルジャパン社)
*2:メチルヘキサヒドロ無水フタル酸(B−650、
大日本インキ化学工業社)
*3:イミダゾール系硬化剤(2MZ−A、四国化成工
業社)
*4:シナジスト系分散剤(ソルスパース5000、ア
ビシア化学社)
*5:高分子系分散剤(ソルスパース24000、アビ
シア化学社)
*6:エポキシシラン(A−186、日本ユニカー社)
*7:ジメチルシリコーンオイル(KF−96、信越化
学工業社)
*8:球状シリカ(SO−C2、龍森社)、平均粒径=
0.5μm、粒径64μm以上のフィラ含有量=0%
*9:球状シリカ(EB−6D、電気化学工業社)、平
均粒径=4.2μm、粒径64μm以上のフィラ含有量
=0%
*10:球状シリカ(MSR−25、龍森社)、平均粒径
=27μm、粒径64μm以上のフィラ含有量=11.
5%(SO−EI、龍森社)
*11:球状シリカ(SO−EI、龍森社)、平均粒径=
0.3μm、粒径64μm以上のフィラ含有量=0%
*12:球状シリカ(FB−24R、電気化学工業社)、
平均粒径=17.2μm、粒径64μm以上のフィラ含
有量=5.5%The components used in Tables 1 and 2 below are as follows. * 1: Bisphenol A type epoxy resin (EP828,
Yuka Shell Japan Co., Ltd. * 2: Methylhexahydrophthalic anhydride (B-650,
Dainippon Ink and Chemicals, Inc. * 3: Imidazole-based curing agent (2MZ-A, Shikoku Kasei Co., Ltd.) * 4: Synergist-based dispersant (Solspers 5000, Abyssia Chemical) * 5: Polymeric dispersant (Solspers 24000) , Abisia Chemical Co., Ltd. * 6: Epoxy silane (A-186, Nippon Unicar Co., Ltd.) * 7: Dimethyl silicone oil (KF-96, Shin-Etsu Chemical Co., Ltd.) * 8: Spherical silica (SO-C2, Tatsumori Co., Ltd.), Average particle size =
Filler content of 0.5 μm and particle size of 64 μm or more = 0% * 9: Spherical silica (EB-6D, manufactured by Denki Kagaku Kogyo Co., Ltd.), average particle size = 4.2 μm, filler content of particle size of 64 μm or more = 0% * 10: Spherical silica (MSR-25, Tatsumori Co., Ltd.), average particle diameter = 27 μm, filler content with particle diameter of 64 μm or more = 11.1.
5% (SO-EI, Tatsumorisha) * 11: Spherical silica (SO-EI, Tatsumorisha), average particle size =
Filler content of 0.3 μm, particle size of 64 μm or more = 0% * 12: Spherical silica (FB-24R, Denki Kagaku Kogyo Co., Ltd.),
Average particle size = 17.2 μm, filler content of particle size 64 μm or more = 5.5%
【0045】[0045]
【表1】 (配合表) 実施例 成分 1 2 3 4 5 6 (重量部) エポキシ樹脂*1 10 10 10 15 10 10 硬化剤*2 10 10 10 15 10 10 硬化助剤*3 0.2 0.2 0.2 0.3 0.2 0.2 分散剤A*4 0.1 − − 0.08 0.1 0.1 分散剤B*5 − 0.4 − − − −シランカッフ゜リンク゛ 剤*6 − − 5 − − −シリコーンオイル *7 − − − − − −シリカフィラ A*8 20 20 20 15 − −シリカフィラ B*9 60 60 60 55 − 50シリカフィラ C*10 − − − − − 30シリカフィラ D*11 − − − − 80 −シリカフィラ E*12 − − − − − − 合計 100.3 100.6 105.2 100.38 100.3 100.3 フィラ 平均粒径(μm) 3.3 3.3 3.3 3.4 0.3 12.8 粒径64μm以上のフィラ(%) 0 0 0 0 0 3.48 粘度(mPa/S;γ=100s-1) 7万 6万 9万 3万 10万 4万 レーザ加工性 ○ ○ ○ ○ ○ ○ 密着性(N/cm) 15 15 15 15 15 15 反り ○ ○ ○ △ ○ ○ メッキ性 ○ ○ ○ ○ ○ ○ [Table 1] (Formulation list) Example components 1 2 3 4 5 6 (parts by weight) Epoxy resin * 1 10 10 10 15 10 10 Curing agent * 2 10 10 10 15 10 10 Curing aid * 3 0.2 0.2 0.2 0.3 0.2 0.2 Dispersant A * 4 0.1 − − 0.08 0.1 0.1 Dispersant B * 5 − 0.4 − − − − Silane coupling agent * 6 − − 5 − − − Silicone oil * 7 − − − − − − Silica filler A * 8 20 20 20 15 − − Silica filler B * 9 60 60 60 55 −50 Silica filler C * 10 − − − − − 30 Silica filler D * 11 − − − − 80 − Silica filler E * 12 − − − − − − Total 100.3 100.6 105.2 100.38 100.3 100.3 Filler average particle size (μm) 3.3 3.3 3.3 3.4 0.3 12.8 Filler with particle size of 64 μm or more (%) 0 0 0 0 0 3.48 Viscosity (mPa / S; γ = 100s -1 ) 70,69,000 30,000 100,000 Laser processability ○ ○ ○ ○ ○ ○ Adhesion (N / cm) 15 15 15 15 15 15 Warpage ○ ○ ○ △ ○ ○ Plating property ○ ○ ○ ○ ○ ○
【0046】[0046]
【表2】 (配合表) 比較例 成分 1 2 3 4 5 6 (重量部) エポキシ樹脂*1 10 10 10 23 10 10 硬化剤*2 10 10 10 22 10 10 硬化助剤*3 0.2 0.2 0.2 0.35 0.2 0.2 分散剤A*4 0.1 0.1 0.1 0.08 − − 分散剤B*5 − − − − − −シランカッフ゜リンク゛ 剤*6 − − − − − −シリコーンオイル *7 − − − − 0.1 −シリカフィラ A*8 − − − 10 20 20シリカフィラ B*9 20 − − 45 60 60シリカフィラ C*10 60 50 7 − − −シリカフィラ D*11 − 30 − − − − シリカフィラ E*12 − − 73 − − − 合計 100.3 100.3 100.3 100.43 100.3 100.2 フィラ 平均粒径(μm) 21.3 17.0 18.2 3.5 3.3 3.3 粒径64μm以上のフィラ(%) 6.9 5.8 5.1 0 0 0 粘度(mPa/S;γ=100s-1) 3万 4万 5万 1万 8万 16万 レーザ加工性 × × × ○ ○ ○ 反り ○ ○ ○ × ○ ○ メッキ性 ○ ○ ○ ○ × ○ [Table 2] (Combination table) Comparative example components 1 2 3 4 5 6 (parts by weight) Epoxy resin * 1 10 10 10 23 10 10 Curing agent * 2 10 10 10 22 10 10 Curing aid * 3 0.2 0.2 0.2 0.35 0.2 0.2 Dispersant A * 4 0.1 0.1 0.1 0.08 − − Dispersing agent B * 5 − − − − − − Silane coupling agent * 6 − − − − − − Silicone oil * 7 − − − − 0.1 − Silica filler A * 8 − − − 10 20 20 Silica filler B * 9 20 − − 45 60 60 Silica filler C * 10 60 50 7 − − − Silica filler D * 11 − 30 − − − − Silica filler E * 12 − − 73 − − − Total 100.3 100.3 100.3 100.43 100.3 100.2 Filler average particle size (μm) 21.3 17.0 18.2 3.5 3.3 3.3 Filler with particle size of 64 μm or more (%) 6.9 5.8 5.1 0 0 0 Viscosity (mPa / S; γ = 100s -1 ) 30 40,000 180,160,000 Laser processability × × × ○ ○ ○ Warp ○ ○ ○ × ○ ○ Plating property ○ ○ ○ ○ × ○
【0047】表1及び表2に示されているように、実施
例1〜6の絶縁性樹脂組成物は、レーザ加工性を含む全
ての評価項目について良好な結果が得られた。As shown in Tables 1 and 2, the insulating resin compositions of Examples 1 to 6 gave good results for all evaluation items including laser processability.
【0048】なお、実施例3の結果から、シランカップ
リング剤を使用することにより、絶縁性樹脂組成物の粘
度減少効果が小さいことが分かる。また、実施例4及び
比較例4の結果から、フィラの含有量を減少させると反
りが生ずる傾向があることが分かる。実施例5の結果か
ら、フィラの平均粒径が小さくなると、絶縁性樹脂組成
物の粘度が増大する傾向があることが分かる。また、比
較例1〜3の結果から、粒径64μm以上のフィラの含
有量が5%を超えると、レーザ加工によりえぐれが生
じ、レーザ加工性が低下することが分かる。また、シリ
コーンオイルを使用すると、スルホール用孔内面にメッ
キが析出しないことがわかる。比較例6の結果から、分
散剤を使用しないと絶縁性樹脂組成物の粘度が増大し過
ぎることがわかる。The results of Example 3 show that the use of the silane coupling agent has a small effect of reducing the viscosity of the insulating resin composition. Further, from the results of Example 4 and Comparative Example 4, it can be seen that when the content of filler is reduced, warpage tends to occur. From the results of Example 5, it can be seen that the viscosity of the insulating resin composition tends to increase as the average particle size of the filler decreases. Further, from the results of Comparative Examples 1 to 3, it can be seen that when the content of the filler having a particle diameter of 64 μm or more exceeds 5%, engraving occurs due to the laser processing and the laser processability deteriorates. Further, it is found that when silicone oil is used, plating does not deposit on the inner surface of the through hole. From the results of Comparative Example 6, it can be seen that the viscosity of the insulating resin composition increases too much unless a dispersant is used.
【0049】[0049]
【発明の効果】本発明によれば、電子部品内蔵配線板に
使用可能な封止用の絶縁性樹脂組成物に対し、良好なレ
ーザ加工性を付与することができる。しかも、電子部品
内蔵配線板の反りの発生を抑制することができる。更
に、シリコーンオイルフリーとすることによりメッキ性
も向上させることができる。According to the present invention, excellent laser processability can be imparted to an insulating resin composition for sealing which can be used for a wiring board with a built-in electronic component. In addition, it is possible to suppress the occurrence of warpage of the electronic component built-in wiring board. Further, by making the silicone oil free, the plating property can be improved.
【図1】 本発明の電子部品内蔵配線板の概略断面図で
ある。FIG. 1 is a schematic sectional view of a wiring board with a built-in electronic component of the present invention.
【図2】 本発明の電子部品内蔵配線板の製造工程図で
ある。FIG. 2 is a manufacturing process diagram of a wiring board with a built-in electronic component of the present invention.
【図3】 従来の電子部品内蔵配線板の概略断面図であ
る。FIG. 3 is a schematic sectional view of a conventional wiring board with built-in electronic components.
【図4】 従来の電子部品内蔵配線板のレーザ加工時に
生ずるえぐれの説明図である。FIG. 4 is an explanatory diagram of an engraving that occurs during laser processing of a conventional wiring board with built-in electronic components.
1 第1基材、2 第1配線、3 第1配線基板、4
電子部品、5 絶縁層、6 第2基材、7 第2配線、
8 第2配線基板、9 バイアホール、10ソルダーレ
ジスト層、11 異方性導電接着フィルム1 1st base material, 2 1st wiring, 3 1st wiring board, 4
Electronic parts, 5 insulating layers, 6 second base material, 7 second wiring,
8 second wiring board, 9 via holes, 10 solder resist layer, 11 anisotropic conductive adhesive film
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 23/31 H05K 3/46 Q H05K 3/46 T H01L 23/30 R (72)発明者 藤井 誉人 栃木県鹿沼市さつき町18 ソニーケミカル 株式会社内 (72)発明者 関 かおり 栃木県鹿沼市さつき町18 ソニーケミカル 株式会社内 Fターム(参考) 4J002 AA021 CD011 CD051 CD061 CD101 DJ016 FD140 FD150 GQ01 4M109 AA01 BA03 EB11 5E346 AA05 AA12 AA15 AA17 AA26 AA32 AA38 AA43 BB01 CC02 CC08 CC09 CC32 DD02 DD03 DD32 EE02 EE06 EE07 FF04 FF45 GG19 GG22 GG28 GG40 HH11 5G303 AA07 AA08 AB20 BA12 CA09 CA11 5G305 AA13 AB36 AB40 BA15 CA15 CC02 CD08 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 7 Identification code FI theme code (reference) H01L 23/31 H05K 3/46 Q H05K 3/46 T H01L 23/30 R (72) Inventor Yoshii Fujii 18 Satsuki-cho, Kanuma-shi, Tochigi Sony Chemical Co., Ltd. (72) Inventor Kaori Seki 18 Satsuki-cho, Kanuma-shi, Tochigi Sony Chemical Co., Ltd. F-term (reference) 4J002 AA021 CD011 CD051 CD061 CD101 DJ016 FD140 FD150 GQ01 4M109 AA01 BA03 EB11 5E346 AA05 AA12 AA15 AA17 AA26 AA32 AA38 AA43 BB01 CC02 CC08 CC09 CC32 DD02 DD03 DD32 EE02 EE06 EE07 FF04 FF45 GG19 GG22 GG28 GG40 HH11 5G303 AA07 AA08 AB20 BA12 CA09 CA11 5G305 BA13 A13 A40
Claims (7)
散してなる絶縁性樹脂組成物において、該非導電性フィ
ラの平均粒径が0.3〜20μmであり、全非導電性フ
ィラに占める粒径64μm以上の非導電性フィラの割合
が5.0重量%以下であることを特徴とする絶縁性樹脂
組成物。1. An insulating resin composition comprising a non-conductive filler dispersed in a thermosetting component, wherein the non-conductive filler has an average particle size of 0.3 to 20 μm, and all non-conductive fillers are contained. The insulating resin composition is characterized in that the proportion of the non-conductive filler having a particle diameter of 64 μm or more in the above is 5.0% by weight or less.
μmである請求項1記載の絶縁性樹脂組成物。2. The non-conductive filler has an average particle size of 3 to 15.
The insulating resin composition according to claim 1, which has a thickness of μm.
重量%である請求項1又は2記載の絶縁性樹脂組成物。3. The content of the non-conductive filler is 60 to 90.
The insulating resin composition according to claim 1, wherein the insulating resin composition has a weight percentage.
項1〜3のいずれかに記載の絶縁性樹脂組成物。4. The insulating resin composition according to claim 1, which contains no silicone oil.
形成されている第1配線基板と、 第1配線基板上で該第1配線に接続されている電子部品
と、 該電子部品を封止する絶縁層と、 該絶縁層上に設けられている、第2基材の少なくとも片
面に第2配線が形成されている第2配線基板と、 第1配線と第2配線とを接続しているバイアホールと、
からなる電子部品内蔵配線板において、 該絶縁層が、熱硬化性成分中に非導電性フィラが分散し
てなる絶縁性樹脂組成物から形成されたものであって、
該非導電性フィラの平均粒径が0.3〜20μmであ
り、全非導電性フィラに占める粒径64μm以上の非導
電性フィラの割合が5.0重量%以下であることを特徴
とする電子部品内蔵配線板。5. A first wiring substrate having a first wiring formed on at least one surface of a first base material, an electronic component connected to the first wiring on the first wiring substrate, and the electronic component. The insulating layer to be sealed, the second wiring substrate provided on the insulating layer, and having the second wiring formed on at least one surface of the second base material, are connected to the first wiring and the second wiring. With a via hole
A wiring board having a built-in electronic component, wherein the insulating layer is formed of an insulating resin composition in which a non-conductive filler is dispersed in a thermosetting component,
An electron characterized in that the non-conductive filler has an average particle size of 0.3 to 20 μm, and the proportion of the non-conductive filler having a particle size of 64 μm or more in all non-conductive fillers is 5.0% by weight or less. Wiring board with built-in components.
配線板の外表面となっている請求項5記載の電子部品内
蔵配線板。6. The electronic component built-in wiring board according to claim 5, wherein the second wiring of the second substrate is an outer surface of the electronic component built-in wiring board.
5又は6記載の電子部品内蔵配線板。7. The wiring board with a built-in electronic component according to claim 5, wherein the electronic component is a semiconductor chip.
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008258429A (en) * | 2007-04-05 | 2008-10-23 | Sekisui Chem Co Ltd | Insulating film, method of manufacturing electronic component apparatus, and electronic component apparatus |
CN101783337A (en) * | 2009-01-13 | 2010-07-21 | 恩益禧电子股份有限公司 | Electronic device |
JP2010182908A (en) * | 2009-02-06 | 2010-08-19 | Sekisui Chem Co Ltd | Thermosetting adhesive for electronic component and method of manufacturing electronic component embedded substrate using the same |
JP2011086680A (en) * | 2009-10-13 | 2011-04-28 | Nec Corp | Multilayer wiring board and method of manufacturing multilayer wiring board |
JP2012044163A (en) * | 2010-08-18 | 2012-03-01 | Dyconex Ag | Method for embedding electrical component |
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JP2010182908A (en) * | 2009-02-06 | 2010-08-19 | Sekisui Chem Co Ltd | Thermosetting adhesive for electronic component and method of manufacturing electronic component embedded substrate using the same |
JP2011086680A (en) * | 2009-10-13 | 2011-04-28 | Nec Corp | Multilayer wiring board and method of manufacturing multilayer wiring board |
JP2012044163A (en) * | 2010-08-18 | 2012-03-01 | Dyconex Ag | Method for embedding electrical component |
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