JPH11317383A - Method for dividing semiconductor chip encapsulated with resin - Google Patents
Method for dividing semiconductor chip encapsulated with resinInfo
- Publication number
- JPH11317383A JPH11317383A JP10161293A JP16129398A JPH11317383A JP H11317383 A JPH11317383 A JP H11317383A JP 10161293 A JP10161293 A JP 10161293A JP 16129398 A JP16129398 A JP 16129398A JP H11317383 A JPH11317383 A JP H11317383A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- sealing resin
- dividing
- notch
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Dicing (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、多数個の半導体チップ
をセラミック基板に搭載し、樹脂で封止した後、各チッ
プを分断する方法に係わるものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of mounting a large number of semiconductor chips on a ceramic substrate, sealing the chips with a resin, and cutting each chip.
【０００２】[0002]
【従来の技術】近年、半導体の業界では、一度に多量の
素子を基板に搭載し、搭載した素子を同時に樹脂封止し
た後、ダイヤモンドカッターで切断して各素子を分離す
ることが行われているが、封止樹脂には、溶融シリカが
混合されているために、ダイヤモンドカッターの摩耗が
激しく、これが半導体デバイスの大きなコストアップ要
因になっている。大量搭載、大量封止したチップをいか
に安く分割するか、これが、半導体デバイスのコストダ
ウンのキーポイントである。2. Description of the Related Art In recent years, in the semiconductor industry, a large number of elements are mounted on a substrate at one time, and the mounted elements are simultaneously sealed with a resin, and then cut with a diamond cutter to separate the elements. However, since fused silica is mixed in the sealing resin, the diamond cutter is severely worn, which is a major factor in increasing the cost of the semiconductor device. The key to reducing the cost of semiconductor devices is how to divide a chip mounted and sealed in a large amount at a low cost.
【０００３】[0003]
【発明が解決する課題】本発明は、かかる問題点に鑑み
てなされたもので、ダイヤモンドカッターで切断する事
なく、安価に分離、分割できる新規な方法を提供せんと
するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a novel method capable of separating and dividing at low cost without cutting with a diamond cutter.
【０００４】[0004]
【問題を解決するための手段】上記問題点は次の方法で
解決される。すなわち、 １． 多数個の半導体チップをセラミック基板に搭載
し、樹脂で封止した後、各チップを分断するに際して、
該封止樹脂にセラミックフィラーを混合すると共に、該
セラミック基板のチップ搭載面の裏面に、該分断する線
に沿ってノッチを入れ、該ノッチの反対側の封止樹脂側
から押圧して該ノッチの線に沿ってセラミックおよび封
止樹脂を割断することによって各チップ片に分断するこ
とを特徴とする樹脂で封止した半導体チップの分断方法 ２． 上記割断時、超音波衝撃を印加して押圧すること
を特徴とする上記１に記載の分断方法。 ３． 上記超音波衝撃を印加する際、超音波衝撃先端子
と封止樹脂の接触面の間にプラスチックのテープを挟
み、該封止樹脂面に貼着することを特徴とする上記２に
記載の分断方法。 ４． 上記セラミックフィラーの混合量が、５０〜９３
重量％である上記１〜３のいずれかに記載の分断方法。 ５． 上記セラミックフィラーの最大粒径が６０ミクロ
ン以下である上記４に記載の分断方法。The above problem is solved by the following method. That is, 1. After mounting a large number of semiconductor chips on a ceramic substrate and sealing it with resin, when dividing each chip,
A ceramic filler is mixed with the sealing resin, and a notch is formed on the back surface of the chip mounting surface of the ceramic substrate along the dividing line, and the notch is pressed from the sealing resin side opposite to the notch. 1. A method for cutting a semiconductor chip sealed with a resin, wherein the chip is cut into individual chip pieces by cutting the ceramic and the sealing resin along the line. 2. The dividing method according to the above item 1, wherein an ultrasonic impact is applied and pressed during the cutting. 3. 3. The dividing according to the above item 2, wherein when applying the ultrasonic shock, a plastic tape is sandwiched between a contact surface of the ultrasonic impact tip terminal and the sealing resin, and is adhered to the sealing resin surface. Method. 4. The mixing amount of the ceramic filler is 50 to 93.
The dividing method according to any one of the above 1 to 3, which is% by weight. 5. 5. The cutting method according to the above 4, wherein the ceramic filler has a maximum particle size of 60 microns or less.
【０００５】[0005]
【発明の実施の形態】封止樹脂の中に小粒子のセラミッ
クフィラーを混合すると、割断した面にチッピングが無
くなり、割断面がより平滑になる。混合量は、４５〜９
３重量％の範囲が好ましい。下限値未満では、チッピン
グが起こることがある。上限を越えると、封止樹脂の強
度が落ちて好ましくない。最も好ましい範囲は、６０〜
９０重量％である。樹脂の種類は、エポキシ系、ナフタ
リン系、ビフェニール系等、通常使用されている封止樹
脂はすべて使用できる。BEST MODE FOR CARRYING OUT THE INVENTION When a small-particle ceramic filler is mixed into a sealing resin, chipping is eliminated on the cut surface, and the cut surface becomes smoother. The mixing amount is 45-9
A range of 3% by weight is preferred. Below the lower limit, chipping may occur. Exceeding the upper limit is not preferred because the strength of the sealing resin decreases. The most preferred range is from 60 to
90% by weight. As for the kind of the resin, all of the commonly used sealing resins such as epoxy type, naphthalene type and biphenyl type can be used.
【０００６】セラミックフィラーの種類は、通常されて
いるセラミックフィラーはすべて使用できる。すなわ
ち、シリカ、アルミナ、ジルコニア、ＢＮ、窒化ケイ
素、窒化アルミ、マグネシア、ムライト、等々、通常の
酸化物、窒化物等の粉末はすべて使用できる。粉末の粒
度は、細かくなるほど割断面の平滑性は向上する。割断
面の平滑性は製品の仕様によって異なるが、概ねの最大
粒径６０〜７０ミクロン程度以下が好ましい。最大粒径
６０ミクロン、平均粒径１５〜２０ミクロンのフィラー
の場合、割断面の平滑性は、概ね±２５〜３５ミクロン
以下になる。フィラーの形状は、球に近く、角の無いほ
うが、割断面はより平滑になる。As for the type of ceramic filler, any commonly used ceramic filler can be used. That is, powders such as silica, alumina, zirconia, BN, silicon nitride, aluminum nitride, magnesia, mullite, etc., and ordinary oxides and nitrides can all be used. The finer the particle size of the powder, the better the smoothness of the fractured surface. Although the smoothness of the fractured surface varies depending on the specifications of the product, it is preferable that the maximum particle size be approximately 60 to 70 microns or less. In the case of a filler having a maximum particle size of 60 microns and an average particle size of 15 to 20 microns, the smoothness of the fractured surface is generally ± 25 to 35 microns or less. The shape of the filler is closer to a sphere and has no corners, so that the fracture surface becomes smoother.
【０００７】セラミック基板に形成するノッチの形状
は、Ｖノッチ、Ｕノッチ、いずれの形状でも良いが、Ｖ
ノッチの方が、割断面がよりシャープになる。ノッチの
溝深さは、基板の肉厚の１／６以上が好ましく、概ね
０．１〜０．５ｍｍ程度が良い。The shape of the notch formed on the ceramic substrate may be any of a V notch and a U notch.
The notch has a sharper cut surface. The groove depth of the notch is preferably 1/6 or more of the thickness of the substrate, and is preferably about 0.1 to 0.5 mm.
【０００８】割断は、ノッチの反対面の封止樹脂の表面
を押圧して行う。超音波衝撃で押圧するとより効果的で
ある。超音波衝撃で押圧すると、割断面がより平滑にな
り、封止樹脂の欠けを防止できる。また、ディラミネー
ションすなわち、基板と樹脂面の界面の剥離防止に効果
がある。The cutting is performed by pressing the surface of the sealing resin opposite to the notch. Pressing with ultrasonic impact is more effective. When pressed by ultrasonic impact, the fractured section becomes smoother, and chipping of the sealing resin can be prevented. In addition, it is effective in preventing delamination, ie, peeling of the interface between the substrate and the resin surface.
【０００９】封止樹脂のエッジ部の欠け防止には、超音
波衝撃の先端子と封止樹脂の表面にプラスチックのテー
プを挟み、テープを封止樹脂の表面に貼着して超音波衝
撃を与えると、割断時、封止樹脂のエッジ部に発生する
欠けが防止できる。To prevent chipping of the edge portion of the sealing resin, a plastic tape is sandwiched between the terminal of the ultrasonic impact and the surface of the sealing resin, and the tape is adhered to the surface of the sealing resin to prevent the ultrasonic impact. If it is given, chipping generated at the edge of the sealing resin at the time of cutting can be prevented.
【００１０】本発明の実施の形態を図面で説明する。図
１，２は本発明方法の説明図である。図１は単純押圧、
図２は超音波衝撃押圧の説明図である。An embodiment of the present invention will be described with reference to the drawings. 1 and 2 are explanatory diagrams of the method of the present invention. Figure 1 is a simple press,
FIG. 2 is an explanatory diagram of the ultrasonic impact pressing.
【００１１】図１で、セラミック基板１の裏面に割断す
る線に沿ってノッチ２を入れて、矢印の方向から機械的
に、あるいは指で押圧して、封止樹脂３とセラミック基
板１を一緒に割断する。封止樹脂には、割断面を平滑に
するために小粒子のセラミックフィラーを混合する。In FIG. 1, a notch 2 is formed along a cutting line on the back surface of the ceramic substrate 1, and the sealing resin 3 and the ceramic substrate 1 are pressed together mechanically or with a finger in the direction of the arrow. Cut into pieces. Small particles of ceramic filler are mixed into the sealing resin to smooth the fractured surface.
【００１２】図２で超音波衝撃の先端子４と封止樹脂３
の間に樹脂テープ５を挟み、樹脂テープは封止樹脂３に
貼着して超音波衝撃を印加する。割断したさい、樹脂の
エッジ部に欠けが起こりやすいが、テープの貼着は、こ
れを防止する。In FIG. 2, the terminal 4 and the sealing resin 3 of the ultrasonic impact are shown.
A resin tape 5 is interposed therebetween, and the resin tape is attached to the sealing resin 3 to apply an ultrasonic impact. Chipping is likely to occur at the edge of the resin when cutting, but sticking the tape prevents this.
【００１３】[0013]
【実施例】実施例によって本発明を説明する。 実施例１ 図１の方法 セラミック基板：１１０ｍｍ×１１０ｍｍ、厚さ０．８
ｍｍの９６％アルミナ基板を使用。 半導体チップ ： ４ｍｍ×６ｍｍの半導体チップをセ
ラミック基板の上に３６個搭載し、基板の配線回路とワ
イヤーボンドした。 封止樹脂 ：平均粒径１３ミクロン、最大粒径４４
ミクロンの溶融シリカの粉末をエポキシ系樹脂に８５重
量％混合したものを使用した。 ノッチ深さ ：Ｖノッチ ０．４ｍｍ ノッチ幅 ：０．２ｍｍ 封止樹脂を硬化後、図１の矢印に示す方向から折り曲げ
て割断した。割断面の平滑性は、±２０ミクロン以下で
あった。ダイヤモンドカッターによる切断面と比較して
もより平滑な面で遜色なかった。また分断速度はダイヤ
モンドカッターの約４倍で極めて生産性が高かった。ダ
イヤモンドカッターで切断するときは水冷の必要があ
り、また粉塵も発生するが、本方法は粉塵も熱も発生せ
ず、環境衛生上極めてクリーンな方法であった。またダ
イヤモンドカッターで切断するときに発生するチップの
水濡れ、水の侵入等による信頼性の低下の問題が解決で
きた。The present invention will be described by way of examples. Example 1 Method of FIG. 1 Ceramic substrate: 110 mm × 110 mm, thickness 0.8
mm 96% alumina substrate is used. Semiconductor chip: 36 semiconductor chips of 4 mm × 6 mm were mounted on a ceramic substrate and wire-bonded to a wiring circuit of the substrate. Sealing resin: average particle size 13 microns, maximum particle size 44
A mixture obtained by mixing 85% by weight of an epoxy resin with micron fused silica powder was used. Notch depth: V notch 0.4 mm Notch width: 0.2 mm After curing the sealing resin, the sealing resin was bent and cut in the direction indicated by the arrow in FIG. The smoothness of the fractured section was ± 20 microns or less. Compared with the cut surface by the diamond cutter, it was comparable to the smoother surface. The cutting speed was about four times that of a diamond cutter, and the productivity was extremely high. When cutting with a diamond cutter, water cooling is necessary, and dust is also generated. However, this method does not generate dust or heat, and is extremely clean in terms of environmental hygiene. In addition, the problem of reduced reliability due to chip wetness, water intrusion, and the like that occur when cutting with a diamond cutter could be solved.
【００１４】実施例２ 図２の方法 セラミック基板：５０ｍｍ×５０ｍｍ、厚さ０．８ｍｍ
の９６％アルミナ基板 半導体チップ ： ３ｍｍ×４ｍｍの半導体チップをセ
ラミック基板の上に２５個搭載し、基板の配線回路とワ
イヤーボンドした。 封止樹脂 ：平均粒径 １０ミクロン、最大粒径３
０ミクロンのアルミナ粉末をエポキシ系樹脂に８０重量
％混合したものを使用した。 ノッチ深さ ：Ｖノッチ ０．３ｍｍ ノッチ幅 ：０．２ｍｍ 封止樹脂を硬化後、厚さ２５ミクロンの樹脂テープを封
止樹脂表面に貼り付けた。樹脂テープの上から超音波衝
撃子の先端子を押しつけてノッチ部から割断した。割断
面の平滑性は、±１７ミクロン以下であった。ダイヤモ
ンドカッターによる切断面と比較しても遜色なかった。
生産性はダイヤモンドカッターの５倍であった。Example 2 Method of FIG. 2 Ceramic substrate: 50 mm × 50 mm, thickness 0.8 mm
Semiconductor chip: 25 semiconductor chips of 3 mm × 4 mm were mounted on a ceramic substrate and wire-bonded to a wiring circuit of the substrate. Sealing resin: average particle size 10 microns, maximum particle size 3
A mixture of 0 micron alumina powder mixed with an epoxy resin at 80% by weight was used. Notch depth: V notch 0.3 mm Notch width: 0.2 mm After curing the sealing resin, a 25-μm-thick resin tape was stuck on the surface of the sealing resin. The tip terminal of the ultrasonic impactor was pressed from above the resin tape to cut from the notch. The smoothness of the fractured section was ± 17 microns or less. It was comparable to the cut surface with a diamond cutter.
Productivity was five times that of a diamond cutter.
【００１５】[0015]
【発明の効果】以上詳記したように、本発明方法は、環
境衛生上極めてクリーンで、かつ安価な上に、生産性、
信頼性、共に高く、半導体デバイス生産の分野に多大の
貢献をなすものである。As described above in detail, the method of the present invention is extremely clean in terms of environmental hygiene, is inexpensive, has high productivity,
Both are highly reliable and make a great contribution to the field of semiconductor device production.
【図１】図１は、本発明方法の説明図である。FIG. 1 is an explanatory diagram of the method of the present invention.
【図２】図２は、超音波を使用するときの本発明方法の
説明図である。FIG. 2 is an explanatory diagram of the method of the present invention when using ultrasonic waves.
１…セラミック基板 ２…ノッチ ３…封止樹脂 ４…超音波衝撃の先端子 ５…樹脂テープ DESCRIPTION OF SYMBOLS 1 ... Ceramic substrate 2 ... Notch 3 ... Sealing resin 4 ... Terminal of ultrasonic impact 5 ... Resin tape
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｌ 23/30 Ｒ ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 6 Identification code FI H01L 23/30 R
Claims (5)
に搭載し、樹脂で封止した後、各チップを分断するに際
して、該封止樹脂にセラミックフィラーを混合すると共
に、該セラミック基板のチップ搭載面の裏面に、該分断
する線に沿ってノッチを入れ、該ノッチの反対側の封止
樹脂側から押圧して該ノッチの線に沿ってセラミックお
よび封止樹脂を割断することによって各チップ片に分断
することを特徴とする樹脂で封止した半導体チップの分
断方法。1. A method for mounting a plurality of semiconductor chips on a ceramic substrate, sealing the resin with a resin, and then, when cutting each chip, mixing a ceramic filler into the sealing resin and a chip mounting surface of the ceramic substrate. On the back surface of each chip piece, a notch is made along the dividing line, and the ceramic and sealing resin are cut along the notch line by pressing from the sealing resin side opposite to the notch. A method for dividing a semiconductor chip sealed with a resin, which comprises dividing the semiconductor chip.
することを特徴とする請求項１に記載の分断方法。2. The dividing method according to claim 1, wherein an ultrasonic impact is applied and pressed during the cutting.
撃先端子と封止樹脂の接触面の間にプラスチックのテー
プを挟み、該封止樹脂面に貼着することを特徴とする請
求項２に記載の分断方法。3. When applying the ultrasonic shock, a plastic tape is sandwiched between a contact surface of the ultrasonic shock receiving terminal and the sealing resin, and is adhered to the sealing resin surface. Item 4. The dividing method according to Item 2.
０〜９３重量％である請求項１〜３のいずれかに記載の
分断方法。4. The mixed amount of the ceramic filler is 5
The dividing method according to any one of claims 1 to 3, which is 0 to 93% by weight.
０ミクロン以下である請求項４に記載の分断方法。5. The maximum particle size of the ceramic filler is 6
5. The dividing method according to claim 4, wherein the size is 0 micron or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10161293A JPH11317383A (en) | 1998-05-06 | 1998-05-06 | Method for dividing semiconductor chip encapsulated with resin |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10161293A JPH11317383A (en) | 1998-05-06 | 1998-05-06 | Method for dividing semiconductor chip encapsulated with resin |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11317383A true JPH11317383A (en) | 1999-11-16 |
Family
ID=15732365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10161293A Pending JPH11317383A (en) | 1998-05-06 | 1998-05-06 | Method for dividing semiconductor chip encapsulated with resin |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11317383A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003234439A (en) * | 2002-02-07 | 2003-08-22 | Sony Chem Corp | Insulative resin composite |
| JP2006278906A (en) * | 2005-03-30 | 2006-10-12 | Oki Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP2007250943A (en) * | 2006-03-17 | 2007-09-27 | Hitachi Metals Ltd | Semiconductor device |
| JP2011060985A (en) * | 2009-09-10 | 2011-03-24 | Murata Mfg Co Ltd | Method of manufacturing electronic component |
| JP2013522874A (en) * | 2010-03-08 | 2013-06-13 | フォームファクター， インコーポレイテッド | Wiring board with customized layer |
| US9755105B2 (en) | 2015-01-30 | 2017-09-05 | Nichia Corporation | Method for producing light emitting device |
| CN110277324A (en) * | 2019-06-28 | 2019-09-24 | 广东工业大学 | Fan-out-type module ultrasound packaging technology, equipment and structure |
-
1998
- 1998-05-06 JP JP10161293A patent/JPH11317383A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003234439A (en) * | 2002-02-07 | 2003-08-22 | Sony Chem Corp | Insulative resin composite |
| JP2006278906A (en) * | 2005-03-30 | 2006-10-12 | Oki Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| US8143718B2 (en) | 2005-03-30 | 2012-03-27 | Oki Semiconductor Co., Ltd. | Semiconductor device having stress relaxation sections |
| JP2007250943A (en) * | 2006-03-17 | 2007-09-27 | Hitachi Metals Ltd | Semiconductor device |
| US7948059B2 (en) | 2006-03-17 | 2011-05-24 | Hitachi Metals, Ltd. | Dividable semiconductor device having ceramic substrate and surface mount components collectively sealed on principle surface of ceramic substrate |
| JP2011060985A (en) * | 2009-09-10 | 2011-03-24 | Murata Mfg Co Ltd | Method of manufacturing electronic component |
| JP2013522874A (en) * | 2010-03-08 | 2013-06-13 | フォームファクター， インコーポレイテッド | Wiring board with customized layer |
| US9755105B2 (en) | 2015-01-30 | 2017-09-05 | Nichia Corporation | Method for producing light emitting device |
| CN110277324A (en) * | 2019-06-28 | 2019-09-24 | 广东工业大学 | Fan-out-type module ultrasound packaging technology, equipment and structure |
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