JP2003233344A - Image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display device capable of preferably correcting variation in driving conditions due to electric resistance of matrix wiring of a display panel by using less hardware. <P>SOLUTION: The image display device is provided with a corrected image data calculation means 14 for calculating corrected image data which are image data corrected in an influence of a voltage drop caused at least by the resistance portion of row wiring and a scanning means, an amplitude adjusting means having a function of adjusting an amplitude of the corrected image data Dout so that the amplitude of the corrected image data Dout corresponds to the input ranges of a modulation means 8, and the modulation means 8 for receiving the image data corrected in the amplitude and outputting a modulated signal to the column wiring. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device provided with image forming elements arranged in a matrix, for example, a plurality of surface-conduction type elements arranged in matrix and receiving electron beam irradiation thereof. It is applied to a television receiver or a display device that receives a display signal from a television signal or a computer using a display panel having a phosphor screen that emits light and displays an image, and in particular the electric power that the matrix wiring of the display panel has. The present invention relates to a digital image data processing unit having an image data correction unit that corrects a drive voltage drop caused by resistance and an amplitude adjustment unit that controls the amplitude of the corrected image data.

[0002]

2. Description of the Related Art Conventionally, in this type of image display device, in order to correct a decrease in brightness due to a voltage drop due to a wiring resistance such as an electrical connection wiring to an electron-emitting device, the correction data is statistically calculated. An image display device having a configuration for calculating and synthesizing an electron beam requirement value and a correction value is disclosed in Japanese Patent Application Laid-Open No. 8-
It is disclosed in Japanese Patent No. 248920.

FIG. 63 is a schematic block diagram of an image display device according to the prior art. The configuration related to the correction of image data will be described below.

First, the brightness data for one line of the digital image signal is added up by the adder 206, and the correction rate data corresponding to this added value is read from the memory 207.

On the other hand, the digital image signal is serial / parallel converted in the shift register 204, held in the latch circuit 205 for a predetermined time, and then input to a multiplier 208 provided for each column wiring at a predetermined timing.

In the multiplier 208, the brightness data and the correction data read from the memory 207 are multiplied for each column wiring, and the obtained corrected data is the modulated signal generator 2.
09, the modulation signal corresponding to the corrected data is generated in the modulation signal generator 209, and an image is displayed on the display panel based on this modulation signal.

Here, like the summing process of the luminance data for one line of the digital image signal in the summing device 206, statistical calculation processing such as calculating the sum or average of the digital image signals is performed. Correction is performed based on this value.

On the other hand, as a general signal processing means, Japanese Patent Application Laid-Open No. 01-091515 discloses a pulse width modulator having an overflow detection section and a limiter, and Japanese Patent Application Laid-Open No. 07-273650 discloses an overflow detection section and a gain control. An A / D conversion circuit having a section is disclosed.

[0009]

However, in the case of the prior art as described above, a multiplier for each column wiring, a memory for outputting correction data, a summing device for giving an address signal to the memory, etc. Large hardware was needed.

Further, the correction may cause overflow in the image data and disturb the displayed image.

The present invention has been made in order to solve the above-mentioned problems of the prior art, and its object is to reduce the resistance of the matrix wiring of the display panel and the internal resistance of the scanning means with a small amount of hardware. An object of the present invention is to provide an image display device excellent in image quality by appropriately correcting the influence of voltage drop.

[0012]

In order to achieve the above object, the present invention provides a display panel including a plurality of row wirings and column wirings and image forming elements connected to them and arranged in a matrix. And a scanning means for sequentially selecting and scanning the row wirings, and a modulation means connected to the column wirings, wherein a voltage generated by at least a resistance component of the row wirings with respect to image data. Corrected image data calculating means for calculating corrected image data for correcting the influence of the drop, and amplitude adjusting means for adjusting the amplitude of the corrected image data so that the amplitude of the corrected image data falls within the input range of the modulating means. And, the modulation means receives the corrected image data whose amplitude is adjusted,
A modulation signal is output to the column wiring.

The amplitude adjusting means is provided with a limit for limiting the amplitude so that the corrected image data or the image data is multiplied by the gain and the multiplication result is completely within the input range of the modulating means. Is preferred.

The amplitude adjusting means detects a maximum value of the output of the corrected image data calculating means, and a gain calculating section for calculating the gain so that the maximum value falls within the input range of the modulating means. It is preferable to have a filter means for limiting the variation of the gain for each frame.

The amplitude adjusting means further comprises a scene switching discriminating section for detecting that the scene of the display image has changed, and the filtering means carries out a process in which the variation of the gain is limited when the scene switching is discriminated. It is preferred not to.

It is preferable that the amplitude adjusting means has a gain limiting section for limiting the gain to a preset upper limit value or less.

The maximum value detection unit excludes the corrected image data for the row wirings of one or more and 1/10 or less of the total number of wirings from the upper and lower end portions of the display area, except for the other rows. It is preferable to detect the maximum value of the corrected image data for the wiring.

The scene switching discriminating unit divides the entire screen into a plurality of areas, discriminates whether or not there is a scene switching in each area, and discriminates the scene switching of the entire screen from each discrimination result. Is preferred.

The amplitude adjusting means includes an external illuminance input section for detecting the illuminance around the image display device and outputting a signal according to the detection result, and the gain is adjusted according to the output signal of the external illuminance input section. Is preferred.

The amplitude adjusting means refers to the output of the corrected image data calculating means for each frame, and calculates the adaptive gain calculated for each frame so that the output corresponds to the input range of the modulating means. Which has at least two operation modes including a first operation mode for outputting a preset fixed gain that does not change for each frame, and an input video signal is for a television. It is preferable that the first operation mode is selected for the video signal of No. 1 and the second operation mode is selected for the video signal for computer.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings.
This will be described in detail by taking as an example an image display device using a CE).

(First Embodiment) (Overall Overview) In a display device in which SCEs are arranged in a simple matrix, a voltage drop occurs due to a current flowing into a scanning wiring and a wiring resistance of the scanning wiring, and a display image is deteriorated. There is a phenomenon of doing. Therefore, the image display device according to the embodiment of the present invention is provided with a processing circuit that appropriately corrects the influence of the voltage drop in the scanning wiring on the display image, and realizes it with a relatively small circuit scale. Configured to.

The correction circuit predicts and calculates the deterioration of the display image caused by the voltage drop according to the input image data, obtains correction data for correcting the deterioration, and corrects the input image data.

As an image display device incorporating such a correction circuit, the present inventors have conducted extensive studies on an image display device of the following system.

In describing the present invention below,
First, an overview of the display panel of the image display device according to the embodiment of the present invention, electrical connection of the display panel, SCE characteristics,
A method of driving the display panel, a mechanism of voltage drop due to the electric resistance of the scanning wiring, a correction method and an apparatus for the influence of the voltage drop will be described.

(Overview of Image Display Device) FIG. 1 is a perspective view of a display panel used in the image display device according to the present embodiment. A part of the panel is cut away to show the internal structure. There is. In the figure, 1005 is a rear plate, 1006
Is a side wall, 1007 is a face plate, and 1005
˜1007 form an airtight container for maintaining a vacuum inside the display panel.

The rear plate 1005 has a substrate 1001.
Are fixed, but N × M SCEs 1002 as image forming elements are formed on the substrate. The row wiring (scanning wiring) 1003, the column wiring (modulation wiring) 1004, and the SCE are connected as shown in FIG.

On the lower surface of the face plate 1007, phosphors 1008 of three primary colors of red, blue and green are formed corresponding to each pixel.

A metal back 1 is formed on the lower surface of the fluorescent film 1008.
009 is formed.

Hv is a high voltage terminal and is a metal back 100.
9 is electrically connected. By applying a high voltage to the Hv terminal, a high voltage is applied between the rear plate 1005 and the face plate 1007.

(Characteristics of SCE) The SCE has the characteristics of (emission current Ie) versus (element applied voltage Vf) and (element current If) versus (element applied voltage Vf) as shown in FIG. Since the emission current Ie is significantly smaller than the device current If and it is difficult to draw the same current scale, the two graphs are shown on different scales.

The SCE has the following three characteristics regarding the emission current Ie.

First, a certain voltage (this is the threshold voltage Vth
When the above voltage is applied to the element, the emission current Ie rapidly increases, while the emission current Ie is hardly detected at a voltage lower than the threshold voltage Vth.

Second, since the emission current Ie changes depending on the voltage Vf applied to the element, the magnitude of the emission current Ie can be controlled by changing the voltage Vf.

Thirdly, since it has a high-speed response,
The emission time of the emission current Ie can be controlled by the application time of the voltage Vf.

In the image display device using the display panel shown in FIG. 1, if the first characteristic is utilized, it is possible to sequentially scan the display screen for display. That is, the threshold voltage Vth is set to the driven element according to the desired emission brightness.
The above voltages are appropriately applied, and a voltage lower than the threshold voltage Vth is applied to the non-selected elements. By sequentially switching the elements to be driven, it is possible to sequentially scan the display screen for display.

By utilizing the second characteristic,
By the voltage Vf applied to the element, the emission brightness of the phosphor can be controlled and an image can be displayed.

By utilizing the third characteristic,
The light emission time of the phosphor can be controlled by the time for which the voltage Vf is applied to the element, and an image can be displayed.

In the image display device of the present invention, modulation is performed using the third characteristic.

(Driving Method of Display Panel) FIG. 4 shows an example of the voltage applied to the voltage supply terminals of the scanning wiring and the modulation wiring when driving the display panel of the present invention.

Here, the horizontal scanning period I is a period in which the pixels in the i-th row emit light.

In order to cause the pixels in the i-th row to emit light,
The scanning wiring of the i-th row is selected and its voltage supply terminal D
The selection potential Vs is applied to xi. Further, the voltage supply terminals Dxk (k = 1, 2, ... N, where k ≠ i) of the other scanning wirings are set in the non-selected state and the non-selection potential Vns is applied.

In this embodiment, the selection potential Vs is set to -0.5VSEL which is half the voltage VSEL shown in FIG. 3, and the non-selection potential Vns is the GND potential.

A pulse width modulation signal having a voltage amplitude Vpwm was supplied to the voltage supply terminal of the modulation wiring. Conventionally, the pulse width of the pulse width modulation signal supplied to the j-th modulation wiring is conventionally i-th row, j-th
The pulse width modulation signal according to the size of the image data of each pixel is supplied to all the modulation wirings, which is determined according to the size of the image data of the pixel of the column.

In the present invention, as will be described later, the pulse width of the pulse width modulation signal supplied to the j-th modulation wiring is the image to be displayed in order to correct the decrease in luminance due to the influence of the voltage drop. Is determined according to the size of the image data of the pixel at the i-th row and the j-th column and the correction amount thereof, and the pulse width modulation signal is supplied to all the modulation wirings.

In this embodiment, the voltage Vpwm is set to + 0.5VSEL.

(Regarding Voltage Drop in Scan Wiring) As described above, the fundamental problem faced by the image display device of the present invention is that the voltage drop in the scan wiring of the display panel causes
This is because the voltage applied to the SCE decreases due to the increase in the potential on the scanning wiring, and thus the emission current from the SCE decreases. The mechanism of this voltage drop will be described below.

Although depending on the design specifications and manufacturing method of the SCE, the device current for one device of the SCE is about several hundred μA when the voltage VSEL is applied.

Therefore, when only one pixel on the selected scanning line is made to emit light and the other pixels are not made to emit light in a certain horizontal scanning period, the element current flowing from the modulation wiring to the scanning wiring of the selected row is 1. Since it is only the current for the pixel (that is, the above-mentioned several 100 μA), there is almost no voltage drop, and the emission brightness does not decrease.

However, in the case where all the pixels in the selected row are made to emit light in a certain horizontal scanning period, the current for all the pixels flows from all the modulation wirings to the scanning wirings in the selected state. The sum is several hundred mA
The number was several A, and a voltage drop occurred on the scanning wiring due to the wiring resistance of the scanning wiring.

If a voltage drop occurs on the scan wiring, SC
The voltage applied across E decreases. Therefore SCE
The emission current emitted from the device was reduced, and as a result, the emission brightness was reduced.

Further, more complicatedly, the magnitude of the voltage drop has the property of changing within one horizontal scanning period by performing modulation by pulse width modulation.

The pulse width modulation signal supplied to each column is shown in FIG.
Consider a case where a pulse width modulated signal whose pulse width depends on the size of the data and whose rising edge is synchronized with respect to the input data is output as shown in FIG. In such a case, depending on the input image data, generally, within one horizontal scanning period, the number of lit pixels is large immediately after the rise of the pulse, and thereafter, the lit pixels are turned off in order from the lowest brightness. Therefore, the number of lit pixels decreases with time in one horizontal scanning period.

Therefore, the magnitude of the voltage drop generated on the scan wiring also tends to decrease gradually toward the beginning of one horizontal scanning period.

Since the output of the pulse width modulation signal changes at each time corresponding to one gradation of modulation, the temporal change of the voltage drop also changes at each time corresponding to one gradation of the pulse width modulation signal.

The voltage drop in the scan wiring has been described above.

(Calculation Method of Voltage Drop) Next, a method of correcting the influence of the voltage drop will be described in detail.

To obtain the correction amount for reducing the influence of the voltage drop, first of all, as the first step, hardware for predicting the magnitude of the voltage drop and its change over time in real time is required. A display panel of such an image display device is generally provided with thousands of modulation wirings, and it is very difficult to calculate the voltage drop at the intersection of all the modulation wirings and the scanning wirings. With
It is not realistic to make hardware that calculates it in real time.

Therefore, the voltage drop amount is calculated by blocking the position in the same row and also blocking in the size direction of the image data.

Such blocking is based on the following characteristics of the voltage drop.

I) At a certain point in one horizontal scanning period, the voltage drop generated on the scan wiring is a spatially continuous amount on the scan wiring, which is a very smooth curve.

Ii) Although the magnitude of the voltage drop varies depending on the display image, it changes at each time corresponding to one gradation of pulse width modulation, and is generally larger at the rising portion of the pulse, and gradually in time. It either becomes smaller or maintains its size.

That is, in the driving method as shown in FIG. 4, the magnitude of the voltage drop does not increase within one horizontal scanning period.

Specifically, the time change of the voltage drop was roughly predicted by calculating the voltage drop by the degeneration model described below for a plurality of times.

(Calculation of voltage drop by degenerate model) FIG. 5
(A) is a figure for demonstrating the block and node at the time of performing degeneration.

In FIG. 5, for simplification of the drawing, SCs connected to the selected scanning wiring, each modulation wiring, and their intersections.
Only E is listed.

Now, at a certain time in one horizontal scanning period, the lighting state of each pixel on the selected scanning wiring (that is, whether the output of the modulating means is "H" or "L"). ) Is known.

In this lighting state, the element current flowing from each modulation wiring to the selected scanning wiring is set to Ifi (i =
1, 2 ,. ． ． N and i are defined as column numbers).

Further, as shown in FIG. 5, a block is defined by grouping n modulation wirings, the intersections of the selected scanning wirings and the SCEs arranged at the intersections, as one group. In the present embodiment, the blocks are divided into four blocks.

A position called a node is set at the boundary position of each block. A node is a horizontal position (reference point) for discretely calculating the amount of voltage drop that occurs on the scan wiring in the degenerate model.

In the present embodiment, at the block boundary position,
Five nodes, node 0 to node 4, were set.

FIG. 5B is a diagram for explaining the degenerate model.

In the degenerate model, n modulation wirings included in one block in FIG. 5A are degenerated to one, and one degenerated modulation wiring is positioned at the center of the block of the scanning wirings. Connected to.

Further, a current source is connected to the modulation wiring of each degenerated block, and the sum total IF0 to IF3 of the current in each block flows from each current source.

[0075] That is, IFj (j = 0, 1, ... 3) is

[Equation 1] Is the current represented by (Equation 1).

Further, the potentials at both ends of the scanning wiring are shown in FIG.
5B, the GND potential is set in FIG. 5B. In the degenerate model, the current flowing into the scanning wiring selected from the modulation wiring is modeled by the current source, and This is because the voltage drop amount of each part can be calculated by calculating the voltage (potential difference) of each part using the power supply part as the reference (GND) potential (that is, defined as the reference potential for calculating the voltage drop). .).

Further, the SCE is omitted because, when viewed from the selected scan wiring, if an equivalent current flows from the column wiring, the generated voltage drop itself changes regardless of the presence or absence of SCE. Because there is no. Therefore, here, by setting the current value flowing from the current source of each block to the current value (Equation 1) of the sum of the element currents in each block, SCE
Was omitted.

Further, the wiring resistance of the scanning wiring of each block is set to n times the wiring resistance r of the scanning wiring in one section (here, one section is the intersection of the scanning wiring with a certain column wiring and its adjacent area. (This means the area between the column wiring and the intersection.) In the present embodiment, the wiring resistance of the scanning wiring in one section is assumed to be uniform.

In such a degenerate model, the voltage drop amounts DV0 to DV generated at each node on the scanning wiring.
4 can be easily calculated by the following product-sum formula.

[0080]

[Equation 2] Becomes

That is,

[Equation 3] Is established.

However, aij is a voltage generated at the i-th node when a unit current is injected into only the j-th block in the degenerate model (hereinafter, this is defined as aij).

The above aij is derived by Kirchhoff's law, and once calculated, it may be stored as a table.

Further, with respect to the total currents IF0 to IF3 of each block defined by the equation 1,

[Equation 4] The approximation shown in was performed.

However, in the above equation, Counti is a variable that takes 1 when the i-th pixel on the selected scanning line is in the on state and 0 when it is in the off state.

IFS is a voltage VSE across the SCE1 element.
0 to 1 for the device current IF that flows when L is applied
It is an amount multiplied by a coefficient α that takes a value between.

That is,

[Equation 5] Was defined.

Equation 2 assumes that an element current proportional to the number of lighting in each block flows into the selected scanning wiring from the column wiring of each block. At this time, the element current IF of one element is multiplied by the coefficient α to obtain the element current IFS of one element.
The reason is as follows.

Originally, in order to calculate the voltage drop amount, it is necessary to repeatedly calculate the voltage increase of the scanning wiring due to the voltage drop and the decrease amount of the device current due to it, but this convergence calculation is performed by hardware. It is not realistic to calculate.

Therefore, in the present invention, αIF is approximately used as the convergent value of IF.

Specifically, the rate of decrease in IF (= α1) when the amount of voltage drop is maximum (when all white) and the rate of decrease in IF when the amount of voltage drop is (minimum = 0). (= Α2)
Is estimated in advance and is calculated as the average value of α1 and α2 or 0.8 × α1.

FIG. 5C shows an example of the result of calculating the voltage drop amounts DV0 to DV4 of each node by the degeneration model in a certain lighting state.

Since the voltage drop has a very smooth curve, the voltage drop between nodes is approximately as shown in FIG.
It is assumed that the value shown by the dotted line in (c) is taken.

As described above, by using this degenerate model, it is possible to calculate the voltage drop at the position of the node at a desired time point with respect to the input image data.

As described above, the amount of voltage drop in a certain lighting state was simply calculated using the degenerate model.

The voltage drop generated on the selected scan wiring changes with time within one horizontal scanning period. As described above, with respect to some times during one horizontal scanning period, the voltage drop occurs at that time. The lighting state was calculated and the voltage drop was calculated using the degeneration model for the lighting state.

The number of lights in each block at a certain point in one horizontal scanning period can be easily obtained by referring to the image data of each block.

As an example, assume that the number of bits of input data to the pulse width modulation circuit is 8 bits, and the pulse width modulation circuit outputs a pulse width according to the size of the input data.

That is, when the input data is 0, the output is "L", when the input data is 255, "H" is output during one horizontal scanning period, and when the input data is 128, the one horizontal scanning period is output. It is assumed that "H" is output in the first half period and "L" is output in the second half period.

In such a case, the number of lights at the start time of the pulse width modulation signal (the rising time in the example of the modulation signal of this example) is counted when the input data to the pulse width modulation circuit is greater than 0. It can be easily detected.

Similarly, the number of lights at the central time of one horizontal scanning period can be easily detected by counting the number of input data to the pulse width modulation circuit which is larger than 128.

In this way, by comparing the image data with a certain threshold value and counting the number of true outputs of the comparator, the number of lightings at any time can be easily calculated.

Here, in order to simplify the following description, a time amount called a time slot is defined.

That is, the time slot represents the time from the rise of the pulse width modulation signal in one horizontal scanning period, and the time slot = 0 represents the time immediately after the start time of the pulse width modulation signal. Define as a thing.

The time slot = 64 is defined to represent the time when 64 gradations have elapsed from the start time of the pulse width modulation signal.

Similarly, time slot = 128 is defined as a time when 128 gradations have elapsed from the start time of the pulse width modulation signal.

In the present example, the pulse width modulation is based on the rising time as a reference, and the pulse width from the leading edge is modulated. However, similarly, when the pulse width is modulated based on the falling time of the pulse, However, it goes without saying that the same can be applied, although the advancing direction of the time axis is opposite to the advancing direction of the time slot.

(Calculation of Correction Data from Voltage Drop Amount) As described above, the time change of the voltage drop during one horizontal scanning period is approximately and discretely calculated by repeatedly performing the degeneracy model. I was able to.

FIG. 6 shows an example in which the voltage drop is repeatedly calculated for a certain image data, and the time change of the voltage drop in the scan wiring is calculated (the voltage drop shown here and its time change are , An example for one image data, and it is natural that the voltage drop for another image data has another change.

In FIG. 6, time slots = 0, 64, 12
The voltage drop at each time was calculated discretely by applying the degenerate model to each of the four time points of 8, 192.

In FIG. 6, the voltage drop amount at each node is connected by a dotted line, but the dotted line is shown to make the diagram easier to see, and the voltage drop calculated by this degenerate model is □, ○, ●. , Δ were calculated discretely at the positions of the nodes.

The present inventors examined a method of calculating correction data for correcting image data from the amount of voltage drop as the next step after the magnitude of voltage drop and its change over time can be calculated.

FIG. 7 is a graph in which the emission current emitted from the SCE in the lighting state is estimated when the voltage drop shown in FIG. 6 occurs on the selected scan wiring.

The vertical axis represents the amount of the emission current at each position for each time in percentage, with the magnitude of the emission current emitted when there is no voltage drop being 100%, and the horizontal axis represents the horizontal position. There is.

As shown in FIG. 7, at the horizontal position (reference point) of node 2, the emission current when time slot = 0 is Ie0, the emission current when time slot = 64 is Ie1, and time slot = 128. The emission current at the time is Ie2, and the emission current at the time slot of 192 is Ie3.

FIG. 7 is calculated from the graph of the voltage drop amount of FIG. 6 and the “driving voltage vs. emission current” of FIG. Specifically, it is a mechanical plot of the value of the emission current when a voltage obtained by subtracting the voltage drop amount from the voltage VSEL is applied.

Therefore, FIG. 7 means only the current emitted from the SCE in the lighting state, and the SCE in the non-lighting state does not emit the current.

A method for calculating correction data for correcting image data from the voltage drop amount will be described below.

(Correction Data Calculation Method) FIG. 8 (a),
(B), (c) is a figure for demonstrating the method of calculating the correction data of a voltage drop amount from the time change of the emission current of FIG. FIG. 8 is an example of calculating correction data for image data having a size of 64.

The emission amount of luminance is nothing but the emitted charge amount obtained by temporally integrating the emission current by the emission current pulse.
Therefore, in the following, when considering the variation of the brightness due to the voltage drop, the description will be given based on the amount of the emitted charges.

Now, assuming that the emission current when there is no influence of the voltage drop is IE and the time corresponding to one gradation of the pulse width modulation is Δt, the emission current pulse when the image data is 64 is emitted. The amount of emitted charge Q0 to be performed is obtained by multiplying the amplitude IE of the emitted current pulse by the pulse width (64 × Δt),

[Equation 6] Can be expressed as

However, in reality, a phenomenon occurs in which the emission current decreases due to the voltage drop on the scan wiring.

The amount of charge emitted by the emission current pulse considering the influence of the voltage drop can be approximately calculated as follows. That is, the emission currents of the time slots = 0 and 64 of the node 2 are Ie0 and Ie1, respectively. If the emission current between 0 and 64 is approximated to linearly change between Ie0 and Ie1, the emission during this period is approximated. The charge amount Q1 is shown in FIG.
The area of the trapezoid.

That is,

[Equation 7] Can be calculated as

Next, as shown in FIG. 8C, it is assumed that the influence of the voltage drop can be removed when the pulse width is extended by DC1 in order to correct the decrease in the emission current due to the voltage drop.

When the voltage drop is corrected and the pulse width is extended, the amount of emission current in each time slot may change. However, for simplification, here,
As shown in FIG. 8C, it is assumed that the emission current is Ie0 at time slot = 0 and the emission current at time slot = (64 + DC1) is Ie1.

Further, the emission current between the time slot 0 and the time slot (64 + DC1) is approximated to take a value on a line connecting the emission currents at two points with a straight line.

Then, the amount of emitted charge Q2 due to the corrected emission current pulse is

[Equation 8] Can be calculated as

If this is equal to Q0, then

[Equation 9] Becomes

If this is solved for DC1,

[Equation 10] Becomes

In this way, the correction data when the image data is 64 was calculated.

That is, the size of the position of node 2 is 64
For the image data of
The correction amount CData may be added by a = DC1.

Similarly, for the image data of size 192, the correction amount can be obtained for each of the three periods as shown in FIG.

When the pulse width is 0, of course, there is no influence of the voltage drop on the emission current, so the correction data is set to 0 and the correction data CData is added to the image data.
Is also 0.

It should be noted that, in this way, 0, 64, 128, 19
The reason why correction data is calculated for discrete image data as in 2 is to reduce the amount of calculation.

An example of discrete correction data for certain input data obtained by this method is shown in FIG.

In the figure, the horizontal axis corresponds to the horizontal display position, and the position of each node is described. The vertical axis represents the size of the correction data.

The discrete correction data is calculated for the positions of the nodes indicated by □, ○, ●, and Δ in the figure and the size of the image data Data (image data reference value = 0, 64, 128, 192). It is a thing.

(Interpolation Method of Discrete Correction Data) The correction data calculated discretely is discrete with respect to the position of each node, and does not give the correction data at any horizontal position (column wiring number). Absent. At the same time, it is correction data for image data having some predetermined reference image data size at each node position and does not give correction data according to the actual image data size. .

Therefore, the present inventors calculated the correction data suitable for the size of the input image data in each column wiring by interpolating the correction data calculated discretely.

FIG. 10B is a diagram showing a method of calculating the correction data corresponding to the image data Data in x located between the node n and the node n + 1.

As a premise, it is assumed that the correction data has already been discretely calculated at the positions Xn and Xn + 1 of the nodes n and n + 1.

The input image data Data has a value between the image data reference values Dk and Dk + 1.

Now, the discrete correction data for the reference value of the k-th image data of the node n is set to CData [k] [n].
The correction data CA of the pulse width Dk at the position x can be expressed as CData [k] [n] and CData.
Using the values of [k] [n + 1], the following can be calculated by linear approximation.

That is,

[Equation 11] Becomes

However, Xn and Xn + 1 are horizontal display positions of the nodes n and (n + 1), respectively, and are constants determined when the above-mentioned block is determined.

Further, the image data Dk + 1 at the position x
The correction data CB of can be calculated as follows.

That is,

[Equation 12] Becomes

By linearly approximating the correction data of CA and CB, the correction data CD for the image data Data at the position x can be calculated as follows.

That is,

[Equation 13] Becomes

As described above, in order to calculate the correction data suitable for the actual position and the size of the image data from the discrete correction data, the calculation can be easily performed by the method described in the expressions 9 to 11.

If the correction data calculated in this way is added to the image data to correct the image data and the pulse width modulation is performed according to the corrected image data (referred to as corrected image data), the conventional problem is solved. It is possible to reduce the influence of the voltage drop on the displayed image, and it is possible to improve the image quality.

The hardware for correction, which has been a problem from the beginning, can be reduced in size by introducing the approximation such as degeneracy described so far, so that the amount of calculation is very small. It had an excellent merit that it could be configured with hardware.

(Explanation of Functions of Entire System and Each Part) Next, the hardware of the image display device incorporating the correction data calculating means will be explained.

FIG. 11 is a block diagram showing an outline of the circuit configuration. In the figure, 1 is the display panel of FIG. 1, Dx1
˜DxM and Dx1 ′ to DxM ′ are voltage supply terminals of the scanning wiring of the display panel 1, Dy1 to DyN are voltage supply terminals of the modulation wiring of the display panel 1, and Hv is an accelerating voltage applied between the face plate and the rear plate. A high-voltage power supply terminal, Va a high-voltage power supply, 2 a scanning circuit, 3 a synchronization signal separation circuit, 4 a timing generation circuit, 7 an RGB conversion circuit for converting the YPbPr signal into RGB by the synchronization separation circuit 3, 23 Is a selector for switching between a television video signal and a computer video signal, 17 is an inverse γ processing section, 5 is a shift register for one line of image data, 6
Is a latch circuit for one line of image data, 8 is a pulse width modulation means for outputting a modulation signal to the modulation wiring of the display panel, 1
Reference numeral 2 is an adder, 14 is a correction data calculating means, 20 is a maximum value detecting means, and 21 is a gain calculating means.

In FIG. 11, R, G and B are RGB.
Parallel input video data, Ra, Ga, and Ba are RGB parallel video data subjected to an inverse γ conversion process described later,
Data is the image data parallel / serial converted by the data array converter 9, and CD is the correction data calculation means 1.
The correction data Dout calculated in 4 is the image data (corrected image data) corrected by adding the correction data to the image data by the adder.

(Synchronous Separation Circuit, Selector) The image display device according to the present embodiment has NTSC, PAL, SECAM,
It is possible to display a television signal such as an HDTV and a VGA output from a computer together.

In the HDTV system video signal, the sync separation circuit 3 first separates the sync signals Vsync and Hsync and supplies them to the timing generation circuit 4. The video signals separated by synchronization are supplied to the RGB conversion means. Inside the RGB conversion means, a YPbPr-to-RGB conversion circuit, a low-pass filter (not shown), an A / D converter, and the like are provided. The YPbPr is converted into a digital RGB signal, and the converted signal is sent to the selector 23. Is being supplied.

A video signal output from a computer such as VGA is A / D converted by an A / D converter (not shown),
It is supplied to the selector 23.

The selector 23 appropriately switches between the television signal and the computer signal and outputs the television signal and the computer signal based on which of the video signals the user wants to display.

(Timing Generation Circuit) The timing generation circuit 4 is a circuit which has a built-in PLL circuit, generates timing signals corresponding to various video formats, and generates operation timing signals for each section.

The timing signal generated by the timing generation circuit 4 is Tsft for controlling the operation timing of the shift register 5, the shift register 5 to the latch circuit 6
Control signal Dataalo for latching data to
d, pulse width modulation start signal Pwmstar of the modulation means 8
t, a clock Pwmclk for pulse width modulation, Tscan for controlling the operation of the scanning circuit 2, and the like.

(Scanning Circuit) As shown in FIG. 12, the scanning circuits 2 and 2'are arranged to sequentially scan the display panel row by row in one horizontal scanning period, so that the selection potential Vs is applied to the connection terminals Dx1 to DxM. Alternatively, it is a circuit which outputs the non-selection potential Vns.

The scanning circuits 2 and 2 ′ are circuits that perform scanning by sequentially switching the selected scanning wiring in every horizontal period in synchronization with the timing signal Tscan from the timing generation circuit 4.

Incidentally, Tscan is a timing signal group made up of a vertical synchronizing signal and a horizontal synchronizing signal.

The scanning circuits 2 and 2'are each composed of M switches and shift registers as shown in FIG. These switches are preferably composed of transistors or FETs.

In order to reduce the voltage drop in the scanning wiring, it is preferable that the scanning circuit is connected to both ends of the scanning wiring of the display panel 1 and driven from both ends, as shown in FIG.

On the other hand, the embodiment of the present invention is effective even when the scanning circuit is not connected to both ends of the scanning wiring, and can be applied only by changing the parameter.

(Inverse γ Processing Unit) The CRT has a light emission characteristic of approximately 2.2 to the input (hereinafter referred to as an inverse γ characteristic).

Such characteristics of the CRT are taken into consideration in the input video signal, and the input video signal is generally converted in accordance with the .gamma. Characteristic of the 0.45th power so as to have a linear emission characteristic when displayed on the CRT.

On the other hand, when the display panel of the image display device according to the embodiment of the present invention has a light emission characteristic which is almost linear with respect to the application time when the modulation is performed by the application time of the drive voltage, the input video signal Needs to be transformed based on the inverse γ characteristic (hereinafter referred to as the inverse γ transformation).

The inverse γ processing section 17 shown in FIG. 11 is a circuit for performing inverse γ conversion on the input video signal.

The inverse γ processing section 17 of this embodiment is configured by a memory for the inverse γ conversion processing.

The inverse γ processing unit 17 sets the number of bits of the video signals R, G, B to 8 bits, and the number of bits of the video signals Ra, Ga, Ba output from the inverse γ processing unit 17 is also 8 bits. It is configured by using a memory having an address of 8 bits and a data of 8 bits for each color (FIG. 13).

(Data Array Converter) Data Array Converter 9
Are Ra, Ga and Ba which are RGB parallel video signals.
Is a circuit for performing parallel / serial conversion according to the pixel arrangement of the display panel. As shown in FIG. 14, the configuration of the data array conversion unit 9 is a FIFO (Firm) for each RGB color.
stInFirstOut) memories 2021R, 202
1G, 2021B and a selector 2022.

Although not shown in FIG. 14, the FIFO memory includes two horizontal pixel memory words for odd lines and even lines. When the video data of the odd line is input, the data is written in the FIFO for the odd line, while the image data accumulated in the previous horizontal scanning period is read from the FIFO memory for the even line. When the video data of the even-numbered lines is input, the data is written in the FIFO for the even-numbered lines, while the image data accumulated in the previous horizontal period is read from the FIFO memory for the odd-numbered lines.

The data read from the FIFO memory is parallel-serial converted by the selector according to the pixel array of the display panel and output as RGB serial image data SData. Although not described in detail, it operates based on the timing control signal from the timing generation circuit 4.

(Delay Circuit 19) The image data SData rearranged by the data array converter 9 are input to the correction data calculator 14 and the delay circuit 19. The correction data interpolating unit of the correction data calculating means 14 which will be described later uses the horizontal position information x and the image data SDat from the timing control circuit.
The correction data CD suitable for them is calculated with reference to the value of a.

The delay circuit 19 is provided to absorb the time required for the correction data calculation (the above-mentioned correction data interpolation processing), and when the adder 12 adds the correction data CD to the image data Data. , A means for delaying so that the correction data CD corresponding to the image data Data is correctly added. The same means can be configured by using a flip-flop.

(Adder 12) The adder 12 receives the correction data CD and the image data Dat from the correction data calculating means 14.
It is a means for adding a. The image data Data is corrected by adding the corrected image data Dout.
Is transferred to the maximum value detection circuit 20 and the multiplier.

The number of bits of the corrected image data Dout output from the adder 12 is preferably determined so that overflow does not occur when the correction data is added to the image data.

More specifically, the image data Data is 8
It has a data width of bits, the maximum value is 255, the correction data CD has a data width of 7 bits, and the maximum value is 1
Suppose it was 20.

At this time, the maximum value of the addition result is 255 + 1
20 = 375.

On the other hand, the corrected image data Dout, which is the output of the adder 12, preferably has an output bit width of 9 bits so that overflow does not occur.

(Overflow processing (amplitude adjusting means))
In the present invention, the calculated correction data CD is used as the image data Da.
It has already been described that the correction is realized by the corrected image data Dout added to ta.

Now, the number of bits of the modulation means 8 is 8 bits, and the corrected image data Dou which is the output of the adder 12 is output.
It is assumed that the number of bits of t is 9 bits.

Then, if the corrected image data Dout is directly connected to the input of the modulation means 8, an overflow will occur.

That is, since data of 8 bits or more is folded back and modulated by the 8-bit modulating means, the image quality is remarkably deteriorated.

Therefore, it is necessary to adjust the amplitude of the corrected image data before it is input to the modulation means 8.

If the number of input bits of the modulation means 8 is increased,
Although overflow at the input of the modulation means 8 can be prevented, on the other hand, it is not possible to extend the pulse width of the pulse output from the modulation signal indefinitely.

That is, since the image display device of the present invention sequentially selects and drives the scanning wirings, the pulse width output from the modulation means 8 cannot extend the pulse beyond the assigned scanning time. .

Therefore, the upper limit of the input range of the modulating means 8 is the maximum input value determined by the number of bits of the modulating means 8 or the maximum pulse width capable of performing the modulation (that is, the time for selecting one row of scanning wiring). Is defined by the input data value corresponding to.

In the present embodiment, the upper limit of the input range of the modulation means 8 will be described below as an example in which it is defined by the maximum value of the input data of the modulation means 8.

As a structure for preventing overflow, an all-white pattern in which the input image data is maximum ((R, G, B) = (where the number of bits of image data is 8 bits)
The maximum value of the correction image data Dout when (FFh, FFh, FFh)) is input may be estimated in advance, and the correction image data Dout may be multiplied by a gain such that the maximum value falls within the input range of the modulation unit 8. Hereinafter, this method is called a fixed gain method.

In the fixed gain method, overflow does not occur, but an image with a low average luminance is multiplied by a small gain even though it can be displayed with a larger gain, so the luminance of the displayed image is dark. May be.

On the other hand, the maximum value of the corrected image data Dout for each frame is detected, and this maximum value is used as the modulation means 8.
The overflow may be prevented by calculating a gain that falls within the input range of 1 and multiplying the gain by the corrected image data Dout. Hereinafter, this method is called an adaptive gain method.

In the adaptive gain method, corrected image data Do
maximum value detecting means 20 for detecting the maximum value MAX of each frame of ut, and corrected image data Dou from the maximum value.
Gain calculating means 21 for calculating a gain G1 for multiplying t, and corrected image data Dout and gain G
A multiplier or the like for multiplying by 1 is required.

In the adaptive gain method, it is preferable to calculate the gain for preventing overflow in units of frames.

For example, a gain can be calculated for each horizontal line to prevent overflow, but in that case, a difference in gain for each horizontal line causes an uncomfortable feeling in the displayed image, which is not preferable.

The outline of the fixed gain method and the adaptive gain method has been described above.

The inventors of the present invention have confirmed that the amplitude of the corrected image data can be adjusted appropriately even if the gain is calculated by any method.

Therefore, in this embodiment, the amplitude is adjusted by the adaptive gain method.

Hereinafter, in the present embodiment, the circuit configuration as means for adjusting the amplitude of the corrected image data by the adaptive gain method will be described in detail.

(Maximum value detecting means (maximum value detecting section)) The maximum value detecting means 20 of the present invention is connected to each section as shown in FIG.

The maximum value detecting means 20 is means for detecting the maximum value in the corrected image data Dout for one frame.

The maximum value detecting means 20 is a circuit which can be easily constructed by a comparator and a register. The maximum value detecting means 20 compares the value stored in the register with the size of the correction image data Dout sequentially transferred. If the correction image data Dout is larger than the value of the register, the value of the register. Is a circuit for updating with the data value.

If the register value is cleared to 0 at the beginning of the frame, the maximum value of the corrected image data in the frame is stored in the register at the end of the frame.

The maximum value of the corrected image data Dout detected in this way is transferred to the gain calculating means 21.

(Gain Calculating Means (Gain Calculating Section)) The gain calculating means 21 sets the gain for adjusting the amplitude so that the corrected image data Dout falls within the input range of the modulating means 8 based on the adaptive gain method. It is a means of calculating.

As for the gain, the maximum value detected by the maximum value detecting means 20 is MAX, and the maximum value in the input range of the modulating means is INM.
If you say AX,

[Equation 14] It may be determined so that (1st method).

The gain calculating means 21 updates the gain during the vertical blanking period and changes the gain value for each frame.

In the structure of the image display device of the present invention,
The maximum value of the corrected image data of the previous frame is used to calculate the gain by which the corrected image data of the current frame is multiplied.

Therefore, strictly speaking, an overflow may occur due to the difference in the corrected image data for each frame.

To solve such a problem, a limiter means to be described later is provided for the output of the multiplier that multiplies the corrected image data and the gain, and the circuit is designed so that the output of the multiplier falls within the input range of the modulating means. I liked it. It can be considered that the overflow process is performed by utilizing the correlation of the corrected image data (image data) between adjacent frames.

If a frame memory is provided between the maximum value detection circuit and the multiplier, overflow can be prevented with a structure having no time delay.

Further, the present inventors have confirmed that the gain determination method of the adaptive gain method may calculate the gain by the following method.

That is, as the gain to be applied to the corrected image data of the current frame, the maximum value of the corrected image data detected in the frame before the current frame is smoothed (averaged) in the frame direction, and the average thereof is calculated. The gain G1 'for the value AMAX is

[Equation 15] It may be determined so that (2nd method).

As the third method, the current gain may be calculated by calculating the gain G1 for each frame by the equation 12 and averaging the gains.

Among the three methods, the present inventors have
Although it has been confirmed that all the methods are preferable, on the other hand, the second method and the third method have another effect that the flicker in the display image is greatly reduced compared to the first method, which is very effective. It is preferable (this will be described later with reference to FIGS. 15 to 17).

The present inventors examined the number of frames to be averaged with respect to the second method and the third method. For example, when 16 to 64 frames are averaged, there is little flicker. A favorable image was obtained.

In the case of the second and third methods as well, as in the first method, the (corrected) image data has a correlation between frames, so that the probability of occurrence of overflow can be reduced. However, it cannot completely prevent overflow.

As a countermeasure for this, it is more preferable that the overflow is roughly prevented by the above-mentioned method, and a limiter is provided at the output of the multiplier to completely prevent the overflow.

FIG. 15 is a diagram for explaining the flicker by taking the first method and the second method as an example.

FIG. 15 is an example of a moving image in which a white bar rotates counterclockwise in a gray background. When such an image is displayed, the size of the correction data CD changes for each frame as the rod rotates.

FIG. 16 is a diagram for explaining corrected image data when such a moving image is corrected. In FIG. 16, the maximum of each corrected image data in each frame is extracted and graphed.

The white portion in FIG. 16 corresponds to the original image data, and the gray portion corresponds to the portion expanded by the correction.

When an image as shown in FIG. 15 is displayed, the maximum value of the corrected image data of consecutive frames fluctuates as shown in FIG.

Therefore, if the gain is set for each frame as shown in Expression 12, the gain variation for each frame becomes severe as shown in FIG. 17A, and as a result, the luminance variation of the display image becomes intense. A flicker feeling occurs.

On the other hand, when the gain is determined by the expression 13, since the gain is averaged, the fluctuation of the gain becomes small and the fluctuation of the luminance becomes small as shown in FIG. There was an excellent effect that the feeling was reduced.

In FIG. 17 (b), the white circle graph is the gain according to equation 12, and the black circle graph is the averaged gain according to equation 13.

Although the third method has not been discussed in detail here, the present inventors have confirmed that flicker is reduced because the gain variation is reduced as in the second method.

Further, the gain calculating means 21 averages the gains for the screens of the continuous scenes as described above, but on the other hand, when the scene of the image is changed, the scene is changed. It was preferable to quickly change the gain.

On the other hand, the gain calculating means 21 sets a preset threshold value which is the scene switching threshold value Gth, and the gain of the previous frame calculated by the equation 12 is GB, and the maximum value of the previous frame is GB. From the maximum value of the corrected image data detected by the value detecting means 20, the gain calculated by Expression 12 is GN, and the absolute value of the difference between GN and GB is Δ.
If G,

[Equation 16] While computing as

[Equation 17] As a result, the gain of the next frame was smoothed and calculated, which was preferable.

Particularly, as the values of A and B, A = 1, B = 1/16 to 1/64 When I set it to a degree, I liked it.

The method of determining the scene switching and the method of calculating the gain are not limited to this, and may be detected by the configuration shown in the eighth embodiment described later.

(Multiplier) The gain G1 calculated by the gain calculating means 21 and the corrected image data Dout which is the output of the adder 12 are multiplied by the multiplier shown in FIG. 11 to obtain corrected image data Dmulti having the adjusted amplitude. Transferred to the limiter circuit.

(Limiter Means (Limiting Means)) There is no problem if the gain can be determined so that the overflow does not occur as described above. However, according to the several gain determination methods described above, the overflow does not occur always. Since it is difficult to determine the gain, the limiter (Lim
Iter) can be provided.

The limiter has a preset limit value and compares the output data Dmulti input to the limiter with the limit value. If the limit value is smaller than the output data, the limit value is output and the limit value is output. If the limit value is large, the output data is output (the signal name in FIG. 11 is the corrected image data Dlim).

The corrected image data Dlim completely limited to the input range of the modulating means 8 by the limiter means is supplied to the modulating means 8 via the shift register and the latch.

(Shift Register, Latch Circuit) The corrected image data Dlim, which is the output of the limiter circuit, is transferred by the shift register 5 from the serial data format to
The parallel image data ID1 to IDN for each modulation wiring are serial / parallel converted and output to the latch circuit 6. The latch circuit 6 latches the data from the shift register 5 by the timing signal Dataload immediately before the start of one horizontal period. The output of the latch circuit 6 is the modulation means 8 as parallel image data D1 to DN.
Is supplied to.

In this embodiment, image data ID1 to ID
Each of N and D1 to DN is 8-bit image data. These operation timings are the timing generation circuit 4
Timing control signals TSFT and Da from (FIG. 11)
It operates based on taload.

(Details of Modulating Means) The parallel image data D1 to DN output from the latch circuit 6 are supplied to the modulating means 8.

As shown in FIG. 18A, the modulation means 8 is a pulse width modulation circuit (PWM circuit) provided with a PWM counter, a comparator and a switch (FET in the figure) for each modulation wiring. .

The relationship between the image data D1 to DN and the output pulse width of the modulating means has a linear relationship as shown in FIG. 18 (b).

FIG. 18C shows three examples of output waveforms of the modulation means.

In FIG. 18 (c), the upper waveform is the waveform when the input data to the modulating means is 0, and the central waveform is
The waveform when the input data to the modulator is 128 and the lower waveform is the waveform when the input data to the modulator is 255.

In this example, the input data D to the modulation means is
The number of bits 1 to DN is 8 bits.

In the above description, when the input data of the modulation means is 255, there is a part that the modulation signal having the pulse width corresponding to one horizontal scanning period is output.
More specifically, as shown in FIG. 6C, a very short time is provided before the pulse rises and a slight period after the fall but is not driven to allow a timing margin.

FIG. 19 is a timing chart showing the operation of the modulation means of the present invention.

In FIG. 19, Hsync is a horizontal synchronizing signal, Dataload is a load signal to the latch circuit 6, and
D1 to DN are input signals to the columns 1 to N of the aforementioned modulation means,
Pwmstart is a PWM counter synchronization clear signal,
Pwmclk is the clock of the PWM counter. Further, XD1 to XDN represent outputs of the first to Nth columns of the modulation means.

As shown in FIG. 19, when one horizontal scanning period starts, the latch circuit 6 latches the image data and transfers the data to the modulation means 8.

The PWM counter, as shown in FIG.
Counting is started based on Pwmstart and Pwmclk, and when the count value reaches 255, the counter is stopped and the count value 255 is held.

The comparator provided for each column is
The count value of the PWM counter is compared with the image data of each column, and when the value of the PWM counter is greater than or equal to the image data, High
h is output, and Low is output during the other periods.

The output of the comparator is connected to the gates of the switches in each column, and the output of the comparator is Low.
During the period, the switch on the upper side (Vpwm side) in the figure is ON,
The lower (GND side) switch is turned off, and the modulation wiring is connected to the voltage Vpwm.

On the contrary, while the output of the comparator is High, the upper switch in the figure is turned off and the lower switch is turned on, and the voltage of the modulation wiring is connected to the GND potential.

The pulse width modulation signal output from the modulating means is D1 and D in FIG. 19 as a result of the operation of each section as described above.
2, a waveform in which the rising edges of the pulses are synchronized as shown by DN.

(Correction Data Calculation Means) The correction data calculation means 14 is a circuit for calculating the voltage drop correction data by the above-mentioned correction data calculation method. The correction data calculation means 14 is composed of two blocks, a discrete correction data calculation unit and a correction data interpolation unit, as shown in FIG.

The discrete correction data calculation unit calculates the voltage drop amount from the input video signal, and calculates the correction data discretely from the voltage drop amount. The discrete correction data calculation unit discretely calculates the correction data by introducing the concept of the degenerate model described above in order to reduce the calculation amount and the hardware amount.

The correction data calculated discretely is interpolated by the correction data interpolation section, and the correction data CD suitable for the size of the image data and its horizontal display position x is calculated.

(Discrete Correction Data Calculation Unit) FIG. 21 shows a discrete correction data calculation unit for calculating correction data discretely according to the present invention.

As will be described below, the discrete correction data calculation unit divides the image data into blocks, calculates a statistic (number of lights) for each block, and calculates the voltage drop amount at each node position from the statistic. A function as a voltage drop amount calculation unit that calculates a time change, a function that converts the voltage drop amount for each time into a light emission brightness amount, and a function that integrates the light emission brightness amount in the time direction to calculate a total light emission brightness amount. , And correction data for the reference values of the image data at discrete reference points.

In FIG. 21, 100a to 100d are lighting number counting means, 101a to 101d are a group of registers for storing the number of lighting at each time for each block, and 10
2 is a CPU, 103 is a table memory for storing the parameters aij described in Equations 2 and 3, 104 is a temporary register for temporarily storing the calculation result, 10
5 is a program memory in which the program of the CPU is stored, 111 is a table memory in which conversion data for converting the voltage drop amount into the emission current amount is described, and 106 is for storing the calculation result of the discrete correction data described above. Is a group of registers.

Lighting number counting means 100a to 100d
Is composed of a comparator and an adder as shown in FIG. Video signals Ra, Ga, Ba
Are respectively input to the comparators 107a to 107c and sequentially compared with the value of Cval.

Cval corresponds to the image data reference value set for the above-mentioned image data.

The comparators 107a to 107c compare Cval with the image data, and if the image data is larger, Hi.
gh is output, and Low is output if it is small.

The output of the comparator is the adders 108 and 1
09, they are added to each other, and addition is performed for each block by the adder 110, and the addition result for each block is set as the lighting number for each block in the register group 101
Store in a to d.

In the lighting number counting means 100a to 100d, 0, 64 and 1 are respectively set as the comparison value Cval of the comparator.
28 and 192 are input.

As a result, the lighting number counting means 100a
Counts the number of image data larger than 0 among the image data, and totals each block by the register 101a.
To store.

Similarly, the lighting number counting means 100b counts the number of image data larger than 64 among the image data, and the total for each block is registered in the register 101b.
To store.

Similarly, the lighting number counting means 100c counts the number of image data larger than 128 among the image data, and the total for each block is registered in the register 101.
Store in c.

Similarly, the lighting number counting means 100d counts the number of image data larger than 192 among the image data, and the total for each block is registered in the register 101.
Store in d.

When the number of lightings for each block is counted, the CPU reads the parameter table aij stored in the table memory 103 at any time, calculates the voltage drop amount according to the equations 2 to 4, and calculates the calculation result. It is stored in the temporary register 104.

In the present embodiment, the CPU is provided with the product-sum calculation function for smoothly performing the calculation of Expression 2.

As a means for realizing the operation shown in the equation (2), the product-sum operation may not be performed by the CPU, and for example, the calculation result may be stored in the memory.

That is, the number of lighting of each block may be used as an input and the voltage drop amount at each node position may be stored in the memory for all possible input patterns.

When the calculation of the voltage drop amount is completed, C
The PU reads the voltage drop amount for each block from the temporary register 104 at each time, and the table memory 2
With reference to (111), the amount of voltage drop was converted into the amount of emission current, and the discrete correction data was calculated according to Equations 5 to 8.

The calculated discrete correction data is stored in the register group 1
It was stored in 06.

(Correction Data Interpolation Section) The correction data interpolation section is means for calculating correction data corresponding to the position (horizontal position) where the image data is displayed and the size of the image data. This means interpolates the correction data calculated discretely to display the image data (horizontal position).
Also, correction data corresponding to the size of the image data is calculated.

FIG. 22 is a diagram for explaining the correction data interpolation unit.

In FIG. 22, the decoder 123 is a decoder for determining the node numbers n and n + 1 of the discrete correction data used for interpolation from the display position (horizontal position) x of the image data, and the decoder 124 is the image data. Is a decoder for determining k and k + 1 in Expressions 9 to 11 from the magnitude of

Further, the selectors 125 to 128 are selectors for selecting the discrete correction data and supplying it to the linear approximation means 120, 121.

Further, the linear approximation means 120 to 122 are the linear approximation means a to c for performing the linear approximations of the equations 9 to 11, respectively.

FIG. 23 shows a configuration example of the linear approximation means a.
Generally, the linear approximation means can be configured by a subtractor, an integrator, an adder, a divider, etc., as represented by the operators of Expressions 9 to 11.

However, preferably, the number of column wirings between the nodes for calculating the discrete correction data and the interval of the image data reference value for calculating the discrete correction data (that is, the time interval for calculating the voltage drop) is a power of two. There is a merit that the hardware can be configured very easily if it is configured as follows. If you set them to a power of 2,
In the divider shown in FIG. 3, Xn + 1-Xn becomes a power of 2 and bit shift is required.

If the value of Xn + 1-Xn is always a constant value and a value represented by a power of 2, it suffices to shift the addition result of the adder by the multiplier of the power and output it. There is no need to make a divider.

Also, by setting the intervals of the nodes for calculating the discrete correction data and the intervals of the image data to the powers of 2 at other locations, for example, the decoders 123 to 12 can be used.
4 can be easily manufactured, and FIG.
There are many advantages, such as the fact that the operation performed by the subtractor can be replaced with a simple bit operation.

(Operation Timing of Each Part) FIG. 24 shows a timing chart of the operation timing of each part.

In FIG. 24, Hsync is a horizontal synchronizing signal and DotCLK is a PL in the timing generation circuit.
A clock generated from the horizontal synchronizing signal Hsync by the L circuit, R, G, B are digital image data from the input switching circuit, Data is image data after data array conversion, Dlim is an output of the limiter means, and voltage drop correction Corrected image data, TSFT is a shift clock for transferring the corrected image data Dlim to the shift register 5, Dataload is a load pulse for latching data in the latch circuit 6, and Pwmstart is the start of the pulse width modulation described above. The signal and the modulation signal XD1 are examples of the pulse width modulation signal supplied to the modulation wiring 1.

With the start of one horizontal period, the selector 23
The digital image data RGB is transferred from. Figure 24
Then, when the input image data is represented by R_I, G_I, and B_I in the horizontal scanning period I, the image data is stored in the data array conversion circuit 9 for one horizontal period, and is displayed in the horizontal scanning period I + 1. The digital image data Data_I is output according to the pixel arrangement of the panel.

R_I, G_I and B_I are input to the correction data calculating means 14 in the horizontal scanning period I. The correction data calculation unit 14 counts the number of lightings described above, and calculates the voltage drop amount when the counting is completed.

Subsequent to the calculation of the voltage drop amount, the discrete correction data is calculated, and the calculation result is stored in the register.

In the scanning period I + 1, in synchronization with the output of the image data Data_I one horizontal scanning period before from the data array conversion unit, the correction data interpolating means interpolates the discrete correction data to calculate the correction data. To be done. The interpolated correction data is supplied to the adder 12.

The adder 12 sequentially adds the image data Data and the correction data CD and transfers the corrected correction image data Dlim to the shift register 5. The shift register 5 stores the corrected image data Dlim for one horizontal period according to TSFT, performs serial / parallel conversion, and outputs parallel image data ID1 to IDN to the latch circuit 6. The latch circuit 6 is Dataaloa
The parallel image data ID1 to IDN from the shift register 5 are latched according to the rising edge of d, and the latched image data D1 to DN are transferred to the pulse width modulation means 8.

The pulse width modulation means 8 outputs a pulse width modulation signal having a pulse width according to the latched image data. In the image display device of the present embodiment, as a result, the pulse width output by the modulator is displayed with a delay of two horizontal scanning periods with respect to the input image data.

When an image is displayed by such an image display device, the amount of voltage drop in the scanning wiring, which has been a problem in the past, can be corrected, and the deterioration of the displayed image due to it can be improved. It was possible to display a very good image.

Further, by introducing some approximations, the correction amount of the image data for correcting the voltage drop can be easily and suitably calculated, and this can be realized by very simple hardware. It had a very good effect.

(Second Embodiment) In the first embodiment, the maximum value of the corrected image data is detected, and the gain is adjusted so that the maximum value corresponds to the maximum value of the input range of the modulation means. The calculated value is multiplied by the corrected image data to prevent overflow.

On the other hand, in the second embodiment, the maximum value of the corrected image data is detected in the same manner, but the maximum value corresponds to the maximum value of the input range of the modulation means.
It was decided to limit the size of the image data before correction.

That is, in order to prevent overflow, the image data input in advance is multiplied by a gain to reduce its amplitude range, and overflow is prevented.

The overflow processing of this embodiment will be described below with reference to FIG.

In FIG. 25, 22R, 22G and 22B are multipliers, 9 is a data array converter, 5 is a shift register for one line of image data, 6 is a latch circuit for one line of image data, and 8 is a modulation of the display panel. Pulse width modulation means for outputting a modulation signal to the wiring, 12 is an adder, 14 is correction data calculation means, and 20 is correction image data Dou in the frame.
a maximum value detection circuit (means) for detecting the maximum value of t,
Reference numeral 21 is a gain calculating means.

Further, R, G, B are RGB parallel input video data, Ra, Ga, Ba are RGB parallel video data subjected to inverse γ conversion processing, and Rx, Gx, Bx are multipliers, and gain G2 is The multiplied image data, the gain G2 is the gain calculated by the gain calculation unit, Data is the image data subjected to parallel / serial conversion by the data array conversion unit 9, CD is the correction data calculated by the correction data calculation unit 14, and Dout. By adding the correction data CD to the image data Data by the adder 12,
Corrected image data (corrected image data), Dlim is corrected image data in which Dout is limited by the limiter to the upper limit of the input range of the modulation means or less.

(Multipliers 22R, 22G, 22B) Multipliers 22R, 22G, 22B are image data R after inverse γ conversion.
It is a means for multiplying a, Ga, and Ba by a gain G2.

More specifically, the multiplier is gain calculating means 2
The image data is multiplied by the gain G2 according to the gain determined by 1, and the multiplied image data Rx, Gx, Bx is output.

The gain G2 is a value calculated by the gain calculating means 21, and is the image data D in the adder 12 which will be described later.
The correction image data Dout, which is the addition result of ata and the correction data CD, is a value determined so as to be within the input range of the modulation unit 8.

(Maximum value detecting means (maximum value detecting section)) Next, the maximum value detecting means 20 will be described.

The maximum value detecting means 20 of the present invention is connected to each section as shown in FIG.

The maximum value detecting means 20 is a means for detecting the maximum value in the corrected image data Dout for one frame, and its configuration and operation are the same as those in the first embodiment. Maximum value MAX of detected corrected image data
Is transferred to the gain calculation means 21.

(Gain Calculating Means (Gain Calculating Section)) The gain calculating means 21 is a detection value MAX of the maximum value detecting means 20.
Is a means for calculating the gain so that the corrected image data Dout falls within the input range of the modulating means. Also in this embodiment, the gain calculating means 21 calculates the gain for adjusting the amplitude of the corrected image data based on the adaptive gain method.

On the other hand, as a method for calculating another gain,
In the configuration of this embodiment (FIG. 25), the gain may be calculated by the fixed gain method.

The gain determination method is as follows: MAX is the maximum value of the corrected image data Dout in one frame, INMAX is the maximum value of the input range of the modulator, and GB is the gain G2 calculated by the gain calculator for the previous frame. Then,

[Equation 18] It may be determined so that

The gain calculating means 21 updates the gain in the vertical blanking period to change the gain value for each frame.

In the structure of the image display device of this embodiment, the maximum value of the corrected image data of the previous frame is used to calculate the gain by which the corrected image data of the current frame is multiplied. (That is, it is configured to prevent overflow by utilizing the correlation of corrected image data (image data) between frames.)

Strictly speaking, therefore, overflow may occur due to the difference in corrected image data for each frame.

In order to solve such a problem, a limiter means is provided for the output of the multiplier that multiplies the corrected image data and the gain, and the circuit is designed so that the output of the multiplier always falls within the input range of the modulating means. It was even better.

Further, in order to obtain another effect of preventing flicker, the inventors of the present invention, as in the first embodiment, use the corrected image data detected in the frame before the current frame. The maximum value is averaged, and the average value AMAX
As opposed to

[Formula 19] May be determined to be However, GB is the gain G2 calculated by the gain calculation means for the immediately preceding frame.

As another method, the current gain may be calculated by calculating the gain G2 for each frame by the equation 14 and averaging the gain G2.

Among the three methods, we have
It has been confirmed that any method is preferable in terms of preventing overflow, but considering the occurrence of flicker as described in the first embodiment, it is preferable to calculate by averaging.

The present inventors examined the number of frames for averaging the maximum value of the corrected image data in the gain calculation method of the equation 15, but from the current frame, 16
When the maximum value of the corrected image data up to 64 frames before was averaged, it was preferable.

In this method, more preferably, as shown in FIG.
It goes without saying that it is preferable to provide a limiter for limiting the output of the adder to completely prevent the overflow, as shown in FIG.

Further, the method of calculating the gain may be changed by detecting the scene change as in the first embodiment.

(Third Embodiment) In the first embodiment, the reference value of the discrete image data is set for the input image data, and the reference point is set on the row wiring to set the reference value. The correction data for the image data having the size of the image data reference value at the point was calculated.

Further, by interpolating the correction data calculated discretely, the correction data corresponding to the horizontal display position of the input image data and its size is calculated, and the correction data is added to the image data by the adder. The correction was realized by.

On the other hand, the same correction can be performed with the configuration of FIG. The third embodiment will be described below with reference to FIG.

In FIG. 26, the difference from FIG. 11 is 14
The correction data calculating means and the adder 12 are deleted, and instead, a discrete correction image data calculating unit (means) 14a and a correction image data interpolating circuit (means) 14b are newly provided.

The flow of calculating the corrected image data of the image display device shown in FIG. 26 will be described below.

(1) Calculate discrete correction image data CDA (that is, the correction result which is the sum of the discrete correction data and the image data reference value) with respect to the discrete horizontal position and the image data reference value (discrete correction image). Data calculation part).

(2) The corrected image data calculated discretely is interpolated to obtain the size of the input image data Data,
Corrected image data corresponding to the horizontal display position x is calculated (corrected image data interpolation circuit).

(3) The maximum value of the interpolated corrected image data is detected (maximum value detection means), and the gain G1 is calculated so that it falls within the input range of the modulation means (gain calculation means). Calculated gain G1 and corrected image data Dou
Multiply t by (multiplier), and further limit the amplitude of the corrected image data by a limiter, and shift register, latch,
Input to the modulation means.

The method of calculating the discrete corrected image data CDA described in (1) can be easily calculated by modifying the conventional method of calculating discrete corrected data (Equations 5 to 8).

That is, the equations 5 to 8 are the equations for calculating the discrete correction data for the image data reference value = 0, 64, 128, 192, and the respective image data reference values are added to the discrete correction data. The added value may be used as the discrete corrected image data CDA.

In such a configuration, since the corrected image data in which the image data and the correction data are added is calculated at the stage of performing the calculation discretely, it is not necessary to add the image data and the correction data after the interpolation. Absent. Therefore, the adder 12 of FIG. 11 is no longer necessary.

The configuration of the corrected image data interpolation circuit is as follows.
It can be configured with the same configuration as the correction data interpolation unit of FIG. 22 described in the first embodiment.

As described above, even with such a configuration, the influence of the voltage drop can be suitably corrected, which is very preferable.

In this embodiment, the structure for preventing overflow of corrected image data is the structure of the first embodiment, but the structure is not particularly limited to this, and the second embodiment is used. It goes without saying that the configuration of the form may be adopted.

(Fourth Embodiment) In the third embodiment, a reference value of discrete image data is set for input image data, and a reference point is set on a row wiring. The corrected image data for the image data having the size of the image data reference value is calculated.

Further, the corrected image data calculated discretely is interpolated to calculate the corrected image data corresponding to the horizontal display position of the input image data and its size.

Further calculated corrected image data Dout
Is multiplied by the gain to obtain the corrected image data Do
The amplitude of ut is adjusted so as to correspond to the input range of the modulation means.

Further, the gain is calculated according to the equation 14 so that the maximum value of the corrected image data one frame before corresponds to the maximum value of the input range of the modulating means.

Further, the gain is calculated according to the equation 15 for the purpose of preventing the flicker feeling.

On the other hand, the same effect can be obtained with the configuration of FIG. The fourth embodiment will be described below with reference to FIG.

27 is different from FIG. 26 in that the discrete correction image data CDA is multiplied by the gain value calculated by the gain calculating means 21.

By multiplying the gain, the amplitude of the discrete corrected image data CDA is adjusted and output as the CDL to the corrected image data interpolation circuit 14b.

The corrected image data interpolating circuit 14b calculates the size of the input image data Data and the corrected image data Dout corresponding to the horizontal display position x based on the CDL which is the discrete corrected image data whose amplitude is adjusted. calculate.

At this time, the corrected image data interpolation circuit 1
This means that the output Dout of 4b has already been amplitude-adjusted so that it falls within the input range of the modulation means.

Strictly speaking, however, the gain G3 when multiplying the discrete corrected image data is

[Equation 20] Or for the purpose of preventing flicker

[Equation 21] Is determined by.

However, INMAX: maximum value MAX of input range of modulator: maximum value of corrected image data Dout for each frame AMAX: value obtained by averaging maximum value MAX for each frame GB: calculation of gain in previous frame It is the gain G3 calculated by the means.

Therefore, with the above configuration, the frequency of occurrence of overflow can be greatly reduced, but strictly speaking, overflow cannot be completely prevented.

Therefore, also in this embodiment, by providing a limiter between the corrected image data interpolating circuit 14b and the shift register 5 as shown in FIG. 27, the corrected image data having an amplitude range equal to the input range of the modulating means is obtained. When I created Dlim, I liked it.

The position where the limiter is provided may be the position shown in FIG. 27, but the position is not limited to this.

For example, without providing the limiter shown in FIG. 27, the same effect can be obtained by providing another limiter for limiting the discrete corrected image data CDL so that it is within the input range of the modulating means.

(Fifth Embodiment) In the first embodiment, the fixed gain method and the adaptive gain method have been described as the method of determining the gain.

The adaptive gain method is a method of detecting the maximum value of the corrected image data for each frame and adaptively calculating the gain so as not to overflow.

The adaptive gain method has the advantage that the display image can be brighter than the fixed gain method because the range is adaptively adjusted regardless of whether the image is a bright image or a dark image. Fluctuations in brightness may be observed due to such fluctuations in gain.

Then, as a result of further study by the inventors, the variation of the brightness due to the variation of the gain is not so noticeable when the television image is displayed, but the image output by the computer is displayed. When
It turned out to be very anxious.

For example, assume a window screen which is often seen in a video output from a computer.

As an example, green (8 bits, (R,
Consider a case where a white window (R, G, B) = (FFh, FFh, FFh) is displayed on the background of (G, B) = (0, FFh, 0)) (hereinafter referred to as display pattern 1).

In this case, the portion where the corrected image data becomes maximum in the frame is the portion where the white window is displayed.

On the other hand, when the white window is closed and only the green background is displayed (hereinafter, display pattern 2), the maximum value of the corrected image data is determined by the green background.

In the image display device of the present invention, since the maximum value of the corrected image data in the display pattern 1 is larger than that in the display pattern 2, the gain is "display pattern 1".
Gain "<" gain of display pattern 2 ".

Then, in the portion of the green background, the display pattern 2 is displayed more when the display pattern 1 is displayed.
Is darker than when is displayed.

When the display pattern 1 is switched to the display pattern 2 by a continuous operation, the brightness of the green background portion becomes brighter by closing the white window.

The discomfort due to such a variation in luminance can be made inconspicuous by the above-described gain averaging process. However, a video signal whose video signal level is flat in the screen such as a video signal of a computer. Then, it was not so preferable because the brightness fluctuated though it was very gentle.

Therefore, the present inventors calculate the gain by the fixed gain method when displaying the video signal of the computer, and calculate the gain by the adaptive gain method when displaying the television signal. I was very pleased.

FIG. 28 is a diagram showing the image display device of this embodiment.

In FIG. 28, the difference from the whole system diagram of the first embodiment (FIG. 11) is that the type signal SVS of the video signal selected from the selector 23 is supplied to the gain calculating means 21. is there.

Thus, the gain calculation means 21 determines that the video signal to be displayed is the video output of the computer,
The gain was calculated by the fixed gain method, and in the case of a television image, the gain G1 was calculated by the adaptive gain method.

FIG. 29 is a diagram for explaining the gain calculating means 21 of this embodiment.

In the gain calculating means 21, the gain is calculated by the adaptive gain method by the adaptive gain calculating circuit based on the maximum value of the corrected image data detected by the maximum value detecting means 20. The calculated gain GD is supplied to the selector.

The gain GS of the fixed gain method is also supplied to the selector.

The selector refers to the video classification signal SVS, and when the video signal to be displayed is a television signal, the output G1 of the selector is the gain GD by the adaptive gain method and the computer video signal. , The gain GS of the fixed gain method is selected.

In this embodiment, the fixed gain method is used when displaying the computer video signal, and the adaptive gain method is used when displaying the television video signal. For example, the user may select which mode to set by using an interface such as a remote controller.

Also, a video input terminal for a computer,
An image input terminal for a television may be provided, and the mode may be switched automatically based on which image is currently displayed.

As a mode for selecting the display quality of the image display device, when it is desired to display a bright screen by prioritizing the peak brightness, the adaptive gain method is selected, and when the screen fidelity is prioritized over the peak brightness. Alternatively, the fixed gain method may be selected.

Thus, when displaying a television video signal, the gain is calculated by the adaptive gain method,
When displaying the video signal of the computer, by calculating the gain by the fixed gain method, it is possible to display a bright screen when displaying the television video signal, and also when displaying the video signal from the computer. , It was possible to display a favorable image without any discomfort.

In this embodiment, as shown in FIG. 28, the structure of the first embodiment is adopted as the structure for preventing the overflow of the corrected image data, but it is particularly limited to this. It will not be done.

That is, the same effect can be obtained even with the configuration shown in the second embodiment (FIG. 25) for adjusting the amplitude range of input image data.

The same effect can be obtained even with the configuration in which the amplitude range of the discrete corrected image data is adjusted as in the fourth embodiment (FIG. 27).

(Sixth Embodiment) In the fifth embodiment, when the computer video signal is displayed, the gain is determined by the fixed gain method, and when the television video signal is displayed, the adaptive gain method is used. The gain had been determined (Fig. 29).

In the sixth embodiment, the gain calculating circuit 21 shown in FIG. 29 is more preferable when it is constructed as shown in FIG. 30 (a).

In FIG. 30A, the adaptive gain calculating circuit calculates the adaptive gain GD by referring to the maximum value MAX of the corrected image data from the maximum value detecting means 20.
The calculated gain GD is input to the limiter.

The limiter is a circuit that limits the gain GD according to the limit value output by the limiter register and outputs the gain GD.

A plurality of limit values are stored in the limiter register.

Which of the plurality of limit values is to be output depends on the video type signal SVS and the dynamic mode / low power mode switching signal S shown in FIG.
Determined by MODE.

In this embodiment, it is preferable to set the relationship between a plurality of limiter values as follows.

Dynamic mode> Low power mode> Computer mode FIG. 30B shows the input / output characteristics of the limiter with respect to the limiter value thus determined.

As shown in FIG. 30B, since the limiter limit value is set to a very large value in the dynamic mode, the limiter output is the adaptive gain G.
Is equal to D.

On the other hand, in the low power mode, the output of the limiter is the same as the adaptive gain GD in the range where the adaptive gain GD is small, but is limited by the limiter when the gain becomes large. As a result, when the input image data is bright, the gain is calculated by the adaptive gain method, and when the input image data is dark, the gain is calculated by the fixed gain method. I was able to display the image faithfully so that I liked it.

Further, when the limit value was selected so that the output of the limiter would be the limit value in the computer mode in the computer mode, it was possible to display a suitable image without the above-mentioned discomfort.

In the present embodiment, the limiter is applied after the gain GD is calculated by the adaptive gain method, but it is not particularly limited to this, and it is an input to the adaptive gain calculation circuit, for example. It goes without saying that even if the minimum value defining means for defining the minimum value of the corrected image data is provided, the same effect can be obtained as a result.

Further, as the configuration of the present embodiment, the configuration for adjusting the amplitude range of the corrected image data is as follows.
The first embodiment (FIG. 11) and the second embodiment (FIG. 2)
Any of the configurations of 5) and the fourth embodiment (FIG. 27) is suitable.

(Seventh Embodiment) In the first embodiment, the correction image data is multiplied by a gain to limit the amplitude range as a structure for preventing overflow of the correction image data. .

Further, it has been described that the upper limit of the amplitude range of the corrected image data whose amplitude is adjusted is limited by the input upper limit value of the modulating means, thereby completely limiting the amplitude range.

On the other hand, as a structure for preventing the overflow and suitably performing the correction, the upper limit of the amplitude range of the corrected image data is simply limited by the input upper limit value of the modulation means without multiplying the corrected image data by the gain. It is also suitable to do just that.

Further, in the second embodiment, as a structure for preventing overflow of corrected image data, the image data before correction is multiplied by a gain to limit its amplitude range, and the gain is multiplied. Image data,
The configuration has been described in which the corrected image data is calculated, and the gain is calculated so that the upper limit value of the amplitude of the corrected image data corresponds to the input upper limit value of the modulator.

On the other hand, as another configuration for appropriately performing the correction while preventing the overflow, the image data before the correction is limited, and the corrected image data is calculated for the limited image data. It is preferable to adjust the limit value of the limiter so that the calculated corrected image data does not overflow the input range of the modulator.

(Eighth Embodiment) In this embodiment,
The configuration is based on the overflow processing described in the first embodiment and improved. FIG. 31 is a block diagram showing a schematic configuration of the image display device according to the eighth embodiment.

The overflow processing method of this embodiment is not limited to the first embodiment, but can be applied to other embodiments.

In this embodiment, the maximum value detecting means 20 for detecting the maximum value of the corrected image data for each frame and the maximum value of the corrected image data for each frame which is the output of the maximum value detecting means 20 are input. Filter means 40 for blocking high frequencies (suppressing large fluctuations in maximum value between frames);
A frame is calculated by a gain calculation unit 21 that receives the output of the filter unit 40 and calculates a gain such that the output of the adder 12 falls within the input range of the modulation unit, and a multiplier that multiplies the calculated gain and the output of the adder. Overflow is prevented by calculating the gain for each.

At this time, a feature amount calculating means 60 as described below is provided as means for detecting that the scene of the display image has changed.

Further, based on the discrimination result of the characteristic amount calculating means (scene switching discriminating unit) 60, a preferable display can be performed by operating the filter as described below.

(Characteristic Amount Calculation Means (Scene Switching Discrimination Unit)) The characteristic amount calculation means 60 of the present embodiment is connected to each unit as shown in FIG.

The characteristic amount calculating means 60 is a means for calculating the average luminance level (APL) of the image data for one frame and further calculating the absolute value by taking the difference between the frames.

The average brightness level (APL) calculation is a circuit that can be configured by an adder and a register. In the calculation of the average brightness level (APL), the value stored in the register and the image data sequentially transferred are added and stored in the register again. Then, the input image data is sequentially added.

If the register value is cleared to 0 at the beginning of the frame, the added value of the image data in the frame at the end of the frame (since the number of pixels in one frame is fixed, a value proportional to the average value) Is required. This value becomes the average brightness level (APL). In the present embodiment, the maximum value of the average brightness level (APL) is 255.

Next, the average luminance level between frames (AP
L) is calculated, and the absolute value is calculated.

Then, the characteristic amount calculating means 60 outputs the absolute value of the difference between the average luminance levels (APL) between the frames.

(Filtering Means) The filtering means 40 of the present embodiment, as shown in FIG. 31, has a maximum value detecting means 20.
And the output of the feature amount calculation means 60 are input, and the processing described later is performed and output to the gain calculation means 21.

The detailed structure of the filter means 40 is shown in FIG.

In FIG. 32, 41 and 42 are multipliers and 4
3 is an adder, 44 is a latch circuit corresponding to a delay element of a digital filter, 45, 46 and 53 are coefficient registers,
Reference numeral 51 is a switch, and 52 is a comparator.

The operation of the filter means 40 having the above structure will be described.

(1) If the output (the absolute value of the APL inter-frame difference) of the feature amount calculation means 60 input to the comparator 52 is less than or equal to the value of the coefficient register 53, the switch 51
The output of the comparator 52 is used as the output of the adder 4
3 is selected, and the output of the adder 43 becomes the output of the filter means 40 and the output to the latch 44.

In this case, the coefficient registers 45 and 46, the multipliers 41 and 42, the adder 43, and the latch circuit 44 form a recursive digital filter.

That is, the maximum value of the current corrected image data is multiplied by the coefficient 1 / a stored in the coefficient register 45 by the multiplier 41.

On the other hand, the output of the filter means 40 one frame before is stored in the latch circuit 44, and the coefficient (1-1 / a) stored in the coefficient register 46 is multiplied by the multiplier 42.

The adder 43 adds the two multiplication results.

The present inventor has realized a low-pass filter by using the filter means described above with a = 64.

The coefficient registers 45 and 46 do not have to have the above values, but may have any value as long as a low pass filter can be formed. When configured with the values described above, the natural number a of the multiplication coefficient handled by the multipliers 41 and 42 is n (n = 2).
Is a natural number), the equivalent calculation can be realized by hardware by bit shift and subtraction, and the circuit scale can be reduced.

(2) When the output (the absolute value of the APL inter-frame difference) of the feature amount calculation means 60 input to the comparator 52 is larger than the value of the coefficient register 53 (when it is determined that the scene has changed, which will be described later). The input of the filter means 40 is selected by the output of the comparator 52 as the output of the switch 51, and the input of the filter means 40 becomes the output of the filter means 40 and the latch circuit 44.
Output to.

That is, the filter means 40 outputs the maximum value of the corrected image data input to the filter means 40 as it is.

The contents of the latch circuit 44 are replaced with the maximum value of the corrected image data.

The above operation is performed.

(Another Embodiment of Filter Means) Another embodiment of the filter means 40 of this embodiment will be described below.

Another embodiment of the filter means 40 is shown in FIG.
3 shows.

In FIG. 33, 41a, 41b, 41c,
41d and 41e are multipliers, 43a is an adder, 44a and 4
4b, 44c and 44d are latch circuits corresponding to delay elements of the digital filter, and 45a, 45b, 45c and 45.
Reference numerals d, 45e and 53 are coefficient registers, and 52 is a comparator.

The operation of another embodiment of the filter means 40 will be described with reference to FIG.

(1) When the output (the absolute value of the difference between the APL frames) of the feature amount calculating means 60 input to the comparator 52 is less than or equal to the value of the coefficient register 53, the comparator 52 does not output and the multiplier 41a, 41b, 41c, 41
d, 41e and coefficient registers 45a, 45b, 45c,
45d and 45e, an adder 43a, and a latch circuit 44
Reference characters a, 44b, 44c and 44d constitute a non-recursive digital filter.

In the above description, an example of a filter with a small number of delay elements (a small number of taps) is shown for the sake of description, but in practice, a filter with about 16 to 128 taps, preferably about 30 to 90 taps was visually good. Similarly to the recursive digital filter described in FIG. 32, the digital filter in FIG. 33 also has coefficient registers 45a, 45b, 45c, 4
As the values of 5d and 45e, those having a low-pass characteristic were used.

(2) When the output (the absolute value of the APL inter-frame difference) of the feature amount calculation means 60 input to the comparator 52 is larger than the value of the coefficient register 53 (when it is determined that the scene has changed, which will be described later). The comparator 52 outputs the load pulse (Ld) of the latch circuits 44a, 44b, 44c and 44d which are delay elements of the digital filter.

Then, the latch circuits 44a, 44b, 44
Replace the contents of c and 44d with the input data. Then, the maximum value of the corrected image data input to the filter means 40 is output as it is.

Then, an operation equivalent to that of the digital filter circuit shown in FIG. 32 is performed (coefficient registers 45a and 45).
The sum of b, 45c, 45d and 45e is selected to be 1. ).

(Gain Calculating Means (Gain Calculating Section)) The gain calculating means 21 is a means for calculating the gain so that the corrected image data Dout falls within the input range of the modulating means.

In this embodiment, the gain is the filter means 4
If the output of 0 is MAX 'and the constant is Kf1,

[Equation 22] Was calculated to be good.

The above expression shows that even if a slight overflow occurs, it is possible to display brightly in a natural image when the gain is increased so that it looks subjectively beautiful.

In the present embodiment, the present inventors determined that Kf1 = 1, and were able to obtain a good image.

Also in this embodiment, the gain value is changed for each frame.

In the present embodiment, since a filter for suppressing the fluctuation of the gain on a frame-by-frame basis is provided, an overflow may occur in a strict sense.

To address such a problem, a limiter means to be described later is provided for the output of the multiplier that multiplies the corrected image data and the gain, and the circuit is designed so that the output of the multiplier falls within the input range of the modulating means.

(Operation of Overflow Process) (1) Reduction of Flicker When performing the overflow process, the brightness can be increased in frame units as described above.

If the filter means 40 is not provided, the following disturbing feeling (flicker) may occur.

For example, as an easy-to-understand example, consider a scene in which the reflected light of the sun is glittering due to ripples in the lower half sea in an image such as the lower half sea.

In this case, the maximum value of the corrected image data changes little by little in correspondence with the portion where the reflected light of the sun shines due to the swell of the waves. As described above, when the gain is determined on a frame-by-frame basis, the gain changes little by little on a frame-by-frame basis. Flicker) occurs.

In the configuration shown in this embodiment, when the overflow processing is performed, the high frequency region is removed by the filter means 40, and the change of the maximum corrected image data is made gentle.

Therefore, even in the image in which the maximum value of the corrected image data changes in small increments as described above, the gain is changed gently, and the brightness can be increased without generating the disturbing feeling.

As described above, in order to remove the flicker, a low-pass filter that removes small changes in the maximum corrected image data is used. However, if the cutoff frequency is lowered too much, the gain that actually follows is desired. It will not change.

Therefore, as a result of confirmation by the present inventors, in the above-described recursive filter of FIG. 32, a = 128
Alternatively, a = 64, a = 32, or a = 16 was good. In particular, a = 64 or a = 32 was the optimum result of the subjective evaluation. In the non-recursive filter shown in FIG. 33, about 16 to 128 taps were good, and particularly 30 to 90 taps were subjectively good.

FIG. 34 shows a graph of the frame number of the actual image data versus the maximum value of the corrected image data (maximum corrected image data). In addition, the frame number of the same image versus the output of the filter means 40 of the present invention (in the recursive filter of FIG.
= 64 hours) is shown in FIG. As can be seen from both graphs, it can be seen that the small fluctuations in gain are suppressed. FIG. 35 shows an example in which the value of the coefficient register 53 is large (for example, the absolute value is equal to 255) and the scene change is not performed for the sake of simplicity.

(2) Reduction of discomfort due to scene change In the above-mentioned image, it is possible to eliminate the flicker.

However, when an image moves from one scene to the next (scene change), a disturbing feeling may occur.

Specifically, a case where a bright scene such as a white beach is changed to a dark scene such as a night sky will be described.

In the white sandy beach scene, the image data is large, and as described above, the corrected image data is also a large value.
Therefore, the gain has a small value.

Immediately after changing to a dark scene such as the night sky, the image data is small and the corrected image data is also a small value (large gain) as described above. However, since the low-pass filter is applied to the corrected image data by the filter means 40, the filter means 40
Has a larger value than the current maximum corrected image data, and the gain has a smaller value.

After that, the gain changes to a large value over time (several seconds).

Therefore, immediately after changing to a dark scene such as the night sky, the image is very dark and is displayed brighter in a few seconds, which gives a feeling of strangeness to the person viewing the image.

In order to eliminate the above-mentioned discomfort, in the present embodiment, the characteristic of the low-pass filter of the above-mentioned filter means 40 is that the output of the characteristic amount calculation means 60 (the absolute value of the APL inter-frame difference) is the coefficient register 53. If it is larger than the value of, the maximum corrected image data input to the filter means 40 is output as it is. The contents of the latch circuit 44 are replaced with the maximum corrected image data.

As the actual value of the coefficient register 53, 20 to 5 are output when the maximum value of the output of the feature amount calculation means 60 (the absolute value of the difference between the APL frames) is 255 (when the maximum value of the APL is 255). Was optimal, especially a value of 10.

That is, the difference between APL frames is 10
In the above cases, it was considered as a scene change and the contents of the delay element of the low-pass filter were changed to the input data to improve the gain followability.

The frame number of the image shown in FIG. 34 vs. AP
A graph of the L value is shown in FIG. FIG. 37 shows a graph of the frame number versus the output of the filter means 40 (a = 64 in the recursive filter of FIG. 32) when the value of the coefficient register 53 is 10. In both figures, the input image is a moving image having a different scene for each 240 frames. As can be seen from FIG. 37, when the scene is changed, the output of the filter means changes with good followability and flicker is suppressed. The image actually displayed was also good with no flicker disturbance or discomfort when changing scenes.

Here, the data before the inverse gamma conversion of the input image data is input to the characteristic amount calculating means 60, but the output of the inverse gamma processing section is input to the characteristic amount calculating means 60, and the average luminance level (APL). The same effect was obtained by calculating the difference between frames.

(Ninth Embodiment) As a ninth embodiment of the present invention, a configuration shown in FIG. 38 will be described.

In the eighth embodiment, the filter means 40 is provided for the output of the maximum value detection means 20, and the gain is calculated for the output value of the filter means 40. In the form, the maximum value detecting means 2
The gain calculation unit 21 calculates the gain from the output of 0, and the filter unit 40 is provided for the calculated gain.

That is, the filter means 40 is so constructed as to carry out a process for suppressing a variation in gain. By making the other respective configurations and the configuration of the filter means 40 similar to those of the eighth embodiment, it is possible to display suitable corrected image data.

(Tenth Embodiment) In the tenth embodiment, the connection is made as shown in FIG. 39, and the feature amount calculating means 60 is arranged between the APL frames of the input image data in units of one frame. Both the absolute value of the difference and the absolute value of the inter-frame difference of the maximum value MAX of the corrected image data are calculated.

In the filter means 40, as shown in FIG. 40, a comparator 52a and a coefficient register 53a, MA for judging the absolute value of the inter-frame difference of the APL.
A comparator 52b for judging the absolute value of the inter-frame difference of X, a coefficient register 53b, and a judgment means 54 for referring to the two judgment results are prepared. In the present embodiment, the determination means 54 is an OR circuit. The other configurations are the same as those in the above embodiments.

When only the inter-frame difference of APL is treated as the feature amount, for example, a screen in which a white solid horizontal line is displayed in 1/3 of a black screen (MAX becomes large)
From the screen (MAX
Becomes smaller) (when both APL values are the same), it is not judged as a scene change, and a feeling of strangeness appears for several seconds. In this embodiment, the MA is also used in this case.
It was determined that there was a scene change by the determination of the difference between X frames, and a good image could be obtained.

Also in the present embodiment, the same effect can be obtained by handling the output of the inverse gamma processing unit when calculating the absolute value of the APL interframe difference.

(Eleventh Embodiment) The image display apparatus of the present invention has been described above based on some embodiments.

On the other hand, as a problem common to all the above-mentioned embodiments, the following problem may occur depending on the quality of the input image.

Noise is added to the input image data, and when the input image data containing the noise is corrected, noise is added to the corrected image data calculated as a result of the correction. In some cases, the noise fluctuates the gain on a frame-by-frame basis and the brightness of the displayed image flickers (flicker occurs).

As a result of examination by the present inventors, such noise is caused by 1) the peripheral part of the image created by the broadcasting station, 2) the peripheral part of the image created by performing the scaler, and 3) the interlaced signal. It is known that a large amount of the image is generated in the peripheral portion of the output image of the I / P converter that converts the signal into a progressive signal, especially in the image data of several horizontal scanning lines above and below the image.

Images 1) to 3) are examples, but in these cases, it has been found that a lot of noise is generated at a specific position in the peripheral portion of the image. Then, this noise changes the gain and gives a displayed image a disturbing feeling.

The causes of images 1) to 3) often occur when the original image is converted. That is, when the original image is filtered and a new image is generated, the peripheral portion (particularly the edge portion) of the image must be processed without the original image at the input of the filter calculation. Therefore, the peripheral part of the image (especially the edge part) may be affected by the difference in processing corresponding to the missing data
In many cases, the value of the image data is deteriorated (noise is generated).

Particularly, the output image of the I / P converter of 3) is
Since the original image to be filtered by the odd field and the even field is shifted by one horizontal line, the values of the upper and lower horizontal line image data of the image change in the field unit of the original image, that is, in the frame unit after I / P conversion.

In the case of 3), when the corrected image data for noise is detected as the maximum value by the maximum value detecting means 20, the noise changes in frame units,
The gain fluctuates on a frame-by-frame basis and the brightness of the displayed image flickers (flicker).

As an example, the maximum value when a certain output image from an I / P converter that converts an interlaced signal into a progressive signal is corrected when there is no range selecting means 400 of the present invention described later. The output from the detection means 20 is shown in FIG.

The maximum corrected image data of certain continuous input image data greatly changes for each frame. This means that the gain significantly changes for each frame and appears as flicker in the output image.

As described above, the noise that causes this may appear in the peripheral portion (especially the edge portion) of the image when the original image is filtered and a new image is generated.

Therefore, the present inventors have provided the range selection means 400 shown below. In FIG. 42, 400 is a range selection means, and 20 is a maximum value detection means.

The overflow processing of this embodiment has been described by taking the configuration of the first embodiment as an example.
It goes without saying that the present invention can also be applied to the overflow processing form of the other embodiments.

The range selecting means 400 can be constructed, for example, as shown in FIG. 43, and 401, 402, 403 and 404 are registers A1, A2, B1 and B2, respectively. 40
5, 406, 407, and 408 are comparators A, respectively.
1, A2, B1 and B2. 409 is a decoder, 41
Reference numeral 0 is a switch and 411 is a register C.

The register A1 (401) stores the minimum value of the vertical range of the corrected image data to be detected as the maximum value, and the comparator A1 (405) outputs Dout.
The input value Y which is the vertical position information is compared and the selection signal is generated when Y is larger.

On the other hand, the maximum value of the vertical range of the corrected image data to be detected as the maximum value is stored in the register A2 (402), and the maximum value of the vertical range of the corrected image data is stored by the comparator A2 (406).
The input value Y, which is vertical position information of out, is compared, and when Y is smaller, a selection signal is generated.

Further, the register B and the comparator B are a selection unit for the horizontal position and have the same configuration as the register A and the comparator A.

From these selection signals, the decoder 409 composed of an AND circuit or the like generates a selection signal when the corrected image data within the range to be detected is input to the switch 410 as Dout. Register C (41
For example, 0 is stored in 1), and the switch 410
Passes through Dout when the selection signal is generated,
When not occurring, 0 is output.

Specifically, the range in which the maximum value of the corrected image data is detected is selected as a range in which the above-mentioned noise can be sufficiently removed and the characteristics of the display image can be taken in. For example, the upper and lower edges of the display area are selected. From the department, 1
It is preferable to select the corrected image data for the central row wirings other than the corrected image data for the number of row wirings equal to or larger than 1 and equal to or less than 1/10 of the total number of row wirings.

Particularly, when inputting the output image of the I / P converter of 3), the selecting means sets the number of wirings in all rows to 768, and outputs the number of horizontal lines of the image (one to ten or less). It is also effective to set 0 to 0.

FIG. 44 shows the output of the maximum value detecting means 20 when the image data shown in FIG. 41 is input using the range selecting means 400.

From FIG. 44, it can be seen that the large variation (that is, gain variation) of the maximum corrected image data for each frame has disappeared. As described above, the occurrence of flicker in the displayed image can be prevented.

Further, as another embodiment, the same effect can be obtained even if the range selecting means 400 is configured as shown in FIG. 45, for example. In FIG. 45, 412 is a multiplier, 41
3 is a memory. The memory 413 stores a weight for making the corrected image data that is not desired to be detected as the maximum value a small value as an address at the position of the corrected image data, and outputs the input corrected image data and the output from the memory 413. Are sequentially multiplied by a multiplier 412 to obtain an output. For example, when it is not desired to detect the corrected image data near the upper and lower ends as the maximum value, the upper and lower ends as shown in FIG.
It suffices to store a smooth convex weight having a central portion of 1 in the memory 413.

Since there are many images with noise as described above, such as I / P converted images outside the image display device, the above-described configuration makes it possible to reduce fluctuations in the maximum corrected image data due to noises, that is, gain fluctuations. It has become possible to suppress to.

(Twelfth Embodiment) As the twelfth embodiment of the present invention, as shown in FIG. 47, the same applies to a configuration in which range selection means 400 is provided for the output of correction data calculation means 14. The effect of was obtained.

In FIG. 47, 14 is a correction data calculating means and 400 is a range selecting means. In this case, the correction data is not added to the input data at the position that is not desired to be detected as the maximum value, or the correction data is not selected by the range selection means 400 so that the correction data is weighted and added. Alternatively, processing such as weighting is performed. By making the other respective configurations similar to those of the eleventh embodiment, it was possible to display suitable corrected image data.

(Thirteenth Embodiment) As the thirteenth embodiment of the present invention, the configuration shown in FIG. 48 will be described. 20 is a maximum value detecting means, 21 is a gain calculating means, 2
2R, 22G and 22B are multipliers. Here, the gain calculated by the gain calculating means 21 is fed back to the outputs Ra, Ga, and Ba from the inverse γ processing unit 17 and multiplied by the multipliers 22R, 22G, and 22B. That is, for the data before correction,
Even after the correction, the value is reduced in advance so that the value falls within the input range required by the modulator 8. By making the other respective configurations similar to those of the eleventh and twelfth embodiments, it was possible to display suitable corrected image data.

(Fourteenth Embodiment) As a fourteenth embodiment of the present invention, a configuration shown in FIG. 49 will be described. In the present embodiment, the range selecting means 400 is connected as in the twelfth embodiment, and the gain calculated by the gain calculating means 21 as in the thirteenth embodiment is calculated by the inverse γ
The configuration is such that Ra, Ga, and Ba, which are outputs from the processing unit 17, are fed back and multiplied by the multipliers 22R, 22G, and 22B. By making each of the other configurations similar to those of the eleventh to thirteenth embodiments, suitable corrected image data could be displayed.

(Fifteenth Embodiment) The inventors have found that the following problems occur depending on the image input in the overflow processing as described above.

The overflow process of the first embodiment will be described below as an example. The overflow process of the present embodiment will be described by taking the first embodiment as an example, but it goes without saying that it can be applied to other embodiments.

For example, the number of input bits to the modulation means is 8
When the number of bits of the corrected image data Dout is 9 bits and the maximum value of the corrected image data of a certain frame, that is, the output of the maximum value detecting means is 255 or more, the gain becomes 1 or less, and the corrected image data The problem of image quality deterioration caused by multiplying Dout by a gain of 1 or less is hardly recognized.

However, when an image such as a night view in which the entire screen is dark is input, the maximum value of the corrected image data of that frame becomes a small value. For example, if the value of the corrected image data is 25 as an example, then the value of the gain is about 10 (= 255/25). When this gain is multiplied by the corrected image data Dout, the following problems occur.

The first problem is that an originally dark image is displayed very brightly, and the second is that the display resolution is multiplied by the gain and becomes coarse, and the pseudo contour is conspicuous. Therefore, the quality of the displayed image is significantly reduced. That is, the above problem occurs when the gain has a large value.

FIG. 50 is a block diagram showing a schematic structure of the image display device according to the fifteenth embodiment.

In the present embodiment, in order to prevent the above-mentioned deterioration of the display image, the maximum value detecting means 901 for detecting the maximum value of the corrected image data for each frame and the adder, as will be described later. Of the gain calculation unit 902 that calculates a gain such that the output (corrected image data) falls within the input range of the modulation unit, the gain limiting unit 903 that limits the maximum value of the gain calculated by the gain calculating unit, and the gain limiting unit. Multiplier 904 that multiplies the output by the corrected image data
This makes it possible to control the gain so that it is not too large for a dark input image as a whole and to prevent overflow for a bright input image.

(Maximum value detecting means (maximum value detecting section)) The maximum value detecting means 901 of this embodiment is connected to each section as shown in FIG.

The maximum value detecting means 901 is a means for detecting the maximum value in the corrected image data Dout for one frame. The maximum value of the detected corrected image data (maximum corrected image data) is transferred to the gain calculating means 902.

(Gain Calculating Means (Gain Calculating Section)) The gain calculating means 902 is a means for calculating the gain so that the corrected image data Dout falls within the input range of the modulating means.

In the configuration of the first embodiment, the gain determination method may be determined by equation 12 or equation 13.

The gain is updated in the vertical blanking period and the gain value is changed for each frame.

Also in the present embodiment, as in the first embodiment, a limiter means 905 described later may be provided for the output of the multiplier that multiplies the corrected image data and the gain.

(Gain limiting section) In FIG. 50, the gain limiting section 903 limits the maximum value of the gain calculated by the gain calculating means 902 and outputs it to the multiplier 904.

The configuration of the gain limiting section 903 is a limiter circuit (also referred to as a gain limiter), and its concrete configuration is as shown in FIG.

The output of the gain calculating means 902 is the comparator 9
032 is input to the contact a of the switch 9033. The output from the gain limiting register 9031 is connected to the other input of the comparator 9032 and the contact b of the switch 9033.

The maximum gain value is stored in advance in the gain limiting register 9031. The maximum gain value and the gain calculated by the gain calculating means 902 are compared with each other by the comparator 9032.
If the gain calculated by the gain calculating means 902 is larger than the maximum gain value stored in the gain limiting register 9031, the switch 9033 selects the contact b and the maximum gain stored in the gain limiting register 9031. Output the value.

On the other hand, if the gain calculated by the gain calculating means 902 is smaller than the maximum gain value stored in the gain limiting register 9031, the switch 9033 selects the contact a and sets the gain calculated by the gain calculating means 902. Output.

The maximum gain value stored in the gain limit register 9031 is preferably about 0.5 to 2,
Above all, 1 was good.

Further, the present inventors have confirmed that the gain may be limited by a configuration as shown in FIG. 52 other than the configuration of the gain limiting section 903 described above.

In FIG. 52, 9034 is a gain limit table, which is a memory (also referred to as a gain table memory) in which gain limit characteristics are stored in advance.

The address line of the gain limit table 9034 (gain table memory) is connected to the output of the gain calculating means 902, and the data line of the gain limit table 9034 (gain table memory) is connected to the multiplier 904.

For example, the gain limiting characteristic is shown in FIG.
In order to realize the characteristic of the gain limiting unit 903 shown in (3), the characteristic of FIG. 53A is stored in the gain limiting table 9034 (the maximum gain value is set to 1 in this example,
It is preferable to choose from 0.5 to 2).

Further, the gain limiting characteristic is shown in FIG.
When the characteristic was gently restricted as in the case of (b), the image could be displayed better (the maximum gain value was set to 1 in this example, but it is preferable to select from 0.5 to 2).

In the present embodiment, the gain calculation means 902
The gain limiter 903 is collectively referred to as a limit gain calculation means.

In the limited gain calculating means, the gain calculating means 902 receives the maximum value (maximum corrected image data) in the corrected image data Dout for one frame obtained by the maximum value detecting means 901, and the corrected image data Dout The gain to be multiplied to fit within the input range of the modulation means was calculated.

Next, the gain limiting section 903 limits the maximum value of the gain calculated by the gain calculating means 902 and outputs it to the multiplier 904.

The same effect can be obtained even if the limiting gain calculating means has the following configuration.

The limiting gain calculating means is the maximum value detecting means 9
The maximum correction image data for one frame obtained in step 01 is provided with a unit (a correction image maximum value limiting unit (not shown)) for limiting the minimum value (setting the lower limit of the minimum value). Further, the output of the corrected image maximum value limiting means is set to the gain calculating means 9
The gain is calculated at 02.

The embodiment of the correction image maximum value limiting means (not shown) is almost the same as the configuration of the gain limiting unit 903 described above, and therefore the drawing is omitted.

As described above, by using the image display device of this embodiment, it is possible to correct the influence of the voltage drop occurring in the scanning wiring and increase the brightness of the display image in the normal image. When an image with low average brightness is input, the effect of the voltage drop on the scanning wiring is corrected, and a dark image is displayed very brightly. It was very favorable because it could prevent the contour from being conspicuous.

(Sixteenth Embodiment) In the overflow processing as described above, the present inventors
As a result of further study, it was confirmed that the feature amount calculating means (scene switching determining means) can perform more precise determination by performing the following processing.

(Characteristic Amount Calculation Means (Scene Switching Discrimination Unit)) The characteristic amount calculation means 60 of the present embodiment is connected to each unit as shown in FIG.

The characteristic amount calculating means 60 shown in FIG. 55 calculates the partial average luminance level (L_APL) of the image data for each frame for each predetermined area, and further calculates the absolute value by calculating the difference between the frames. It is a means for adding the results of comparing the area calculation results with predetermined values.

In this embodiment, a configuration in which three predetermined areas are selected will be described.

In FIG. 55, 61a, 61b, 61c
Is area determining means, 62a, 62b and 62c are latches,
63a, 63b, 63c are difference calculation means, 64a, 64
Reference numerals b and 64c are comparators, 65a, 65b and 65c are coefficient registers, and 66a, 66b, 66c and 67 are adders.

In the adders 66a, 66b and 66c,
The values stored in the respective latches 62a, 62b, 62c are added to the sequentially transferred image data and stored again in the latches 62a, 62b, 62c. Then, the input image data is sequentially added.

Here, the area determining means 61a, 61b,
The position information 61c compares the position information of the input image data with the predetermined area information stored in each of them, and outputs an enable signal to the latches 62a, 62b, 62c when they match.

If the values of the latches 62a, 62b and 62c are cleared to 0 at the beginning of the frame, the added value of the image data in the frame at the end of the frame (the number of pixels in each area of one frame is fixed. , A value proportional to the average value) is obtained for each predetermined area. This value becomes the partial average luminance level (L_APL) of each predetermined area.

Next, the difference calculating means 63a, 63b, 63
In c, the difference in the partial average luminance level (L_APL) between frames is calculated for each predetermined area, and the absolute value is further calculated.

Then, the absolute values of the respective predetermined areas are compared with the predetermined values stored in the coefficient registers 65a, 65b and 65c by the comparators 64a, 64b and 64c, respectively. 1 is output if there is a scene change. When the absolute value of each predetermined area is smaller than each predetermined value, 0 is output.

Further, in the adder 67, the outputs of the comparators 64a, 64b, 64c are added and the result is output from the characteristic amount calculating means 60. Therefore, the feature amount calculation means 60
The larger the number of areas determined to be scene changes, the larger the output of.

(Determination Means) Determination means 80 of the present embodiment
As shown in FIG. 54, the output of the feature amount calculation means 60 is input, and the result of comparison with a predetermined value is output to the filter means 40 described later.

In FIG. 56 showing the structure of the judging means 80, 83 is a coefficient register and 84 is a comparator.

The output from the characteristic amount calculating means 60 is compared with a predetermined value stored in the coefficient register 83 by the comparator 84, and if the input value is larger than the predetermined value, it is determined that a scene change has occurred, and High is output.

Here, the adder 67 provided in the feature amount calculating means 60 may be a combination of an AND circuit and an OR circuit. In this case, the determining means 80 is unnecessary, but the AND circuit and the OR circuit are not necessary. The combination of must be complicated.

(Scene Change Judgment) As described above, the sense of incongruity can be eliminated by changing the output of the filter means 40 by the scene change judgment, but the scene is changed by the change of the average luminance (APL) of the entire screen between frames. When the change is determined, the scene change may be erroneously detected.

Specifically, it was when a telop appeared in white letters at the bottom of the screen against the same background. In this case, the telop increases the average brightness (APL) of the entire screen,
Since it was judged as a scene change accordingly, the screen suddenly became dark immediately after the telop appeared.

In order to prevent this phenomenon, in the present embodiment, as the predetermined area in the feature amount calculation means 60,
An area obtained by dividing the screen into three parts is stored, and the partial average luminance (L_APL) in each area is calculated.

According to this structure, when the telop appears, the partial average luminance (L_AP) of the area under the screen changes.
L) only, and the output of the adder 67 (that is, the output of the feature amount calculation means) becomes 1. Therefore, by storing 2 as the value of the coefficient register 83a, erroneous detection of a scene change can be prevented.

Here, each of the actual coefficient registers 65a, 6a
The difference detection means 63 as the values stored in 5b and 65c.
When the maximum value of a, 63b, and 63c was 255, the range of 5 to 20, particularly the value of 10, was optimum.

In the image actually displayed by the above-described structure, the flicker disturbing feeling and the uncomfortable feeling at the scene change are removed without the scene change being erroneously detected.
It was good.

In the above example, the structure for eliminating the discomfort for the horizontal telop has been described for the sake of simplicity.
It was effective to divide the area into left and right to remove the feeling of strangeness in the scene where vertical telop appears. In fact, in order to eliminate the discomfort caused by the combination of them, it was effective to adopt areas that were finely divided by position information.
Also, each area did not necessarily have to be independent.

Also, the output of the inverse gamma processing unit is input to the feature amount calculation means 60, and the partial average luminance level (L
Even if the determination is made based on the inter-frame difference of (_APL), the same effect is obtained.

Further, the corrected image data is calculated as the characteristic amount calculating means 6
0, and enter the partial average brightness level (L_AP
Similar effects were obtained even when the determination was made based on the inter-frame difference of L).

Further, FIG. 57 shows the configuration of the characteristic amount calculating means 60.
The corrected image data is calculated as shown in FIG.
The same effect can be obtained by inputting the data into the area and making a determination based on the inter-frame difference of the partial maximum value of each area.

In FIG. 57, 61a, 61b, 61c
Is area determining means, 62a, 62b, 61c are latches,
63a, 63b, 63c are difference calculation means, 64a, 64
b, 64c, 66a, 66b, 66c are comparators,
Reference numerals 65a, 65b and 65c are coefficient registers, and 67 is an adder.

In the comparators 66a, 66b, and 66c, the values stored in the latches 62a, 62b, and 62c are compared with the corrected image data sequentially transferred, and the larger value is latched again.
Store in c. Then, the input image data are sequentially compared.

Here, the area determining means 61a, 61b,
Reference numeral 61c compares the positional information of the input corrected image data with the predetermined area information stored in each of them, and when they match, the latches 62a, 62b, 62c respectively.
To the enable signal. The value of the latch is
If it is cleared to 0 at the beginning of the frame, the partial maximum value of the corrected image data in the frame is obtained for each predetermined area at the end of the frame.

Next, the difference calculating means 63a, 63b, 63
In c, the difference between the partial maximum values is calculated for each predetermined area, and the absolute value is calculated.

Then, the absolute values of the respective predetermined areas are compared with the predetermined values stored in the coefficient registers 65a, 65b and 65c by the comparators 64a, 64b and 64c, respectively, and if the absolute values are larger than the predetermined value, a scene change occurs in each of the predetermined areas. Outputs 1 if there is. When the absolute value of each predetermined area is smaller than each predetermined value, 0 is output.

Further, in the adder 67, the outputs of the comparators 64a, 64b, 64c are added and the result is output from the feature quantity calculating means 60. Therefore, the feature amount calculation means 6
The output of 0 has a larger value as the number of areas determined to be a scene change increases.

Further, the characteristic amount calculating means 60 secures an address for storing the calculated value of each area as a memory, and
The same effect was obtained even if the determination and calculation were performed by U.

As described above, according to the present embodiment, the feeling of obstruction (flicker) that may occur when performing the overflow process when the voltage drop correction is performed and the strangeness at the time of scene change are reduced. It was possible to improve the image quality.

(Seventeenth Embodiment) In the overflow processing as described above, the present inventors
As a result of further study, it was confirmed that it was more preferable to perform the processing for calculating the gain as follows.

For example, taking the overflow process as shown in the first embodiment as an example, it has been found that the gain G for multiplying the corrected image data by the overflow process is as follows.

A. If a value equal to or lower than the gain G calculated so as not to overflow is used, the brightness changes in proportion to the value of the gain G. However, when the value of the gain G is small, the brightness is dark and the gradation is further deteriorated.

B. When a value larger than the gain G calculated so as not to overflow is used, the brightness increases according to the value of the gain G. However, when the value of the gain G is large, the limiter 905 cannot display an image faithfully.

Further, when studying to display an image by multiplying the corrected image data Dout by such a gain G, depending on the external environment, especially the illuminance of the place where the image is displayed,
It has been found that the evaluation value for the subjective display image changes.

That is, C.I. When the illuminance of the place where the image is displayed is lower than the reference value (when the screen is viewed in a dark room), the image quality is deteriorated due to the influence of the scanning wiring, rather than displaying the screen with higher brightness (that is, displaying it brighter). It is better to correct
The evaluation value for the subjective display image was improved.

D. When the illuminance at the place where the image is displayed is higher than the reference value (when viewing the screen in a bright room), it is better to display the screen with higher brightness than to correct the image quality deterioration due to the influence of the scanning wiring. The evaluation value for the subjectively displayed image was improved (that is, the brighter the display was).

Here, the reference value is not necessarily uniquely determined, but in consideration of the characteristics of the image display device, its user, field of use, etc., an optimum value may be set as the reference value. Good. For example, it is conceivable to use the illuminance in the environment where the image display device is most used as the reference value.

From such a constitutional characteristic and subjective evaluation, the present inventors multiply the corrected image data by the gain with the following constitution and display an image, thereby obtaining a good display image. I was able to get it.

FIG. 58 is a block diagram showing a schematic structure of the image display device according to the seventeenth embodiment.

That is, in addition to the above configuration, the external environment input means 906 for inputting the external environment and the external environment input means 9
It has a KGAIN table (conversion means) 907 for converting the output of 06 into KGAIN, and further has a gain calculation means 9
02 is the output of the maximum value detecting means 901 and the KGAIN.
By calculating a gain G as will be described later, the gain is calculated for each frame by a multiplier that multiplies the calculated gain G by the output of the corrected image data, and the input data of the modulation means is calculated. A good display image could be obtained.

Details will be described below.

(Maximum value detecting means (maximum value detecting section)) The maximum value detecting means of the present invention is connected to each section as shown in FIG.

The maximum value detecting means 901 is a means for detecting the maximum value in the corrected image data Dout for one frame.

The maximum value of the detected corrected image data (maximum corrected image data) is transferred to the gain calculating means 902.

(Gain Calculating Means (Gain Calculating Section)) The gain calculating means 902 is a means for calculating a multiplier (gain G) by which the corrected image data Dout is multiplied. An example of the actual calculation formula of the gain calculation means 902 is shown below.

The method of determining the gain is such that, within one frame, the maximum value of the output data of the adder detected by the maximum value detection unit is M
AX, the maximum value of the input range of the modulation means is INMAX, and the output of a KGAIN table (conversion means) described later is KGAI.
If N,

[Equation 23] To be

If the gain G is determined by this method, K
Gain G is increased by increasing the value of GAIN from 1
Can be made larger and the brightness of the display image can be made brighter.

The gain G obtained by the gain calculating means 902 is updated during the vertical blanking period, and the gain value is changed for each frame.

When KGAIN is larger than 1, the multiplier 9
The output of 04 generates more data that exceeds the maximum value of the input range of the modulation means 8. As will be described later, the corrected image data Dmulti obtained by multiplying the corrected image data by KGAIN causes overflow.

Further, in the configuration of the image display device of this embodiment, the maximum value of the corrected image data of the preceding frame is used to calculate the gain by which the corrected image data of the current frame is multiplied. .

Therefore, strictly speaking, overflow may occur due to the difference in the corrected image data for each frame.

As described above, the corrected image data Dmul obtained by multiplying KGAIN with respect to the above two causes of overflow.
Limiter means 905 described later for t (output of multiplier)
Is provided, and the circuit is designed so that the output of the multiplier 904 falls within the input range of the modulation means 8.

Results of the above-mentioned subjective evaluation C. Therefore, when the environment in which the display device is placed is dark, the display image has a high fidelity (instead, the brightness is suppressed).
Set to = 1.

Further, the result of the above-mentioned subjective evaluation D. From
When the environment in which the display device is placed is bright, KG is used to increase the brightness (instead, reduce the fidelity of the displayed image).
Set AIN = 1 to 2.

By setting KGAIN as described above, an excellent image display can be subjectively performed.

A specific method for creating KGAIN will be described later.

(Multiplier) The output of the gain calculating means 902 and the corrected image data Dout are the multiplier 904 of FIG.
And is transferred to the limiter means 905 as corrected image data Dmulti. The multiplier 904 may be configured by a so-called logic circuit, or the multiplication result is stored in a table memory (ROM or RAM), two parameters to be multiplied are input to an address, and the multiplication result is output from data. May be.

Further, since the limiter means 905 to which the output of the multiplier 904 is connected can also be constituted by the table memory, the limiter means 905 and the multiplier 904 can be constituted by one table memory.

In this case, as the contents to be stored in the table memory, data for limiting the multiplication result may be described.

The preferable limiter characteristics will be described below.

(Limiter Means) The gain G is determined as described above, but as described above, overflow often occurs. Therefore, a limiter is provided to prevent the modulator from overflowing.

The limiter means 905 has a preset limit value, compares the output data Dmulti input to the limiter means 905 with the limit value, and if the limit value is smaller than the output data Dmulti, the limit value is set. If the limit value is larger than the output data Dmult, the output data Dmult is output (the signal name in FIG. 58 is the corrected image data Dlim).

The limiter means 905 may have a characteristic of a broken line which is a straight line having a constant inclination up to the maximum value as shown in FIG. 59 (a), or may be saturated at the maximum value as shown in FIG. 59 (b). It may have a curved characteristic such as a saturated characteristic. The limiter with the characteristics shown in FIG. 59A can be realized by a comparator, and the limiter with the characteristics shown in FIG. 59B can be realized by a table memory or the like.

The limiting means 905 causes the modulating means 8
Image data Dlim completely limited to the input range of
Is supplied to the modulation means 8 via the shift register 5 and the latch 6.

(External environment input means) External environment input means 9
Reference numeral 06 denotes a sensor such as a CdS light receiving element or a photodiode, which is installed near the display panel. Then, the illuminance of the environment where the display device is placed is converted into an electric signal, and further converted into a digital signal by an analog / digital converter and output.

If the external environment input means 906 has a low-pass filter (not shown) and is designed so that the output changes slowly with respect to the temporal change of the environment (illuminance), the display image becomes better.

(User Input Means) User Input Means 9
08 is realized by, for example, a switch, and selects the conversion characteristic stored in the KGAIN table described later according to the user's preference. Of course, a remote controller or the like may be used.

(KGAIN table) The KGAIN table 907 outputs the output of the external environment input means to KGAIN.
Is a conversion means for converting into. KGAIN is, for example, as shown in FIG. 60A, a table that outputs 1 when it is dark and 1.5 when it is bright, and is composed of a memory in which the characteristics are stored in advance. .

Further, by the output of the user input means, the characteristics can be set as shown in FIG.
It is possible to select (b), (c) or the like. This function connects the output of the user input means to the upper address of the memory that constitutes the KGAIN table 907,
It is realized by switching banks.

The characteristic (a) is K when the external environment is dark.
This is an example of converting GAIN to 1 and KGAIN to 1.5 when the external environment is bright.

In this case, as will be described later, when the external environment is dark, the gain G for displaying the corrected image data Dmulti without overflow is calculated. And the image can be displayed faithfully.

When the external environment is bright, the gain G is calculated to be large and the display brightness is increased. When the external environment is bright, the corrected image data Dmulti overflows the modulation means 8, so the limiter 905 limits the output of the multiplier 904 (corrected image data Dmulti). For this reason, the fidelity becomes worse at the expense of higher brightness.

By using such a KGAIN table, as shown in the above-mentioned subjective evaluation (CD), subjectively good display is possible.

The characteristic of (b) is that KG when the external environment is dark.
In this example, AIN is converted to 1 and KGAIN is converted to 2 when the external environment is bright. In this case, since KGAIN is increased when the external environment is brighter than that in (a), the fidelity becomes worse, but a brighter image can be displayed as compared to (a). The user selects a good conversion table by the user input means according to the type of the input image displayed.

The characteristic (c) is an example in which KGAIN is fixed at 1. In this case, KGAIN is set to 1 regardless of the brightness of the external environment, so the corrected image data Dm
The ult can be displayed without overflow. The user may select it when he / she wants to display the image faithfully to the input image.

Further, the inventors of the present invention have conducted extensive studies and carried out KGA
It has been found that the IN table 907 can obtain good results also by having the following characteristics.

For example, as shown in FIG. 61 (d), KGA
In this example, the area of IN = 1 is changed from low illuminance to medium illuminance. In this case, the image can be displayed faithfully even if the external environment is slightly bright. Further, as shown in FIG. 61 (e), if the characteristic that KGAIN is changed smoothly with respect to the external illuminance, even if the external illuminance changes, a person who looks at the image display panel does not feel uncomfortable.

The curves shown in FIGS. 62 (f) and 62 (g) were also effective.

By making it possible to select the characteristics described above by the output of the user input means, it is possible to display the characteristics satisfactorily according to the user's preference, the type of input image, and the like.

As described above, according to the present invention, by providing the external environment inputting means, the external environment information (illuminance) is input and the converting means (KGAI) for converting the value into KGAIN.
N table) to obtain KGAIN.

When the gain G is calculated by the gain calculating means and the calculated gain G is multiplied by the corrected image data or the input image data, when the illuminance at the place where the image is displayed is lower than the reference value (in a dark room, a screen is displayed). When the illuminance at the place where the image is displayed is higher than the reference value (when the image is displayed in a bright room, the brightness of the screen is not increased (that is, it is displayed brightly)) When the image is viewed), the image quality deterioration due to the influence of the scanning wiring is accurately corrected to increase the brightness of the screen (that is, display the image brightly), whereby a subjectively good display image can be obtained.

[0611]

As described above, according to the image display device of the present invention, it is possible to suitably improve the deterioration of the display image due to the voltage drop on the scanning wiring, which has been a problem in the past.

Further, by introducing some approximations, the corrected image data in which the influence of the voltage drop is corrected can be easily and suitably calculated, and it can be realized by very simple hardware. It had a very good effect.

Further, an overflow processing circuit is provided so that the corrected image data does not overflow the input range of the modulation means, and in the overflow processing, the overflow processing method is changed between the television video signal and the computer video signal. As a result, the image could be displayed with high quality.

[Brief description of drawings]

FIG. 1 is a diagram showing an overview of an image display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an electrical connection of a display panel.

FIG. 3 is a diagram showing characteristics of a surface conduction electron-emitting device.

FIG. 4 is a diagram showing a driving method of a display panel.

FIG. 5 is a diagram illustrating a degenerate model.

FIG. 6 is a graph showing a voltage drop amount calculated discretely.

FIG. 7 is a graph showing the amount of change in emission current calculated discretely.

FIG. 8 is a diagram for explaining another method of calculating correction data.

FIG. 9 is a diagram showing an example of calculation of correction data when the size of image data is 192.

FIG. 10 is a diagram for explaining an interpolation method of correction data.

FIG. 11 is a block diagram showing a schematic configuration of the image display device according to the first embodiment.

FIG. 12 is a block diagram showing a configuration of a scanning circuit of the image display device.

FIG. 13 is a block diagram showing a configuration of an inverse γ processing unit of the image display device.

FIG. 14 is a block diagram showing a configuration of a data array conversion unit of the image display device.

FIG. 15 is a diagram showing an example of consecutive frames.

FIG. 16 is a graph showing the size of image data in consecutive frames.

FIG. 17 is a graph showing a gain in consecutive frames.

FIG. 18 is a diagram illustrating the configuration and operation of the modulation means of the image display device.

FIG. 19 is a timing chart of the modulation means of the image display device.

FIG. 20 is a block diagram showing a configuration of a correction data calculation unit of the image display device.

FIG. 21 is a block diagram showing a configuration of a discrete correction data calculation unit of the image display device.

FIG. 22 is a block diagram showing a configuration of a correction data interpolation unit.

FIG. 23 is a block diagram showing a configuration of a linear approximation means.

FIG. 24 is a timing chart of the image display device.

FIG. 25 is a block diagram showing a schematic configuration of an image display device according to a second embodiment.

FIG. 26 is a block diagram showing a schematic configuration of an image display device according to a third embodiment.

FIG. 27 is a block diagram showing a schematic configuration of an image display device according to a fourth embodiment.

FIG. 28 is a block diagram showing a schematic configuration of an image display device according to a fifth embodiment.

FIG. 29 is a block diagram of a gain calculation unit according to the fifth embodiment.

FIG. 30 is a block diagram of a gain calculation unit according to the sixth embodiment.

FIG. 31 is a block diagram showing a schematic configuration of an image display device according to an eighth embodiment.

FIG. 32 is a block diagram showing a configuration of a filter means of the eighth exemplary embodiment.

FIG. 33 is a block diagram showing another configuration of the filter means of the eighth exemplary embodiment.

FIG. 34 is a diagram illustrating a change in maximum corrected image data in a moving image, which has been described in the eighth embodiment.

FIG. 35 is an output graph of the frame number-to-filter unit described in the eighth embodiment.

FIG. 36 is a frame number vs. average luminance (APL) graph described in the eighth embodiment.

[Fig. 37] Fig. 37 is an output graph of frame number versus filter means for which a scene change has been performed, which has been described in the eighth embodiment.

FIG. 38 is a block diagram showing a schematic configuration of an image display device according to a ninth embodiment.

FIG. 39 is a block diagram showing a schematic configuration of an image display device according to a tenth embodiment.

FIG. 40 is a block diagram showing a configuration of a filter means of the tenth embodiment.

[Fig. 41] Fig. 41 is a diagram illustrating a change in maximum corrected image data of a moving image containing noise, which has been described in the eleventh embodiment.

FIG. 42 is a block diagram showing a schematic configuration of an image display device according to an eleventh embodiment.

FIG. 43 is a block diagram showing a configuration of range selecting means according to an eleventh embodiment.

FIG. 44 is a diagram illustrating a change in maximum corrected image data when a noise part is ignored, which is described in the eleventh embodiment.

FIG. 45 is a block diagram showing another configuration of the range selecting means of the eleventh embodiment.

FIG. 46 is a diagram showing characteristics of weights of the range selecting means of the eleventh embodiment.

FIG. 47 is a block diagram showing a schematic configuration of an image display device according to a twelfth embodiment.

FIG. 48 is a block diagram showing a schematic configuration of an image display device according to a thirteenth embodiment.

FIG. 49 is a block diagram showing a schematic configuration of an image display device according to a fourteenth embodiment.

FIG. 50 is a block diagram showing a schematic configuration of an image display device according to a fifteenth embodiment.

FIG. 51 is a block diagram showing a first configuration of a gain limiting section of the fifteenth embodiment.

FIG. 52 is a block diagram showing a second configuration of the gain limiting section of the fifteenth embodiment.

FIG. 53 is an example of a gain limiting characteristic of the gain limiting table of the fifteenth embodiment.

FIG. 54 is a block diagram showing a schematic configuration of an image display device according to a sixteenth embodiment.

FIG. 55 is a block diagram showing the structure of a feature amount calculating means according to the sixteenth embodiment.

FIG. 56 is a block diagram showing the structure of a judging means of the sixteenth embodiment.

FIG. 57 is a block diagram showing another configuration of the feature amount calculating means of the sixteenth embodiment.

FIG. 58 is a block diagram showing a schematic configuration of an image display device according to a seventeenth embodiment.

FIG. 59 is a diagram showing characteristics of the limiter means of the seventeenth embodiment.

FIG. 60 is a diagram showing an example of the characteristics of the KGAIN table of the seventeenth embodiment.

FIG. 61 is a diagram showing an example of the characteristics of the KGAIN table of the seventeenth embodiment.

FIG. 62 is a diagram showing an example of characteristics of a KGAIN table according to the seventeenth embodiment.

FIG. 63 is a block diagram showing a schematic configuration of a conventional image display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 display panel 2 scanning circuit 3 sync separation circuit 4 timing generation circuit 5 shift register 6 latch 8 pulse width modulation means 9 data array conversion section 12 adder 14 correction data calculation means 14a discrete correction image data calculation means 14b correction image data interpolation circuit 17 Inverse γ Processing Unit 19 Delay Circuit 20 Maximum Value Detection Means 21 Gain Calculation Means 22 Multiplier 23 Selector 40 Filter Means 54 Judgment Means 60 Judgment Means Calculator 80 Judgment Means 100a, 100b, 100c, 100d Lighting Number Count Means 101a 101b , 101c, 101d Register 103 Table memory 107a, 107b, 107c Comparator 111 Table memory 123, 124 Decoder 400 Range selecting means 409 Decoder 901 Maximum value detecting means 902 Gain calculating means 903 Gain limiting section 04 Multiplier 905 Limiter 906 External environment input means 907 Table 908 User input means 1001 Substrate 1002 Cold cathode element 1003 Row wiring (scanning wiring) 1004 Column wiring (modulation wiring) 1007 Face plate 1008 Fluorescent film 1009 Metal back 9031 Gain limit register 9032 Comparator 9033 Switch 9034 Gain limit table

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 633 G09G 3/20 633L 641 641A 641C 641P 642 642F (31) Priority claim number Japanese Patent Application No. 2001-353889 (P2001) −353889) (32) Priority date November 19, 2001 (November 19, 2001) (33) Priority claim country Japan (JP) (31) Priority claim number Japanese Patent Application No. 2001-361478 (P2001-361478) (32) Priority date November 27, 2001 (November 27, 2001) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 2001-364561 (P2001-364561) (32) Priority date November 29, 2001 (November 29, 2001) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 2001-370466 (P2001-370466) (32) Priority date Heisei December 4, 2013 (December 4, 2001) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 2001-374624 (P2001-374624) (32) Priority date December 2001 7th (2001.12.7) (33) Priority claim countries Japan (J P) (72) Inventor Yutaka Saito 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Kohei Inamura 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) ) Inventor Takeshi Ikeda 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. F-term (reference) 5C080 AA08 AA18 BB05 DD04 DD05 EE19 EE29 GG08 JJ02 JJ04 JJ05 JJ06

Claims (31)

[Claims] 1. A plurality of row wirings and column wirings, a display panel including image forming elements connected to the row wirings and column wirings, scanning means for sequentially selecting and scanning the row wirings, and the column wirings. An image display device comprising: a modulation means connected to the correction means; a correction image data calculation means for calculating correction image data for the image data; and an amplitude of the correction image data within an input range of the modulation means. And an amplitude adjusting unit that adjusts the amplitude of the corrected image data, wherein the modulating unit receives the amplitude-adjusted corrected image data as an input and outputs a modulation signal to the column wiring. Display device. 2. The image display device according to claim 1, wherein the corrected image data calculation means is means for correcting the influence of a voltage drop caused by at least the resistance of the row wiring on the image data. 3. The corrected image data calculating unit obtains the corrected image data by expanding the size of the image data input to the corrected image data calculating unit. Image display device. 4. The amplitude adjustment means detects a maximum value of the output of the corrected image data calculation means, and a gain calculation which calculates a gain so that the maximum value falls within the input range of the modulation means. The image display device according to claim 2, further comprising: 5. The amplitude adjusting means is means for obtaining the amplitude adjusted corrected image data by multiplying the corrected image data or the image data by the gain. The image display device according to. 6. The image display device according to claim 5, further comprising a limiter arranged to limit the amplitude so that the amplitude-modulated corrected image data is completely included in the input range of the modulating means. 7. The image display device according to claim 4, wherein the gain is an adaptive gain calculated for each frame. 8. The image display device according to claim 7, wherein the amplitude adjusting means has a filter means for limiting a variation of the gain for each frame. 9. The amplitude adjusting means further comprises a scene switching discriminating section for detecting that the scene of the display image has changed, and the filter means limits the variation of the gain when the scene switching is discriminated. 9. The image display device according to claim 8, wherein the processing described above is not performed. 10. The scene switching discriminating unit determines an average luminance level (AP for each frame of input image data.
The image display device according to claim 9, wherein the scene switching is determined based on the inter-frame difference of L) and / or the inter-frame difference of the maximum value of the corrected image data for each frame. 11. The image display device according to claim 4, wherein the amplitude adjusting unit has a gain limiting unit that limits the gain to a preset upper limit value or less. 12. The maximum value detecting unit detects the maximum value of the corrected image data in a predetermined area of the corrected image data in the frame, not in the entire display area. The image display device according to item 4. 13. The maximum value detection unit detects the maximum value of the corrected image data multiplied by the weight by a range selection unit that multiplies the corrected image data by a weight determined according to the display position. The image display device according to claim 12. 14. The image display device according to claim 13, wherein a weight multiplied by the range selecting means is large in a display central portion and small in a peripheral portion. 15. The maximum value detection unit excludes the corrected image data for one or more and one-tenth or less of the total number of line wirings from the upper and lower end portions of the display area, except for the corrected image data. 13. The image display device according to claim 12, wherein the maximum value of the corrected image data for the row wiring is detected. 16. The scene switching discriminating unit divides the display area into a plurality of areas, discriminates scene switching for each area, and switches scenes for the entire screen from the discrimination result for each area. The image display device according to claim 9, wherein the image display device discriminates. 17. The scene switching discriminating unit divides the entire screen into a plurality of areas, and calculates a partial average luminance level (L_APL) of the image data or the corrected image data for each frame for each area. At the same time, the inter-frame difference of the partial average brightness level is calculated, and the difference is compared with a predetermined amount to perform the scene switching determination for each area, and the determination result is digitized, and the digitized determination result is added. 17. The image display device according to claim 16, wherein the scene switching determination of the entire screen is performed by comparing the added value with a predetermined value. 18. The amplitude adjusting means includes an external illuminance input section for detecting illuminance around the image display device and outputting a signal according to the detection result, and a gain according to the output signal of the external illuminance input section. The image display device according to claim 4, wherein the image display device is adjusted. 19. The adjustment of the gain is performed by adjusting the maximum value of the corrected image data detected by the maximum value detection unit according to the output of the external illuminance input unit, and based on the adjusted maximum value. The image display device according to claim 18, wherein the image display device is calculated as follows. 20. The amplitude adjusting means does not adjust the gain for adjusting the amplitude when the illuminance is lower than a predetermined reference value, and the gain is higher than the reference value when the illuminance is higher than the reference value. The image display device according to claim 18, having a function of changing the gain to a larger value. 21. The image display device according to claim 18, wherein a method of adjusting the gain performed by the amplitude adjusting unit according to the external illuminance is selected by a user input unit operable by a user. 22. The amplitude adjusting means outputs a first operation mode that outputs the adaptive gain calculated for each frame, and a second operation that outputs a preset fixed gain that does not change for each frame. The image display device according to claim 4, comprising at least two operation modes including a mode. 23. In the operation mode, when the input video signal is a video signal for television, the first operation mode is selected, and the input video signal is a video signal for computer. 23. The image display device according to claim 22, wherein the second operation mode is selected at this time. 24. The image display device according to claim 22, wherein the operation mode is selectable by a user. 25. The corrected image data calculating means predicts and calculates a spatial distribution and a temporal change of a voltage drop amount that should occur on a row wiring during one horizontal scanning period in accordance with input image data. The image display device according to claim 2, further comprising: a unit that calculates corrected image data obtained by correcting the input image data from the calculated voltage drop amount. 26. The corrected image data calculating means discretely predicts and calculates a voltage drop amount to be generated on the row wiring in one horizontal scanning period in the space direction and the time direction, corresponding to the input image data. And discrete correction image data calculation for discretely calculating correction image data for the image data corresponding to the time when the voltage drop amount is calculated at the spatial position where the voltage drop amount is calculated from the voltage drop amount. Means for compensating the output of the discrete corrected image data calculating means and calculating corrected image data corresponding to the size of the input image data and the horizontal display position. 25. The image display device according to item 25. 27. The amplitude adjusting means performs the amplitude adjusting function by multiplying the output of the discrete corrected image data calculating means by a gain for adjusting the amplitude. The image display device according to 2 or 26. 28. The amplitude adjusting means multiplies the output of the discrete corrected image data calculating means by the gain for adjusting the amplitude, and the maximum value of the multiplication result falls within the input range of the modulating means. 27. The image display device according to claim 26, wherein the amplitude adjusting function is achieved by limiting the maximum value. 29. The amplitude adjusting means multiplies the output of the discrete corrected image data calculating means by the gain for adjusting the amplitude, and further outputs the output of the corrected image data interpolating means to the modulating means. 27. The image display device according to claim 1, 2 or 26, wherein the amplitude adjusting function is achieved by limiting the maximum value so as to be within a range. 30. The modulation means is pulse width modulation means for performing modulation by varying the pulse width of the voltage pulse waveform applied to each column wiring in accordance with the input of the modulation means. The image display device according to claim 26. 31. The image display device according to claim 30, wherein the image forming element is a surface conduction electron-emitting device.