JP2003226042A - Driving circuit for optical writing head - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct displacement in the paper feeding direction of the light dot row on a photo drum in an optical writing head with light emitting element array chips mounted by zigzag arrangement. <P>SOLUTION: With the interval of the central line of the light emitting point row of each self scanning type light emitting element array chip provided as a multiple of an integer of the distance on a photosensitive drum moving in the y axis direction per one line time, image data corresponding to an odd- numbered (or even-numbered) light emitting element array chip are stored in a memory element having a capacity larger than (value of the multiple of the integer)×(number of the light emitting elements transferred in the one line time)/2. The image data are read out from the memory element after passage of (value of the multiple of the integer)×(one line time) from the initial data writing time so as to be outputted to the odd-numbered (or even-numbered) light emitting element array chip. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for an optical writing head used in an optical printer, and more particularly to a drive circuit for an optical writing head in which light emitting element array chips are mounted in a staggered arrangement.

[0002]

2. Description of the Related Art A writing head (optical writing head) of an optical printer is a light source for exposing light to a photosensitive drum and has a light emitting point array composed of a light emitting element array. A principle diagram of an optical printer having an optical writing head is shown in FIG. On the surface of the cylindrical photosensitive drum 2, a photoconductive material (photoconductor) such as amorphous Si is formed. This drum is rotating at print speed. The photoconductor surface of the rotating drum is uniformly charged by the charger 4. Then, the optical writing head 6 irradiates the photosensitive member with the light of the dot image to be printed, and neutralizes the charging where the light hits. Subsequently, the developing device 8 applies toner onto the photoconductor according to the charged state of the photoconductor. Then, the transfer device 10 transfers the toner onto the sheet 14 sent from the cassette 12. The sheet of paper is heated and fixed by the fixing device 16 and is fixed to the stacker 18. On the other hand, in the drum after the transfer, the erase lamp 20 neutralizes the charge over the entire surface, and the cleaning device 22 removes the remaining toner.

The structure of the optical writing head 6 is shown in FIG.
The optical writing head 6 is composed of a light emitting element array 24 and a rod lens array 26, and the focal point of the lens is located on the photosensitive drum 2. The rod lens array is
For example, it is configured by stacking rod lenses in a bag.

On the other hand, the present inventors have paid attention to a three-terminal light emitting thyristor having a pnpn structure as a constituent element of a light emitting element array, and have already filed a patent application (Japanese Patent Laid-Open No. 1-238962, which discloses that self-scanning of a light emitting point can be realized). Japanese Patent Laid-Open No. 2-14
No. 584, No. 2-92650, No. 2
No. 92651), it has been shown that it is easy to mount as a light source for an optical writing head, the light emitting element pitch can be made fine, and a compact light emitting element array can be manufactured.

Furthermore, the present inventors have proposed a self-scanning light emitting element array having a structure in which a transfer element array composed of a light emitting thyristor having a pnpn structure is used as a shift register and is separated from the light emitting element array (JP-A-2- 26366
No. 8).

FIG. 3 shows the self-scanning light emitting element array.
Equivalent circuit diagram of (2-phase drive 1 point lighting common cathode type)
Show. This light emitting element array includes switch elements T (1) to
From T (4), the writing light emitting elements L (1) to L (4)
Become. Use a diode connection for the switch element configuration.
I am V_GKIs a power supply (usually 5V) and a load resistance R
_L Through the gate electrode G of each switch element₁ ~ G₃ Connected to
Has been done. Also, the gate electrode G of the switch element₁ ~ G
₃ Is also connected to the gate electrode of the writing light-emitting element.
It The gate electrode of the switch element T (1) has a start pattern.
Ruth φ_S Is added to the anode electrode of the switch element.
Of the transfer clock pulses φ1 and φ2 are alternately applied.
Write on the anode electrode of the light emitting element for writing.
Signal φ_IHas been added.

The operation will be briefly described. First, the transfer clock
When the voltage of pulse pulse φ1 is high level, the switching element T
It is assumed that (2) is on. At this time, the gate electrode
G₂ Potential is V_GKFrom 5 V to almost zero V.
The effect of this potential drop is diode D₂ By gated
Pole G₃ To about 1 V (diode D
₂ Forward voltage (equal to the diffusion potential) of
It However, the diode D₁ Is in reverse bias
Gate electrode G₁ No potential is connected to the gate
Pole G₁ The potential remains at 5V. Light-emitting thyristor
The gate potential is the gate electrode potential + the diffusion potential of the pn junction (about 1
V), the next transfer clock pulse φ2
H level voltage is about 2V (switch element T (3) is turned on
Is higher than the required voltage) and about 4V (switch
Switch element T (5) to turn on)
If set to, only the switch element T (3) is turned on,
Other switch elements can be left off
It Therefore, the on state changes with two transfer clock pulses.
Will be sent.

The start pulse φ _S is a pulse for starting such a transfer operation, and the start pulse φ S
At the same time when _{S is set} to the L level (about 0 V), the transfer clock pulse φ2 is set to the H level (about 2 to about 4 V), and the switch element T (1) is turned on. Immediately after that, the start pulse φ _S is returned to the H level.

Now, assuming that the switch element T (2) is in the ON state, the potential of the gate electrode G ₂ becomes lower than V _GK and becomes almost 0V. Therefore, if the voltage of the write signal φ _I is the diffusion potential of the pn junction (about 1 V) or more,
The light emitting element L (2) can be in a light emitting state.

On the other hand, the gate electrode G ₁ is about 5V and the gate electrode G ₃ is about 1V. Therefore, the writing voltage of the light emitting element L (1) is about 6 V,
The write voltage of (3) is about 2V. From this, the voltage of the write signal φ _I which can be written only to the light emitting element L (2) is in the range of 1 to 2V. Light-emitting element L (2) is on,
That is, when entering the light emitting state, the light emission intensity is the write signal φ.
It is determined by the amount of current flowing through _I , and it is possible to write images at any intensity. In order to transfer the light emitting state to the next light emitting element, the voltage of the write signal φ _I line is once set to 0.
It is necessary to turn off the light emitting element which is emitting light to V.

Such a self-scanning light emitting device array is
It has a feature that the number of bonding pads may be smaller than that of a normal light emitting element array. This feature has the advantage that the chip area can be reduced. By disposing the bonding pads on both ends of the rectangular chip, the chip width can be reduced to a width almost required by the bonding pad itself. However, when it is applied to an optical print head or the like, if a plurality of chips are arranged in one direction, it is not possible to make the intervals of the light emitting point arrays constant at the chip ends. In order to avoid this, there is a so-called zigzag arrangement method in which a part of the chips are arranged in an overlapping manner (Japanese Patent Laid-Open No. 8-2.
16448 gazette).

FIG. 4 is a diagram showing this zigzag arrangement method. For convenience of explanation, the xy coordinate axes are defined as shown in the figure. That is, the x-axis direction is the chip arrangement direction (main scanning direction), and the y-axis direction is the direction orthogonal to the chip arrangement direction (sub-scanning direction). The self-scanning light emitting element array chip 28 has bonding pads 3 on both ends.
0 is provided, and the light emitting element 32 is provided linearly between them.

Such a light emitting element array chip 28 is
Both ends of the chips are overlapped with each other by shifting in the axial direction, arranged in a zigzag pattern in the x-axis direction, and fixed on the substrate with an adhesive. With such an arrangement, the intervals of the light emitting elements in the x-axis direction can be made constant throughout the plurality of chips.

[0014]

However, when an optical writing head in which light emitting element array chips are arranged in a zigzag pattern is used and a light spot array is projected on a photosensitive drum, the array chips are arrayed while being shifted in the y-axis direction. The light spots on the photosensitive drum are displaced (stepped) in the y-axis direction.
The output image also has a step corresponding to the displacement width of the array chip.

When outputting an image, the optical writing head synchronizes the image data in the memory with a desired timing and transfers it to the corresponding light emitting element on the array chip to cause the light emitting element to emit light. At this time, the time for transferring one line is also the time for sequentially turning on the light emitting elements for the number of one line and projecting the light emitting elements on the photosensitive drum, and the photosensitive drum also rotates during this time.

In the staggered array of light-emitting element array chips, if the reference array chip is an odd-numbered array chip, in order to turn on the even-numbered array chip, an odd number is set at a distance corresponding to the time when the photosensitive drum rotates. It needs to be turned on when the light spot train projected by the second array chip comes. This deviation of the lighting time is realized by adjusting the generation timing of the start pulse supplied to the start pulse line for each light emitting element array chip.

That is, in the light emitting element array chips arranged in a staggered pattern, the deviation in the y-axis direction is inevitably generated, and the correction of the deviation in the y-axis direction is supplied to the start pulse line for each array chip. The generation timing of the start pulse is adjusted to reduce the deviation of the light spot train of the light projected on the photosensitive drum.

Therefore, in the conventional optical write head, it is necessary to incorporate a circuit for adjusting the generation timing of the start pulse for each array chip, and since the timing is adjusted for each array chip, the array chip is required. It is necessary to store the set value of the timing for each time, and it is also necessary to synchronize the generation timing of the start pulse supplied to the start pulse line with this set value, which complicates the circuit configuration.

The present invention has been made by paying attention to such a conventional problem, and an object of the present invention is to perform a photosensitive operation without requiring a circuit for adjusting a start pulse generation timing for each array chip. It is an object of the present invention to provide a drive circuit of an optical writing head capable of correcting a shift of a light spot array on a drum in the y-axis direction.

[0020]

According to the present invention, a plurality of light emitting element array chips in which a plurality of light emitting elements are arranged in a row are arranged in a staggered pattern, and a direction orthogonal to the arrangement direction of the light emitting element array chips is provided. The interval between each light emitting element array chip is 1
In order to hold the image data corresponding to the odd-numbered light emitting element array chips in the drive circuit of the optical writing head that mounts each light emitting element array chip at an integral multiple of the distance on the photosensitive drum that moves in line time (the above-mentioned A memory element having a capacity larger than a value of (integral multiple value) × (number of light emitting elements transferred in one line time) / 2 is provided, and when reading data from the memory element, the first data is written. It is characterized in that it is read out after a time (value of the integral multiple) × (1 line time) from the time and is used as image data to be written in the odd-numbered light emitting element array chips.

Further, according to the present invention, a plurality of light emitting element array chips in which a plurality of light emitting elements are arranged in a row are arranged in a staggered pattern, and each light emitting element in a direction orthogonal to the arrangement direction of the light emitting element array chips. Image data corresponding to even-numbered light emitting element array chips in the drive circuit of the optical writing head in which each light emitting element array chip is mounted by making the array chip interval an integral multiple of the distance on the photosensitive drum that moves in one line time. In order to hold the above, a memory element having a capacity larger than the value of (the integer multiple) × (the number of light emitting elements transferred in one line time) / 2 is provided, and reading of data from the memory element is possible. Image data that is read after the time when the first data is written (a value that is an integer multiple) × (1 line time) and is written to the even-numbered light emitting element array chip Characterized in that it is to use.

According to the present invention, the data read from the memory element by the time (value of the integral multiple) × (1 line time) has elapsed from the time when the first data was written, is the image without writing. Is preferable, and the timing of data read from the memory element is preferably read with reference to the transfer clock signal of the light emitting element.

The light emitting element array chip is preferably a self-scanning type light emitting element array chip.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 5 is a diagram showing a state in which the self-scanning light emitting element array chips according to the present invention are arranged in a staggered pattern on the optical writing head. For convenience of explanation, as shown in the figure, xy
The coordinate axes shall be defined. That is, the x-axis direction is the chip arrangement direction (main scanning direction), and the y-axis direction is the direction orthogonal to the chip arrangement direction (sub-scanning direction), which is the same as the paper feeding direction.

Self-scanning light emitting element array chips C _{0 to} C
₃ is the bonding pads 101 to 10 at both ends
4 are provided, and 256 light emitting elements 33 are provided between them.
Are linearly provided at intervals p. A φ _I signal which is a write signal is input to the bonding pad 101,
A φ1 signal (transfer clock pulse) is input to the bonding pad 102, a φ2 signal (transfer clock pulse) is input to the bonding pad 103, and power is supplied to the bonding pad 104.

Self-scanning light emitting element array chips C _{0 to} C
₃ is the light emitting element 3 in which the interval between the center lines of the light emitting point array is in the y axis direction.
The light emitting element array chips are arranged in a zigzag pattern in a zigzag pattern so that the light emitting element array chips are overlapped with each other at a distance corresponding to n times the interval p of 3 (n is an integer) and fixed on the substrate with an adhesive. There is. Consider a case where the paper feed speed advances by p during one line time. Here, the one-line time means a time for sequentially turning on the light-emitting elements for one line and projecting the light-emitting elements on the photosensitive drum.

At this time, the intervals in the x-axis direction between the light emitting points at the ends of the adjacent light emitting element array chips are all equal to p, so that the x of the light emitting element 33 passes through all the plurality of light emitting element array chips. The axial distance is set to a constant value p. Self-scanning light emitting element array chip C ₀ ~
All of C ₃ have the same design, and the even-numbered light emitting element array chips C ₀ and C ₂ and the odd-numbered light emitting element array chips C ₁ and C ₃ are placed to face each other. . Therefore, the lighting direction of the light emitting element 33 is from left to right in the light emitting element array chips C ₀ and C ₂ .
The light emitting element array chips C ₁ and C ₃ are arranged from right to left.

Now, if one straight line data is given to this optical writing head as it is, an image as shown in FIG. 6 having a step difference of np, which is the displacement of the staggered arrangement in the y-axis direction, is drawn. Here, the straight line is not parallel to the x-axis direction because the paper is being fed during drawing, and the inclination of the line drawn by the even numbered chips and the line drawn by the odd numbered chips The lines have different inclinations because the light emitting elements are turned in the opposite directions in the even-numbered chips and the odd-numbered chips. In order to eliminate this np step, the image drawn by the even-numbered chips upstream is sent to the downstream,
The image data for the odd-numbered chips may be delayed by the time np of the paper so as to be connected to the image drawn by the odd-numbered chips. This is realized by the circuit shown in FIG.

FIG. 7 is a circuit diagram showing an embodiment of a drive circuit for an optical writing head according to the present invention. The self-scanning light emitting element array chips C _{0 to} C ₅ are arranged in a staggered pattern, and the amount of shift between the chips in the y-axis direction is n = 2.

Self-scanning light emitting element array chips C _{0 to} C
_The φ1 signal is input to the bonding pad 102 of ₅ from the terminal 83 of the connector 80 via the buffer 76,
A φ2 signal is input from the terminal 82 via the buffer 77 to the bonding pads 103 of the self-scanning light emitting element array chips C _{0 to} C ₅ . Note that φ1 signal and φ2
The current limiting resistor that limits the signal current is built in the self-scanning light emitting element array chip. Power is supplied from the terminal 81 to the bonding pads 104 of the self-scanning light emitting element array chips C _{0 to} C ₅ .

The φ1 signal at the terminal 83 and the φ2 signal at the terminal 82 are sent to the AND circuit 62. AND circuit 62 is φ
The logical product of 1 signal and φ2 signal is obtained, and the obtained signal is
Output to the terminal 41 of the counter 40. The counter 40
The falling edge of the signal output from the AND circuit 62 at the terminal 41 is counted, and the count value is output from the terminal 42.

This count value specifies the address of the RAM 50 which is a memory for storing image data. Here, the memory capacity of the RAM 50 is the number N of odd-numbered chips.
(3 in FIG. 7) × K number of light emission points per chip (see FIG.
Is 256) × amount of shift n (2 in FIG. 7). The RAM 50 has a data bus having a width of N lines.

Although the reset of the counter 40 is not shown in FIG. 7, the reset may be automatically applied when the power is turned on, or the reset signal may be input from the outside. Counter 40 here
Used a 9-bit ripple counter so that 512, which is the number of bits per chip, can be counted.

In the bonding pad 101 of the even-numbered light emitting element array chip C ₀ , a logical product of the φ _I signal from the terminal 86 and the φ _I light emission timing signal from the terminal 90 obtained by the AND gate 64 is the buffer 73, Current limiting resistor 9
It is input via 1.

The bonding pad 101 of the light emitting element array chip C ₂ has a φ _I signal at the terminal 85 and a φ _I signal at the terminal 90.
The logical product of the _I light emission timing signal and the AND gate 65 is input through the buffer 74 and the current limiting resistor 93.

The bonding pad 101 of the light emitting element array chip C ₄ has a φ _I signal at the terminal 84 and a φ _I signal at the terminal 90.
A logical product of the _I emission timing signal and the AND gate 66 is input through the buffer 75 and the current limiting resistor 95.

On the other hand, the odd-numbered light emitting element array chip C ₁
On the bonding pad 101 of the
The logical product of the signal output from 3 and the φ _I light emission timing signal of the terminal 90 is taken by the AND gate 67 and input via the buffer 70 and the current limiting resistor 92.
Further, the φ _I signal from the terminal 87 is input to the terminal 53 of the RAM 50 via the 3-state bus buffer 57.

In the bonding pad 101 of the light emitting element array chip C ₃ , the AND product of the signal output from the terminal 52 of the RAM 50 and the φ _I light emission timing signal of the terminal 90 by the AND gate 68 is used as the buffer 71. , Through the current limiting resistor 94. RAM5
The φ _I signal from the terminal 88 is input to the 0 terminal 52 via the 3-state bus buffer 58.

In the bonding pad 101 of the light emitting element array chip C _5, a buffer 72 is obtained by ANDing the signal output from the terminal 51 of the RAM 50 and the φ _I light emission timing signal of the terminal 90 by the AND gate 69. , Through the current limiting resistor 96. RAM5
The φ _I signal at the terminal 89 is input to the 0 terminal 51 via the 3-state bus buffer 59.

Reading / writing of the RAM 50 is controlled by the state of the switching terminal 54. When the switching terminal 54 is at the H level, the write trigger of the terminal 56 is changed from the L level to the H level, and the contents of the image data given to the terminals 51 to 53 at the address specified by the address value input to the terminal 55. Is written. A delay gate 63 is inserted before the terminal 56 in order to apply a write trigger to the terminal 56 after the state of the switching terminal 54 is determined.

On the other hand, when the switching terminal 54 is at the L level, the image data of the address designated by the address value input to the terminal 55 is output from the terminals 51 to 53. The switching terminal 54 is provided with a signal that is the logical product of the φ1 signal and the φ2 signal. That is, it becomes H level only when both φ1 signal and φ2 signal are H level. This signal is also used as a control signal for the 3-state bus buffers 57-59. That is, when this signal is at the H level, the image data at the terminals 87 to 89 is used as a buffer for the terminal 51.
Tell ~ 53. When this signal becomes L level, it becomes high impedance, and the signals at the terminals 87 to 89 are disconnected.

The operation of this embodiment will be described with reference to the timing chart shown in FIG. 8. First, FIG. 8 shows the first part of the data of the first line of the image data in the main scanning direction.
The number written in the H level portion of the φ _I timing signal at the terminal 90 is the serial number of the image data, i.
In the j-th pixel on the line, (i−1) × 256 + j. 83 AND which is the logical product of φ1 signal and φ2 signal
The trailing edge of the 82 signal is counted by the counter 40. This count value is output to the terminal 55 of the RAM 50 as an address value, and the row address of the RAM 50 is designated. The 83AND82 signal is input to the write / read switching terminal 54 of the RAM 50, and specifies writing at H level and reading at L level.

First, at time 0, the memory contents of the RAM 50 are all 0.

Next, at time t1, since the 83AND82 signal is at L level, the RAM 50 is read. The image data read from the terminal 53 is 0 in the memory.
The value of 00 (h) becomes 0. At time t2, φ of the terminal 90
_{Since the I} timing signal is at the H level, the bonding pad 101 of the light emitting element array chip C ₀ is
The φ _I signal of the terminal 86 is input, and the φ _I signal of the terminal 53 is input to the bonding pad 101 of the light emitting element array chip C ₁ .

Subsequently, the φ1 signal and the φ2 signal are simultaneously set to H level.
At the time t3 when it is at the level, the 83AND82 signal becomes the H level, the 83AND82 signal enables the 3-state bus buffer 60, and supplies the image data from the terminal 87 to the terminal 53 of the RAM 50. A signal obtained by slightly delaying the 83AND82 signal by the delay gate 63 is input to the terminal 56 during the H level during the writing, and the image data from the terminal 87 is
The data is written to the address 000 (h) specified by the terminal 55 of the RAM 50 in the column connected to the terminal 53.

Next, at time t4, the 83AND82 signal goes low.
The level is reached, and the counter 40 becomes 001 (h) by counting the falling.

Thereafter, the same process is repeated, and as shown in FIG. 8, data 1000100011001 ...
・ Write in sequence.

Looking at this series of operations while paying attention to the memory writing, the image data on the RAM is read out, the image data of the light emitting element array chip is created, and then the counter 40 is operated.
While the value of is the same, writing new data to the same address is repeated. When the shift amount of the light emitting point in the y-axis direction is n lines, if the counter 40 is reset every n × (the number of light emitting points per chip),
Just before n lines, the previously written data will be read.

FIG. 9 shows a timing chart of the third line. The data 1000100110 written in FIG.
It can be seen that 01 ... Is read in order.

As a result, as shown in FIG. 10, one line can be drawn by connecting the front and rear of the light emitting point array.

In the above-described embodiment, the case where the number of light emitting elements transferred in one line time is equal to the number of light emitting elements mounted in one chip has been described, but the present invention is not limited to this. Number of transferred light emitting elements is 1
A plurality of sets may be integrated on one chip.

[0053]

As described above, according to the present invention, in the optical writing head in which the light emitting element array chips are arranged in a zigzag pattern, the image data corresponding to one of the light emitting element array chips which are alternately arranged in a zigzag pattern. Hold it in a memory element,
Since the image data is read from the memory element and output to the light emitting element array chip after a time corresponding to the shift amount in the y-axis direction, it is possible to correct the deviation of the light spot array on the optical drum in the y-axis direction, and the printing quality is good. An optical writing head can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of an optical printer including an optical writing head.

FIG. 2 is a diagram showing a structure of an optical writing head.

FIG. 3 is a self-scanning light-emitting element array chip (2-phase drive 1
It is an equivalent circuit diagram of a basic structure of a point lighting type cathode common type).

FIG. 4 is a diagram showing a state in which light emitting element array chips are arranged in a staggered pattern on a head.

FIG. 5 is a diagram showing a state in which light emitting element array chips according to the present invention are arranged in a staggered pattern on a head.

FIG. 6 is a diagram showing an image drawn when straight line data is directly applied to an optical writing head.

FIG. 7 is a circuit diagram showing an embodiment of a drive circuit for an optical writing head according to the present invention.

FIG. 8 is a timing chart showing the operation of the present embodiment.

FIG. 9 is a timing diagram showing the operation of the present embodiment.

FIG. 10 is a diagram showing an image drawn by the optical writing head according to the present invention.

[Explanation of symbols]

2 Photosensitive drum 4 Charging device 6 Optical writing head 8 Developing device 10 Transfer device 12 Cassette 14 Paper 16 Fixing device 18 Stacker 20 Erase lamp 22 Cleaning device 24 Light emitting element array 26 Rod lens array 28, C _{0 to} C ₅ Self-scanning light emission Element array chip 30, 101-104 Bonding pad 32, 33 Light emitting element 40 Counter 41, 42, 51-53, 54-56 Terminal 50 RAM 57-59 3-state bus buffer 62, 64-69 AND gate 63 Delay gate 70- 76 buffer 80 connector 81 power supply 82 φ2 signal 83 φ1 signal 84 to 89 φ _I signal 90 φ _I light emission timing signal 91 to 96 current limiting resistor

Claims (7)

[Claims] 1. A plurality of light emitting element array chips in which a plurality of light emitting elements are arranged in a row are arranged in a staggered pattern, and the intervals between the light emitting element array chips in a direction orthogonal to the arrangement direction of the light emitting element array chips. In order to hold the image data corresponding to the odd-numbered light emitting element array chips in the drive circuit of the optical writing head that mounts each light emitting element array chip by multiplying the distance on the photosensitive drum that moves in one line time And a memory element having a capacity larger than the value of (the value of the integral multiple) × (the number of light emitting elements transferred in one line time) / 2. 2. The reading of data from the memory device is performed after (time of the integral multiple) × (1 line time) from the time when the first data is written to the odd-numbered light emitting device array chips. The drive circuit of the optical writing head according to claim 1, wherein the drive circuit is used as image data to be written. 3. A plurality of light emitting element array chips in which a plurality of light emitting elements are arranged in a row are arranged in a zigzag pattern, and an interval between the respective light emitting element array chips in a direction orthogonal to the arrangement direction of the light emitting element array chips. In order to hold the image data corresponding to the even-numbered light emitting element array chips in the drive circuit of the optical writing head that mounts each light emitting element array chip by multiplying the distance on the photosensitive drum that moves in one line time And a memory element having a capacity larger than the value of (the value of the integral multiple) × (the number of light emitting elements transferred in one line time) / 2. 4. The data read from the memory device is performed after (time of the integral multiple) × (1 line time) from the time when the first data is written to the even-numbered light emitting device array chips. The drive circuit of the optical writing head according to claim 3, wherein the drive circuit is used as image data to be written. 5. The data read from the memory device until the time of (the integer multiple value) × (1 line time) elapses from the time when the first data is written indicates that no image is written. The optical write head drive circuit according to claim 2, wherein the drive circuit is data. 6. The drive circuit for an optical writing head according to claim 1, wherein the timing of reading data from the memory element is read with reference to a transfer clock signal of the light emitting element. . 7. The light emitting element array chip is a self-scanning light emitting element array chip.
7. The drive circuit for the optical writing head according to any one of 6 above.