JP2010017897A - Light emitting device and exposure system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable an action by a first main scan direction resolution, and to suppress formation of a zigzag pattern when acting in a second main scan direction resolution of half of the first main scan direction resolution. <P>SOLUTION: In a full resolution mode wherein an output resolution in a main scan direction is 1,200 dpi, odd-numbered and even-numbered lighting signals ϕ1 and ϕ2 are supplied to a light emitting chip C1. Consequently, all light emitting thyristors L1-L256 of the light emitting chip C1 are brought while being able to be turned on. On the other hand, in a half resolution mode wherein the output resolution in the main scan direction becomes half of that of the full resolution mode, only an odd-numbered lighting signal ϕI1 is supplied to the light emitting chip C1. In consequence, while odd-numbered light emitting thyristors L1, L3, ..., L255 prepared in the light emitting chip C1 are brought in the state of being able to be turned on, even-numbered light emitting thyristors L2, L4, ..., L256 are substantially brought while being unable to be turned on. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a light emitting device for sequentially lighting a plurality of light emitting elements, and an exposure apparatus including a plurality of light emitting chips for sequentially lighting a plurality of light emitting elements.

  In an image forming apparatus such as a printer or a copying machine using an electrophotographic method, light emitting elements such as LEDs (Light Emitting Diodes) have recently been arranged in a line as an exposure apparatus that exposes an image carrier such as a photosensitive drum. The one using the light emitting element array is adopted.

  As a prior art described in the publication, there is a so-called self-scanning light emitting element array (see Patent Document 1). In this self-scanning light emitting element array, a thyristor (transfer thyristor) is used as a switch element for lighting each LED in the light emitting chip. In the self-scanning light-emitting element array, the LED itself is also composed of a thyristor (light-emitting thyristor). In the self-scanning light emitting element array, each transfer thyristor is sequentially turned on by two input transfer signals, and the light emitting thyristors corresponding to the turned-on transfer thyristors are set in a state where they can be sequentially turned on one by one. On the other hand, one common wiring connected to the anode terminal (or cathode terminal) of each light emitting thyristor is set to a constant potential, and the other common wiring connected to the cathode terminal (or anode terminal) of each light emitting thyristor is set to By supplying a lighting signal, the light-emitting thyristor that is set in a lighting-enabled state is instructed to be turned on / off. In Patent Document 1, two self-scanning light-emitting element arrays are formed per light-emitting chip, and two light-on signals are supplied to each light-emitting chip, so that one light-emitting chip can be turned on simultaneously. It is described that the number of light emitting thyristors is two.

  As another prior art described in another publication, in the self-scanning light emitting element array, two light emitting thyristors are connected to each transfer thyristor, and the first write signal is applied to the light emitting thyristors arranged in an odd number. And the second write signal is supplied to even-numbered light-emitting thyristors, so that there are two light-emitting thyristors that can be turned on simultaneously in one light-emitting chip (patent) Reference 2).

JP 2007-125785 A Japanese Patent Laid-Open No. 2001-232849

  By the way, with the recent increase in image quality of image forming apparatuses, output resolution in the main scanning direction (referred to as main scanning direction resolution) tends to be higher. For this reason, the resolution in the main scanning direction, which was 600 dpi for example in the conventional machine, has become 1200 dpi or even 2400 dpi. In the exposure apparatus using the light emitting element array, it is necessary to set the number of light emitting elements and the arrangement interval according to the resolution in the main scanning direction. For example, when the resolution in the main scanning direction is 1200 dpi (dot per inch), the number of light emitting elements is doubled and the arrangement interval of the light emitting elements is halved as compared with the case where the resolution in the main scanning direction is 600 dpi. There is a need.

  Here, one exposure apparatus uses an image forming apparatus that forms an image with a first main scanning direction resolution (for example, 1200 dpi), and a second main scanning direction resolution (for example, half the first main scanning direction resolution). It may be shared with an image forming apparatus that forms an image at 600 dpi).

However, for example, when a light-emitting chip having one self-scanning light-emitting element array is used, it is necessary to change the lighting signal supply condition so that the lighting signal is supplied every other light-emitting thyristor. The drive circuit for driving the type light emitting element array becomes large-scale.
For example, when a light emitting chip having two self-scanning light emitting element arrays is used and only one lighting signal is supplied to the light emitting chip, the self-scanning light emitting element array on the side to which the lighting signal is supplied is used. An image in which the length in the scanning direction is halved is formed, resulting in a situation in which no image is formed by the self-scanning light emitting element array on the side where the lighting signal is not supplied.

  On the other hand, for example, in a light-emitting chip having one self-scanning light-emitting element array, when a configuration in which two light-emitting thyristors are connected to one transfer thyristor and only one lighting signal is supplied, the light-emitting thyristor Can be turned on every other, and an image corresponding to the original image data can be obtained. However, in this case, since the position of the light-emitting thyristor that can be turned on moves in one direction along the light-emitting element array, a linear shape along the main scanning direction is used by using an exposure apparatus in which a plurality of light-emitting chips are arranged. When a thin line image is formed, a zigzag pattern with the length in the main scanning direction of the light emitting element array as a period becomes conspicuous, and there is a possibility that the image quality is deteriorated.

  The present invention can operate at the first main scanning direction resolution, and suppresses the generation of zigzag patterns when operating at the second main scanning direction resolution which is half the first main scanning direction resolution. For the purpose.

  According to the first aspect of the present invention, a light emitting element array having a plurality of light emitting elements which are arranged in a line and whose lighting / non-lighting is controlled by a lighting signal is provided corresponding to each of the plurality of light emitting elements. A switch element array having a plurality of switch elements that can turn on the corresponding light-emitting elements by being set to a state, and the light-emitting element array is a light-emitting element arranged in an odd number in the light-emitting element array A first light emitting element group configured to be supplied with a common first lighting signal as the lighting signal, and light emitting elements arranged in an even number in the light emitting element row, and a common second lighting as the lighting signal. A second light emitting element group to which a signal is supplied, and the switch element row includes a light emitting element belonging to the first light emitting element group and a light emitting element belonging to the second light emitting element group. A first switch element group for setting each light emitting element of the one end side light emitting element group configured by the light emitting elements arranged on one end side of the light emitting element row in a state capable of sequentially emitting light along a first direction; Of the light emitting elements belonging to the first light emitting element group and the light emitting elements belonging to the second light emitting element group, each light emission of the other end side light emitting element group constituted by the light emitting elements arranged on the other end side of the light emitting element row. A light emitting device comprising: a second switch element group that sets elements in a state capable of sequentially emitting light along a second direction opposite to the first direction.

According to a second aspect of the present invention, there is provided a lighting signal generator that supplies the first lighting signal to the first light emitting element group and supplies the second lighting signal to the second light emitting element group, and the lighting signal generator. A first mode in which both the first lighting signal and the second lighting signal are supplied, and a second mode in which the lighting signal generator supplies only either the first lighting signal or the second lighting signal. The light emitting device according to claim 1, further comprising a switching unit that switches between the modes.
The invention described in claim 3 is characterized in that the number of light emitting elements constituting the first light emitting element group and the number of light emitting elements constituting the second light emitting element group are an even number and the same number. Or it is a light-emitting device of 2.
A fourth aspect of the present invention is the light emitting device according to any one of the first to third aspects, wherein the plurality of light emitting elements and the plurality of switch elements are formed of thyristors.

  According to a fifth aspect of the present invention, a plurality of first transfer thyristors are arranged in a line, and the gates of adjacent first transfer thyristors are connected to each other so that current flows in one direction by a diode. A first thyristor in which an anode or a cathode of a transfer thyristor is alternately connected in the arrangement direction to a first transfer signal terminal to which a first transfer signal is input and a second transfer signal terminal to which a second transfer signal is input. A transfer block and a plurality of second transfer thyristors are arranged in a line adjacent to the first transfer block, and a current flows in the direction opposite to the one direction by a diode between the gates of the adjacent second transfer thyristors. The second transfer thyristors are connected so that the anodes or cathodes of the second transfer thyristors are alternately connected to the first transfer signal terminal and the second transfer signal terminal in the arrangement direction. A second transfer block and a plurality of first light-emitting thyristors arranged in a line, the gate of each first light-emitting thyristor, the gate of the odd-numbered first transfer thyristor and the second transfer in the first transfer block. The gates of the odd-numbered second transfer thyristors of the block are connected to each other, and the first light-emitting block adjacent to the first light-emitting block in which a common first lighting signal is supplied to the anode or the cathode of each first light-emitting thyristor. A plurality of second light-emitting thyristors are respectively arranged between the light-emitting thyristors, and each second light-emitting thyristor gate, the even-numbered first transfer thyristor gate of the first transfer block, and the even-numbered second transfer block. Are connected to the gates of the second transfer thyristors, and the anode or cathode of each second light-emitting thyristor is shared. The second lighting signal is a light emitting device including a can and a second light-emitting blocks to be supplied.

  According to a sixth aspect of the present invention, a plurality of first transfer thyristors are arranged in a line, and the gates of adjacent first transfer thyristors are connected so that current flows in one direction by a diode, respectively. A first thyristor in which an anode or a cathode of a transfer thyristor is alternately connected in the arrangement direction to a first transfer signal terminal to which a first transfer signal is input and a second transfer signal terminal to which a second transfer signal is input. A transfer block and a plurality of second transfer thyristors are arranged in a line adjacent to the first transfer block, and a current flows in the direction opposite to the one direction by a diode between the gates of the adjacent second transfer thyristors. A second transfer block in which the second transfer thyristor is connected to the first transfer signal terminal and the second transfer signal terminal alternately. And a plurality of first light-emitting thyristors arranged in a line, and a first light-emitting block in which a common first lighting signal is supplied to the anode or cathode of each first light-emitting thyristor, and a plurality of second light-emitting elements The first light emitting thyristor is alternately arranged with the plurality of first light emitting thyristors, and each of the first light emitting thyristors includes a second light emitting block to which a common second lighting signal is supplied. Among the plurality of first light-emitting thyristors constituting the light-emitting block, the gates of some of the first light-emitting thyristors are connected to the gates of the first transfer thyristors constituting the first transfer block, respectively, and the remaining first A gate of one light emitting thyristor is connected to each gate of the second transfer thyristor constituting the second transfer block, and the second light emitting block is connected to the second light emitting thyristor. Among the plurality of second light-emitting thyristors that are formed, the gates of some of the second light-emitting thyristors constitute gates of the first transfer thyristors that constitute the first transfer block and that are not connected to the first light-emitting thyristor. A light-emitting device that is connected to each other and that connects the gates of the remaining second light-emitting thyristors to the second transfer thyristor that constitutes the second transfer block and that is not connected to the first light-emitting thyristor. It is.

According to a seventh aspect of the present invention, in the first transfer block, a gate of each of the first transfer thyristors is connected to a common wiring through a resistor, and each second transfer in the second transfer block 7. The light emitting device according to claim 5, wherein a gate of the thyristor is connected to the common wiring through a resistor.
According to an eighth aspect of the present invention, a lighting signal generator that supplies the first lighting signal to the first light-emitting block and supplies the second lighting signal to the second light-emitting block, and the lighting signal generator is the A first mode that supplies both the first lighting signal and the second lighting signal, and a second mode in which the lighting signal generator supplies only one of the first lighting signal or the second lighting signal. The light-emitting device according to claim 5, further comprising a switching unit that switches between the two.
The invention according to claim 9 is characterized in that the number of light-emitting thyristors constituting the first light-emitting block and the number of light-emitting thyristors constituting the second light-emitting block are an even number and the same number. The light-emitting device according to any one of the above.

According to a tenth aspect of the present invention, there is provided a charged image carrier including a light emitting section in which a plurality of light emitting chips each having a light emitting element array in which a plurality of light emitting elements are arranged in the main scanning direction are arranged in the main scanning direction. The light-emitting chip is provided corresponding to each of the plurality of light-emitting elements, and a plurality of switch elements that turn on the corresponding light-emitting elements by being set to an on state are provided. A first light emitting element group that is configured by light emitting elements arranged in an odd number in the light emitting element array and to which a common first lighting signal is supplied as a lighting signal; A second light emitting element group which is configured by even-numbered light emitting elements in the light emitting element array and to which a common second lighting signal is supplied as the lighting signal. Among the light emitting elements belonging to the first light emitting element group and the light emitting elements belonging to the second light emitting element group, each light emitting element of the one end side light emitting element group constituted by the light emitting elements arranged on one end side of the light emitting element row is A first switch element group that is set in a state capable of sequentially emitting light along the first direction;
Of the light emitting elements belonging to the first light emitting element group and the light emitting elements belonging to the second light emitting element group, each of the other end side light emitting element groups configured by light emitting elements arranged on the other end side of the light emitting element row. An exposure apparatus comprising: a second switch element group configured to sequentially set light emitting elements in a state capable of emitting light along a second direction opposite to the first direction.

In the invention described in claim 11, the light emitting chips arranged in an odd number in the main scanning direction and the light emitting chips arranged in an even number in the light emitting section are arranged in a staggered manner by being shifted in the sub scanning direction. In addition, the odd-numbered light emitting chips and the even-numbered light emitting chips are attached in the reverse direction in the sub-scanning direction, and supply the first lighting signal to the first light emitting element group, A lighting signal generator that supplies a second lighting signal to the second light emitting element group, a first mode in which the lighting signal generator supplies both the first lighting signal and the second lighting signal, and the lighting A switching unit that switches between a second mode in which the signal generation unit supplies only one of the first lighting signal and the second lighting signal, and the switching unit in the second mode, The first lighting signal or the second lighting signal is supplied to the odd-numbered light emitting chips, and the odd-numbered light emitting chips are supplied to the even-numbered light emitting chips. 11. The exposure apparatus according to claim 10, wherein the second lighting signal or the first lighting signal that is not supplied is supplied.
The invention according to claim 12 is characterized in that the number of light emitting elements constituting the first light emitting element group and the number of light emitting elements constituting the second light emitting element group in the light emitting chip are an even number and the same number. An exposure apparatus according to claim 10 or 11.
According to a thirteenth aspect of the present invention, in the exposure apparatus according to any one of the tenth to twelfth aspects, the plurality of light emitting elements and the plurality of switch elements constituting the light emitting chip are formed of thyristors. It is.

According to the first aspect of the present invention, light can be emitted with the first main scanning direction resolution, and zigzag when emitting light with the second main scanning direction resolution which is half of the first main scanning direction resolution. The occurrence of patterns can be suppressed.
According to the second aspect of the present invention, it is possible to easily switch between the first main scanning direction resolution and the second main scanning direction resolution as compared with the case where this configuration is not provided.
According to the third aspect of the present invention, only one light emitting element capable of emitting light in the same light emitting element group can be provided.
According to the fourth aspect of the present invention, it is possible to speed up the switching of the light emitting elements that can be turned on as compared with the case where the present configuration is not provided.
According to the fifth aspect of the present invention, light can be emitted with the first main scanning direction resolution, and zigzag when emitting light with the second main scanning direction resolution which is half of the first main scanning direction resolution. The occurrence of patterns can be suppressed.
According to the sixth aspect of the present invention, the light can be emitted with the first main scanning direction resolution, and zigzag when the light is emitted with the second main scanning direction resolution which is half of the first main scanning direction resolution. The occurrence of patterns can be suppressed.
According to the seventh aspect of the invention, the transfer operation from the transfer thyristor to another transfer thyristor adjacent to the thyristor can be stabilized.
According to the eighth aspect of the present invention, it is possible to easily switch between the first main scanning direction resolution and the second main scanning direction resolution as compared with the case where this configuration is not provided.
According to the ninth aspect of the present invention, only one light emitting element capable of emitting light in the same light emitting block can be provided.
According to the tenth aspect of the present invention, the image carrier can be exposed at the first main scanning direction resolution and exposed at the second main scanning direction resolution which is half of the first main scanning direction resolution. The generation of zigzag patterns can be suppressed when performing.
According to the invention described in claim 11, when the exposure is performed with the first main scanning direction resolution, the interval between the light emitting thyristors that can be turned on can be made constant within the light emitting chip and between the adjacent light emitting chips. In addition, when the exposure is performed with the second main scanning direction resolution, the interval between the light emitting thyristors that can be turned on can be made constant within the light emitting chips and between the light emitting chips.
According to the twelfth aspect of the present invention, only one light emitting element that can emit light within the same light emitting element group of one light emitting chip can be provided.
According to the thirteenth aspect of the present invention, it is possible to speed up the switching of the light emitting elements that can be turned on as compared with the case where this configuration is not provided.

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
<Embodiment 1>
FIG. 1 is a diagram illustrating an example of the overall configuration of an image forming apparatus 1 to which the exemplary embodiment is applied. The image forming apparatus 1 shown in FIG. 1 includes an image forming process unit 10 that forms an image corresponding to image data of each color, a control unit 30 that controls the operation of the entire image forming apparatus 1, a personal computer, an image reading device, and the like. An image processing unit 35 is connected to an external device (not shown) and performs image processing on image data received from these devices.

  The image forming process unit 10 includes four image forming units 11 (specifically, 11Y, 11M, 11C, and 11K) that are arranged at a predetermined interval. Each image forming unit 11 includes a photosensitive drum 12 as an example of an image carrier on which a photosensitive layer (not shown) is formed, a charger 13 for charging the photosensitive drum 12, and a photosensitive member charged by the charger 13. An LED print head (LPH) 14 as an example of an exposure device that exposes the drum 12 based on image data, a developing device 15 that develops an electrostatic latent image formed on the photosensitive drum 12, and the surface of the photosensitive drum 12 A cleaner 16 for cleaning is provided. Here, each image forming unit 11 is configured in substantially the same manner except for the toner stored in the developing device 15. Each image forming unit 11 forms yellow (Y), magenta (M), cyan (C), and black (K) toner images.

  Further, the image forming process unit 10 circulates through a position facing each photoconductive drum 12 of each image forming unit 11, and primary transfer disposed so as to face each photoconductive drum 12 across the intermediate transfer belt 20. A roll 21, a secondary transfer roll 22 disposed to face the intermediate transfer belt 20, and a fixing device 45 that fixes an unfixed image on a sheet after the secondary transfer by heating and pressing.

  In the image forming apparatus 1, the image forming process unit 10 performs an image forming operation based on various control signals supplied from the control unit 30. Then, under the control of the control unit 30, the image data input from the external device is subjected to image processing by the image processing unit 35 and is supplied to each image forming unit 11. For example, in the black (K) image forming unit 11K, the photosensitive drum 12 is charged to a predetermined potential by the charger 13 while rotating in the direction of arrow A, and the image transmitted from the image processing unit 35 is transmitted. The exposure is performed by the LPH 14 that emits light based on the data. As a result, an electrostatic latent image related to a black (K) color image is formed on the photosensitive drum 12. The electrostatic latent image formed on the photosensitive drum 12 is developed by the developing device 15, and a black (K) toner image is formed on the photosensitive drum 12. Similarly, yellow (Y), magenta (M), and cyan (C) toner images are formed in the image forming units 11Y, 11M, and 11C, respectively.

  The respective color toner images formed by the respective image forming units 11 are sequentially electrostatically attracted by the primary transfer roll 21 onto the intermediate transfer belt 20 moving in the arrow B direction, and become a composite toner image in which the respective color toners are superimposed. . The synthetic toner image on the intermediate transfer belt 20 is conveyed to a region (secondary transfer portion T) where the secondary transfer roll 22 is disposed as the intermediate transfer belt 20 moves. The paper is supplied from the paper holding unit 40 to the secondary transfer unit T in accordance with the timing at which the composite toner image is conveyed to the secondary transfer unit T. The composite toner image is collectively electrostatically transferred onto the conveyed paper by the transfer electric field formed by the secondary transfer roll 22 in the secondary transfer portion T.

  Thereafter, the sheet on which the synthetic toner image has been electrostatically transferred is peeled off from the intermediate transfer belt 20 and conveyed to the fixing device 45. The synthesized toner image on the paper conveyed to the fixing device 45 is fixed on the paper by the fixing device 45 by a fixing process using heat and pressure. Then, the sheet on which the fixed image is formed is conveyed to the paper discharge stacking unit 41 provided in the discharge unit of the image forming apparatus 1. On the other hand, the toner remaining on the intermediate transfer belt 20 after the secondary transfer is removed from the surface of the intermediate transfer belt 20 by the belt cleaner 25 after the completion of the secondary transfer.

  FIG. 2 is a cross-sectional view showing the configuration of the LPH 14. The LPH 14 includes a housing 61, a light emitting unit 63 having a plurality of LEDs (light emitting thyristors in the present embodiment), a light emitting unit 63, a signal generation circuit 100 that drives the light emitting unit 63 (see FIG. 5 in the subsequent stage), and the like. A circuit board 62, a rod lens array 64 for imaging light emitted from the light emitting unit 63 on the surface of the photosensitive drum 12, and a holder 65 for supporting the rod lens array 64 and shielding the light emitting unit 63 from the outside. .

  The housing 61 is made of metal, for example, and supports the circuit board 62. The rod lens array 64 is disposed along the axial direction of the photosensitive drum 12 and is formed with a width in the rotational direction of the photosensitive drum 12. The holder 65 is disposed along the axial direction of the photosensitive drum 12 and seals the light emitting unit 63. The holder 65 supports the housing 61 and the rod lens array 64, and is set so that the light emitting point of the light emitting unit 63 and the focal plane of the rod lens array 64 coincide.

  FIG. 3A is a top view of the circuit board 62 and the light emitting unit 63 in the LPH 14, and FIG. 3B is a top view of the rod lens array 64 and the holder 65 in the LPH 14. As shown in FIG. 3A, the light emitting unit 63 includes 60 light emitting chips C (C1 to C60) as an example of a light emitting device on a circuit board 62 in a staggered pattern in two rows in the sub-scanning direction. It is arranged and configured. In the light emitting unit 63, odd-numbered light emitting chips C1, C3,..., C59 arranged in a line in the main scanning direction on the upstream side in the sub scanning direction are referred to as first chip rows 63a and on the downstream side in the sub scanning direction. The even-numbered light emitting chips C2,..., C58, C60 arranged in a line in the main scanning direction are referred to as a second chip line 63b.

  Each of the light emitting chips C1 to C60 is provided with 256 light emitting thyristors as described later, and the light emitting unit 63 as a whole is provided with 15360 light emitting thyristors. The distance from the outer end of the light emitting chip C1 (light emitting element array 71 described later) to the outer end of the light emitting chip C60 (light emitting element array 71 described later) (the length in the main scanning direction of the light emitting unit 63) is A3. In order to cope with the image formation on the Nobi paper P, it is set to 324 mm. Therefore, adjacent light emitting thyristors are arranged at equal intervals of about 21.15 μm, respectively, and the resolution in the main scanning direction of the LPH 14 is 1200 dpi (dot per inch).

  Further, as shown in FIG. 3B, the rod lens array 64 is obtained by holding a plurality of rod lenses 64a in a holder 65 in a state of being arranged in two rows in the sub-scanning direction so as to be staggered. It is configured. Each rod lens 64a has, for example, a cylindrical shape, and is composed of a refractive index distribution type lens that has a refractive index distribution in the radial direction thereof and forms an erecting equal-magnification real image. An example of such a gradient index lens is a SELFOC (trademark of Nippon Sheet Glass Co., Ltd.) lens array.

  FIG. 4 is an enlarged view of a connection portion of the light emitting chips C1, C2, and C3 in the light emitting unit 63. As shown in FIG. Here, the light emitting chips C1 to C60 all have the same configuration. For example, when the light emitting chip C2 is taken as an example, a rectangular chip substrate 70 and the surface of the chip substrate 70 are arranged in a line along the longitudinal direction. And a light emitting element array 71 arranged. The light emitting element array 71 has 256 light emitting thyristors arranged in a line in the main scanning direction. The light emitting element array 71 is attached to a position biased to one side of the surface of the chip substrate 70 in the short direction. The light emitting chips C1, C3 (..., C59) constituting the first chip row 63a and the light emitting chips C2 (..., C58, C60) constituting the second chip row 63b are opposite in the sub-scanning direction. As a result, the light emitting element array 71 constituting the first chip row 63a and the light emitting element array 71 constituting the second chip row 63b come close to each other in the sub scanning direction in the sub scanning direction. ing. As shown in FIG. 4, at the end boundary of the light emitting element array 71 arranged in each of the light emitting chips C1, C2, and C3, the light emitting element array 71 is connected to the light emitting chips C1 and C2 and the light emitting chip C2. , C3 are arranged so as to be continuous in the main scanning direction.

FIG. 5 is a diagram showing the configuration of the signal generation circuit 100 mounted on the circuit board 62 (see FIG. 2) and the wiring configuration of the circuit board 62.
The signal generation circuit 100 receives various control signals such as a line synchronization signal Lsync, video data Vdata, a clock signal clk, and a reset signal RST from the image processing unit 35 (see FIG. 1). The signal generation circuit 100 performs, for example, rearrangement of video data Vdata, correction of output values, and the like based on various control signals input from the outside, and turns on the light emitting chips C (C1 to C60). A lighting signal generator 110 that outputs signals φI (φI1 to φI120) is provided. In each light-emitting chip C, the 256 light-emitting thyristors to be mounted are divided into two sets of 128, and lighting control is performed with each set (128 light-emitting thyristors) as one thread. Therefore, two light-on signals φI (for example, φI1 and φI2 in the light-emitting chip C1) are supplied to each of the light-emitting chips C1 to C60. The circuit board 62 is provided with a changeover switch 130 as an example of a switching unit for setting operation switching of the lighting signal generation unit 110 in the signal generation circuit 100.

  The signal generation circuit 100 outputs a start transfer signal φS, a first transfer signal φ1, and a second transfer signal φ2 to each of the light emitting chips C1 to C60 based on various control signals input from the outside. A transfer signal generator 120 is provided.

  The circuit board 62 is provided with a power supply line 101 for power supply Vcc = −5.0 V connected to the SUB terminals of the light emitting chips C1 to C60 and a power supply line 102 for grounding connected to the GND terminal. Yes. Further, the circuit board 62 includes a start transfer signal line 103 and a first transfer signal line 104 for transmitting the start transfer signal φS, the first transfer signal φ1, and the second transfer signal φ2 from the transfer signal generator 120 of the signal generation circuit 100. A second transfer signal line 105 is also provided. Furthermore, 120 lighting signals for transmitting two lighting signals φI (φI1 to φI120) to the light emitting chips C (C1 to C60) from the lighting signal generation unit 110 of the signal generation circuit 100 to the circuit board 62. Lines 106 (106_1 to 106_120) are also provided. The circuit board 62 is provided with 120 lighting current limiting resistors RID for preventing an excessive current from flowing through the 120 lighting signal lines 106 (106_1 to 106_120). Each of the lighting signals φI1 to φI120 can take two states of high level (H) and low level (L) as described later. The potential is −5.0 V at the low level and ± 0.0 V at the high level.

  FIG. 6 is a diagram for explaining a circuit configuration of the light emitting chip C. FIG. Here, the light emitting chip C1 will be described as an example. However, as described above, the other light emitting chips C2 to C60 also have the same configuration as the light emitting chip C1.

  The light emitting chip C1 includes 256 transfer thyristors S1 to S256 as an example of a switch element, and 256 light emitting thyristors L1 to L256 as an example of a light emitting element. The light emitting thyristors L1 to L256 have the same pnpn connection as the transfer thyristors S1 to S256, and function as light emitting diodes (LEDs) by using the pn connection therein. The light emitting chip C1 includes 254 diodes D1 to D254 and 256 resistors R1 to R256. Further, the light emitting chip C1 includes transfer current limiting resistors R1A and R2A for preventing an excessive current from flowing through the signal lines to which the first transfer signal φ1, the second transfer signal φ2, and the start transfer signal φS are supplied. , R3A. The light emitting thyristors L1 to L256 constituting the light emitting element array 71 are arranged in the order of L1, L2,..., L255, and L256 from the left side in the drawing to form a light emitting element array, that is, the light emitting element array 71. The transfer thyristors S1 to S256 are also arranged in the order of S1, S2,..., S255, S256 from the left side in the drawing, and form a switch element array. Furthermore, the diodes D1 to D254 are also arranged in the order of D1, D2,..., D253, D254 from the left in the drawing. Furthermore, the resistors R1 to R256 are also arranged in the order of R1, R2,... R255, R256 from the left in the drawing.

  The light emitting chip C1 includes two light emitting blocks, that is, a first light emitting block LB1 and a second light emitting block LB2. Here, the first light-emitting block LB1 as an example of the first light-emitting element group includes light-emitting thyristors L1, L3,..., L253, and L255 that are odd-numbered in the main scanning direction. On the other hand, the second light emitting block LB2 as an example of the second light emitting element group includes light emitting thyristors L2, L4,..., L254, L256 that are even-numbered in the main scanning direction. In this embodiment, one end side light emitting element group is formed by 128 light emitting thyristors L1 to L128 arranged on the left side (one end side) of the light emitting element array 71, and the right side of the light emitting element array 71 in the figure. The other end side light emitting element group is formed by 128 light emitting thyristors L129 to L256 arranged on the other end side. In the present embodiment, the odd-numbered light emitting thyristors L1, L3,..., L255 each function as a first light-emitting thyristor, and the even-numbered light emitting thyristors L2, L4,. is doing.

  The light emitting chip C1 includes two transfer blocks, that is, a first transfer block TB1 and a second transfer block TB2. Here, the first transfer block TB1 as an example of the first switch element group includes 128 transfer thyristors S1 to S128, 127 diodes D1 to D127, and 128 resistors R1 to R128 on the left side in the drawing. Is done. On the other hand, the second transfer block TB2 as an example of the second switch element group includes 128 transfer thyristors S129 to S256, 127 diodes D128 to D254, and 128 resistors R129 to R256 on the right side in the drawing. The In the present embodiment, the 128 transfer thyristors S1 to S128 arranged on the left side in the drawing each function as the first transfer thyristor, and the 128 transfer thyristors S129 to S256 arranged on the right side in the drawing are the first ones. It functions as a 2-transfer thyristor.

Next, electrical connection of each element in the light emitting chip C1 will be described.
The anode terminal of each transfer thyristor S1 to S256 is connected to the GND terminal. A power supply line 102 (see FIG. 5) is connected to the GND terminal and grounded.

  The odd-numbered transfer thyristors S1, S3,..., S127 in the first transfer block TB1 and the even-numbered transfer thyristors S130, S254, S256 in the second transfer block TB2 have transfer current limiting resistors R1A. To the φ1 terminal as an example of the first transfer signal input terminal. The first transfer signal line 104 (see FIG. 5) is connected to the φ1 terminal, and the first transfer signal φ1 is supplied.

  On the other hand, the cathode terminals of the even-numbered transfer thyristors S2, S4,..., S128 in the first transfer block TB1 and the odd-numbered transfer thyristors S129, ... S253, S255 in the second transfer block TB2 are connected via the transfer current limiting resistor R2A. Are connected to a φ2 terminal as an example of the second transfer signal input terminal. The second transfer signal line 105 (see FIG. 5) is connected to the φ2 terminal, and the second transfer signal φ2 is supplied.

  The gate terminals of the transfer thyristors S1 to S256 are connected to the SUB terminals via resistors R1 to R256 provided corresponding to the transfer thyristors S1 to S256, respectively. A power supply line 101 (see FIG. 5) is connected to the SUB terminal, and a power supply voltage Vcc (−5.0 V) is supplied.

  Furthermore, the gate terminals of the transfer thyristors S1 to S256 are connected to the gate terminals of the corresponding light emitting thyristors L1 to L256, respectively, on a one-to-one basis.

  Here, in the first transfer block TB1, the anode terminals of the diodes D1 to D127 are connected to the gate terminals of the transfer thyristors S1 to S127, and the cathode terminals of the diodes D1 to D127 are adjacent to the right side. The transfer thyristors S2 to S128 are connected to the gate terminals. That is, the diodes D1 to D127 are connected in series across the gate terminals of the transfer thyristors S1 to S128.

  On the other hand, in the second transfer block TB2, the anode terminals of the diodes D128 to D254 are connected to the gate terminals of the transfer thyristors S130 to S256, and the cathode terminals of these diodes D128 to D254 are each adjacent to the left side. The thyristors S129 to S255 are connected to the gate terminals. That is, the diodes D128 to D254 are connected in series with the gate terminals of the transfer thyristors S129 to S256 interposed therebetween.

  The anode terminal of the diode D1 provided at the left end of the first transfer block TB1 (the gate terminal of the transfer thyristor S1) and the anode terminal of the diode D254 provided at the right end of the second transfer block TB2 (of the transfer thyristor S256) The gate terminal) is connected to the φS terminal via the transfer current limiting resistor R3A. The φS terminal is supplied with a start transfer signal φS via a start signal transfer line 103 (see FIG. 5).

  Here, in the diodes D1 to D127 of the first transfer block TB1, the forward current flows in one direction from the left to the right in the figure, whereas in the diodes D128 to D254 of the second transfer block TB2, The forward current flows in one direction from right to left in the figure. That is, the currents flowing through the diodes D1 to D127 and the diodes D128 to D254 in the first transfer block TB1 and the second transfer block TB2 are opposite to each other.

  Next, the anode terminals of the light emitting thyristors L1 to L256 are connected to the GND terminal in the same manner as the anode terminals of the transfer thyristors S1 to S256.

  Further, the cathode terminals of odd-numbered light emitting thyristors L1, L3,..., L253, L255 constituting the first light emitting block LB1 are connected to the φI1 terminal. A lighting signal line 106 (in the case of the light emitting chip C1, the lighting signal line 106_1: see FIG. 5) is connected to the φI1 terminal, and an odd-numbered lighting signal φI1 is supplied. Note that other odd-numbered lighting signals φI3,..., ΦI117 are respectively supplied to the φI3,..., ΦI117 terminals of the other odd-numbered light emitting chips C3,.

  On the other hand, the cathode terminals of the even-numbered light emitting thyristors L2, L4,..., L254, L256 constituting the second light emitting block LB2 are connected to the φI2 terminal. A lighting signal line 106 (in the case of the light emitting chip C1, the lighting signal line 106_2: see FIG. 5) is connected to the φI2 terminal, and the even-numbered lighting signal φI2 is supplied. Note that other even-numbered lighting signals φI4,..., ΦI120 are supplied to the φI4,..., ΦI120 terminals of the other even-numbered light emitting chips C4,.

  FIG. 7 is a diagram for explaining the operation switching of the lighting signal generator 110 by the changeover switch 130 shown in FIG. When the changeover switch 130 is set to ON, the lighting signal generation unit 110 has two odd-numbered and even-numbered lighting signals for each of the light emitting chips C1 to C60 (in the case of the light emitting chip C1, the lighting signal φI1, φI2) is supplied. On the other hand, when the change-over switch 130 is set to OFF, the lighting signal generator 110 generates an odd number for the odd-numbered light emitting chips C1, C3,..., C59 constituting the first chip row 63a (see FIG. 3). Only the lighting signal (lighting signal φI1 in the case of the light-emitting chip C1) is supplied, and the even-numbered lighting signal (lighting signal φI2 in the case of the light-emitting chip C1) is not supplied. Further, when the changeover switch 130 is set to OFF, the lighting signal generation unit 110 is an even number for the even-numbered light emitting chips C2, C4,..., C60 constituting the second chip row 63b (see FIG. 3). Only the first lighting signal (lighting signal φI4 in the case of the light-emitting chip C2) is supplied, and the odd-numbered lighting signal (lighting signal φI3 in the case of the light-emitting chip C2) is not supplied.

  Here, the changeover switch 130 is set to ON when the LPH 14 is attached to the image forming apparatus 1 having a main scanning direction resolution of 1200 dpi, and the changeover switch 130 is set to OFF. This is a case where the image forming apparatus 1 is mounted with a half-direction resolution of 600 dpi.

  Next, the image processing unit 35 (see FIG. 1) of the image forming apparatus 1 outputs video data Vdata having a main scanning direction resolution of 1200 dpi while referring to the timing charts shown in FIGS. 5, 6, and 8 described above. The operation of the light emitting unit 63 in the case of having the function to perform will be described. Therefore, it is assumed that the changeover switch 130 provided in the LPH 14 is set to ON. In the following description, the operation of the light emitting unit 63 in a state where the changeover switch 130 is set to ON is referred to as a full resolution mode (corresponding to the first mode). The timing chart shown in FIG. 8 shows a case where all the light emitting thyristors L1 to L256 are turned on in each of the light emitting chips C1 to C60 constituting the light emitting unit 63.

  When instructing the light emitting chips C1 to C60 to start the operation, the transfer signal generation unit 120 changes the start transfer signal φS from the low level (L) to the high level (H). As a result, the high-level start transfer signal φS is supplied to the gate terminal of the transfer thyristor S1 of the first transfer block TB1 and the gate terminal of the transfer thyristor S256 of the second transfer block TB2 of each of the light emitting chips C1 to C60. At this time, in the first transfer block TB1, the start transfer signal φS is also supplied to the gate terminals of the other transfer thyristors S2 to S128 via the diodes D1 to D127. However, since a voltage drop occurs in each of the diodes D1 to D127, the voltage applied to the gate terminal of the transfer thyristor S1 is the highest in the first transfer block TB1. On the other hand, in the second transfer block TB2, the start transfer signal φS is also supplied to the other transfer thyristors S255 to S129 via the diodes D254 to D128. However, since a voltage drop occurs in the diodes D254 to D128, the voltage applied to the gate terminal of the transfer thyristor S256 is the highest in the second transfer block TB2.

  Then, in a state where the start transfer signal φS is at the high level, the transfer signal generation unit 120 changes the first transfer signal φ1 from the high level to the low level. Further, the transfer signal generation unit 120 changes the second transfer signal φ2 from the low level to the high level after the first period ta has elapsed since the first transfer signal φ1 was set to the low level.

  As described above, when the first transfer signal φ1 having the low level is supplied in the state where the start transfer signal φS is at the high level, the first transfer block TB1 of each of the light emitting chips C1 to C60 has the low level first. Among odd-numbered transfer thyristors S1, S3,..., S127 to which one transfer signal φ1 is supplied, the transfer thyristor S1 having the highest gate terminal voltage and a gate voltage equal to or higher than the threshold value is turned on. On the other hand, in the second transfer block TB2, among the even-numbered transfer thyristors S130,..., S254, S256 to which the low-level first transfer signal φ1 is supplied, the gate terminal voltage is the highest, The transfer thyristor S256 is turned on. At this time, since the second transfer signal φ2 is at the high level, the voltages of the cathode terminals of the even-numbered transfer thyristors S2, S4,..., S128 in the first transfer block TB1 remain high, and the turn-off state is reached. Is maintained. On the other hand, the voltages at the cathode terminals of the odd-numbered transfer thyristors S129,..., S253, S255 in the second transfer block TB2 remain high, and the turn-off state is maintained. Further, at this time, since the lighting signals φI1 to φI120 are at the high level, the voltages at the cathode terminals of the light emitting thyristors L1 to L256 remain high, and the light emitting thyristors L1 to L256 are not lighted.

  Then, in a state where the transfer thyristor S1 of the first transfer block TB1 and the transfer thyristor S256 of the second transfer block TB2 of the light emitting chips C1 to C60 are turned on, the transfer signal generating unit 120 sets the second transfer signal φ2 to the high level. After the second period tb has elapsed since the change, the lighting signal generator 110 changes the lighting signals φI1 to φI120 from the high level to the low level. Accordingly, in the first light emitting block LB1 of each of the light emitting chips C1 to C60, the light emitting thyristor L1 having the highest gate terminal voltage among the odd numbered light emitting thyristors L1, L3,. On the other hand, in the second light emitting block LB2, the light emitting thyristor L256 having the highest potential at the gate terminal among the even numbered light emitting thyristors L2, L4,. For example, when the light emitting thyristor L1 is not lit, the lighting signal φI1 may be maintained at a high level while the transfer thyristor S1 is turned on. Similarly, for example, when the light emitting thyristor L256 is not turned on, the lighting signal φI2 may be maintained at a high level while the transfer thyristor S256 is turned on.

  Next, when the transfer thyristor S1 is turned on in the first transfer block TB1 of each of the light emitting chips C1 to C60, and the transfer thyristor S256 is turned on in the second transfer block TB2, the transfer signal generation unit 120 performs the second transfer. The transfer signal φ2 is changed from the high level to the low level. Then, in the first transfer block TB1 of each of the light emitting chips C1 to C60, the gate terminal voltage is the highest among the even-numbered transfer thyristors S2, S4,..., S128 to which the low-level second transfer signal φ2 is supplied. The transfer thyristor S2 having a gate voltage equal to or higher than the threshold is turned on. On the other hand, in the second transfer block TB2, among the odd-numbered transfer thyristors S129,..., S253, S255 to which the low-level second transfer signal φ2 is supplied, the voltage at the gate terminal is the highest, The transfer thyristor S255 is turned on. At this time, in the first transfer block TB1 of each of the light emitting chips C1 to C60, two adjacent transfer thyristors S1 and S2 are turned on, and in the second transfer block TB2, two adjacent transfer thyristors S255 and S256 are turned on. Both are turned on.

  At the same time that the transfer signal generator 120 changes the second transfer signal φ2 from the high level to the low level, the lighting signal generator 110 changes the lighting signals φI1 to φI120 from the low level to the high level. Accordingly, both the light emitting thyristor L1 of the first light emitting block LB1 and the light emitting thyristor L256 of the second light emitting block LB2 that have been turned on until then are turned off. Then, the transfer signal generator 120 changes the first transfer signal φ1 from the low level to the high level after the first period ta has elapsed since the second transfer signal φ2 was set to the low level. Then, the transfer thyristor S1 is turned off in the first transfer block TB1 of each light emitting chip C1 to C60, and the transfer thyristor S256 is turned off in the second transfer block TB2. In the first transfer block TB1 of each of the light emitting chips C1 to C60, the potential of the gate terminal of the transfer thyristor S1 is gradually decreased by the resistor R1 with the turn-off of the transfer thyristor S1, and is adjacent in the forward direction via the diode D1. The potential of the gate terminal of the transfer thyristor S2 rises. On the other hand, in the second transfer block TB2, as the transfer thyristor S256 is turned off, the potential of the gate terminal of the transfer thyristor S256 is gradually decreased by the resistor R256, and the gate of the transfer thyristor S255 adjacent in the forward direction via the diode D254. The terminal potential rises. The transfer signal generator 120 changes the start transfer signal φS from the high level to the low level simultaneously with changing the first transfer signal φ1 from the low level to the high level.

  Then, in the state where the transfer thyristor S2 of the first transfer block TB1 and the transfer thyristor S255 of the second transfer block TB2 of each of the light emitting chips C1 to C60 are turned on, the transfer signal generation unit 120 sets the first transfer signal φ1 to the high level. After the second period tb has elapsed since the change to, the lighting signal generator 110 changes the lighting signals φI1 to φI120 from the high level to the low level. Accordingly, in the first light-emitting block LB1 of each of the light-emitting chips C1 to C60, the light-emitting thyristor L255 having the highest gate terminal voltage among the odd-numbered light-emitting thyristors L1, L3,. On the other hand, in the second light-emitting block LB2, the light-emitting thyristor L2 having the highest voltage at the gate terminal among the even-numbered light-emitting thyristors L2, L4,.

  Next, when the transfer thyristor S2 is turned on in the first transfer block TB1 of each of the light emitting chips C1 to C60, and the transfer thyristor S255 is turned on in the second transfer block TB2, the transfer signal generator 120 is the first. The transfer signal φ1 is changed from high level to low level. Then, in the first transfer block TB1 of each of the light emitting chips C1 to C60, among the odd-numbered transfer thyristors S1, S3,... S127 supplied with the low-level first transfer signal φ1, the gate terminal voltage is the highest. The transfer thyristor S3 having a gate voltage higher than the threshold is turned on. On the other hand, in the second transfer block TB2, among the even-numbered transfer thyristors S130,..., S254, S256 to which the low-level first transfer signal φ1 is supplied, the transfer has the highest gate voltage and the gate voltage equal to or higher than the threshold value. Thyristor S254 is turned on. At this time, in the first transfer block TB1 of each of the light emitting chips C1 to C60, two adjacent transfer thyristors S2 and S3 are turned on, and in the second transfer block TB2, two adjacent transfer thyristors S254 and S255 are turned on. Both are turned on.

  At the same time as the transfer signal generator 120 changes the first transfer signal φ1 from the high level to the low level, the lighting signal generator 110 changes the lighting signals φI (φI1 to φI120) from the low level to the high level. Accordingly, both the light emitting thyristor L2 of the first light emitting block LB1 and the light emitting thyristor L255 of the second light emitting block LB2 that have been turned on until then are turned off. Thereafter, when the transfer signal generator 120 changes the second transfer signal φ2 from the low level to the high level, the transfer thyristor S2 is turned off in the first transfer block TB1 of each light emitting chip C1 to C60, and the transfer is performed in the second transfer block TB2. Thyristor S255 is turned off. In the first transfer block TB1 of each of the light emitting chips C1 to C60, the potential of the gate terminal of the transfer thyristor S2 is gradually lowered by the resistor R2 with the turn-off of the transfer thyristor S2, and is adjacent in the forward direction via the diode D2. The potential at the gate terminal of the transfer thyristor S3 rises. Along with this, the potentials of the gate terminals of the other transfer thyristors S4 to S128 connected via the diodes D3 to D127 also rise. On the other hand, in the second transfer block TB2, as the transfer thyristor S255 is turned off, the potential of the gate terminal of the transfer thyristor S255 is gradually decreased by the resistor R255, and the gate of the transfer thyristor S254 adjacent in the forward direction via the diode 253 is used. The terminal potential rises. Along with this, the potentials of the gate terminals of the other transfer thyristors S253 to S129 connected via the diodes D252 to D128 also rise. Note that the period from when the first transfer signal φ1 becomes low level until the second transfer signal φ2 becomes low level, and after the second transfer signal φ2 becomes low level, the first transfer signal φ1 becomes low level. The period until becomes is called a thyristor transfer cycle P.

  As described above, in the full resolution mode, the light emitting unit 63 provides an overlapping period (first period ta shown in FIG. 8) in which both the first transfer signal φ1 and the second transfer signal φ2 are set to a low level. By alternately switching between the high level and the low level, the transfer thyristors S1 to S128 are sequentially turned on in the numerical order in the first transfer block TB1 of each light emitting chip C1 to C60, and the transfer thyristor S129 in the second transfer block TB2. ˜S256 are sequentially turned on in the reverse order of the numbers.

  In the full resolution mode, the changeover switch 130 is set to ON. Therefore, the odd-numbered lighting signals φI1, φI3,..., ΦI119 and the even-numbered lighting signals φI2, φI4 after passing the second period tb shown in FIG. 8 in synchronization with the turn-on transfer operation of the transfer thyristors S1 to S256. ,..., ΦI120 is switched from the high level to the low level, whereby the odd-numbered light emitting thyristors L1, L3,..., L253, L255 are turned on one by one in the first light emitting block LB1, and the second light emitting block LB2 is turned on. , The even-numbered light emitting thyristors L2, L4,..., L254, L256 are turned on one by one.

Here, FIG. 9 is a diagram for explaining the lighting order of the light-emitting thyristors L1 to L256 constituting the light-emitting chips C1 to C60 in the full resolution mode.
As described with reference to FIG. 8, first, the light emitting thyristor L1 belonging to the first light emitting block LB1 and positioned at the left end of the light emitting element array 71 can be turned on by the transfer thyristor S1 belonging to the first transfer block TB1. At the same time, the light-emitting thyristor L256 belonging to the second light-emitting block LB2 and positioned at the right end of the light-emitting element array 71 is in a state that can be turned on by the transfer thyristor S256 belonging to the second transfer block TB2. Subsequently, secondly, the light-emitting thyristor L2 belonging to the second light-emitting block LB2 and located on the right side of the light-emitting thyristor L1 in the light-emitting element array 71 is in a state that can be turned on by the transfer thyristor S2 belonging to the first transfer block TB1. At the same time, the light-emitting thyristor L255 belonging to the first light-emitting block LB1 and located on the left side of the light-emitting thyristor L256 in the light-emitting element array 71 can be turned on by the transfer thyristor S255 belonging to the second transfer block TB2. Then, as the lighting order decreases, the position of the light emitting thyristor that can be turned on moves from the left and right ends of the light emitting element array 71 toward the center. And 128th, the light-emitting thyristor L128 belonging to the second light-emitting block LB2 and located on the right side of the light-emitting thyristor L127 in the light-emitting element array 71 can be turned on by the transfer thyristor S128 belonging to the first transfer block TB1. The light-emitting thyristor L129 that belongs to the first light-emitting block LB1 and is located on the left side of the light-emitting thyristor L130 in the light-emitting element array 71 can be turned on by the transfer thyristor S129 that belongs to the second transfer block TB2.

  As described above, in the present embodiment, the light-emitting thyristors that belong to the first light-emitting block LB1 and the second light-emitting block LB2 and constitute one end side light-emitting element group by the transfer thyristors S1 to S128 constituting the first transfer block TB1. L1 to L128 are set in a state where light can be emitted sequentially in a first direction from left to right in the drawing. In synchronization with this, the light-emitting thyristors L129 that belong to the first light-emitting block LB1 and the second light-emitting block LB2 and constitute the other light-emitting element group are transferred by the transfer thyristors S129 to S256 that form the second transfer block TB2. ˜L256 are set in a state where light can be emitted sequentially in the second direction from right to left in the drawing.

  Here, FIG. 10 is a diagram for explaining the arrangement of the light-emitting thyristors that can be turned on in the full resolution mode. In FIG. 10, only the light emitting chips C1 to C3 are extracted and shown. In the full resolution mode, as described with reference to FIGS. 8 and 9, all the light emitting thyristors L1 to L256 constituting each of the light emitting chips C1 to C60 are set to a lightable state.

  Subsequently, the image processing unit 35 (see FIG. 1) of the image forming apparatus 1 outputs video data Vdata having a main scanning direction resolution of 600 dpi while referring to the timing charts shown in FIGS. 5 and 6 and FIG. The operation of the light emitting unit 63 when only having the function to perform will be described. Therefore, it is assumed that the changeover switch 130 provided in the LPH 14 is set to OFF. In the following description, the operation of the light emitting unit 63 in a state where the changeover switch 130 is set to OFF is referred to as a half resolution mode (corresponding to the second mode). The timing chart shown in FIG. 11 shows a case where all the light emitting thyristors L1 to L256 are turned on in each of the light emitting chips C1 to C60 constituting the light emitting unit 63, as in the above-described full resolution mode.

  Also in the half resolution mode, the transfer signal generation unit 120 supplies the light-emitting chips C1 to C60 with the start transfer signal φS, the first transfer signal φ1, and the second transfer signal φ2 similar to those in the full resolution mode described above. . Even in the half resolution mode, while providing an overlapping period (first period ta shown in FIG. 11) in which both the first transfer signal φ1 and the second transfer signal φ2 are set to the low level, the high transfer level and the low transfer By switching the levels, the transfer thyristors S1 to S128 are sequentially turned on in the numerical order in the first transfer block TB1 of each light emitting chip C1 to C60, and the transfer thyristors S129 to S256 are the numbers in the second transfer block TB2. Turn on sequentially in reverse order.

  Here, in the half resolution mode, the changeover switch 130 is set to OFF. Therefore, the odd-numbered light emitting chips C1, C3,..., C59 constituting the first chip row 63a (see FIG. 3) are not supplied with the even-numbered lighting signals φI2, φI6,. Apparently, it is in a high level state (± 0.0 V). Therefore, in the odd-numbered light emitting chips C1, C3,..., C59 in the half resolution mode, the even-numbered lighting signals φI2, φI6,. Even-numbered light emitting thyristors L2, L4,..., L256 constituting the two light emitting blocks LB2 are not lit. On the other hand, in the odd-numbered light emitting chips C1, C3,..., C59, the odd-numbered lighting signals φI1, φI5,. The odd-numbered light emitting thyristors L1, L3,..., L255 constituting the light emitting block LB1 are turned on one by one.

  Further, even-numbered light emitting chips C2, C4,..., C60 constituting the second chip row 63b (see FIG. 3) are not supplied with odd-numbered lighting signals φI3, φI7,. Apparently, it is in a high level state (± 0.0 V). Therefore, in the half resolution mode, in the even-numbered light emitting chips C2, C4,..., C60, the odd-numbered lighting signals φI3, φI7,. The odd-numbered light emitting thyristors L1, L3,..., L255 constituting one light emitting block LB1 are not lit. On the other hand, in the even-numbered light emitting chips C2, C4,..., C60, the even-numbered lighting signals φI4, φI8,. The even-numbered light emitting thyristors L2, L4,..., L256 constituting the light emitting block LB2 are turned on one by one.

  Here, FIG. 12 is a diagram for explaining the lighting order of the light-emitting thyristors L1 to L256 constituting the light-emitting chips C1 to C60 in the half resolution mode. 12A shows the lighting order of the light emitting thyristors L1 to L256 constituting the first chip row 63a, that is, odd-numbered light emitting chips C1, C3,..., C59 in the half resolution mode. (B) shows the lighting order of the light emitting thyristors L1 to L256 constituting the second chip row 63b, that is, the even-numbered light emitting chips C2, C4,..., C60 in the half resolution mode.

  As described with reference to FIG. 11, as in the above-described full resolution mode, first, the light emitting thyristor L1 belonging to the first light emitting block LB1 and positioned at the left end of the light emitting element array 71 is first transferred to the first transfer block TB1. The light emitting thyristor L256 belonging to the second light emitting block LB2 and located at the right end of the light emitting element array 71 can be turned on at the same time by the transfer thyristor S256 belonging to the second transfer block TB2. become. However, in the half resolution mode, the even-numbered lighting signals φI2, φI6,..., ΦI120 are not supplied to the odd-numbered light emitting chips C1, C3,. Therefore, in the odd-numbered light-emitting chips C1, C3,..., C59, only the odd-numbered light-emitting thyristor L1 can be lit, and the even-numbered light-emitting thyristor L256 is substantially unlit as shown in FIG. It becomes possible. In the half resolution mode, the odd-numbered lighting signals φI3, φI7,..., ΦI119 are not supplied to the even-numbered light emitting chips C2, C4,. Therefore, in the even-numbered light-emitting chips C2, C4,..., C60, as shown in FIG. 12 (b), only the even-numbered light-emitting thyristor L256 can be turned on, and the odd-numbered light-emitting thyristor L1 is substantially unlit. It becomes possible.

  Subsequently, similarly to the above-described full resolution mode, secondly, the light emitting thyristor L2 belonging to the second light emitting block LB2 and located on the right side of the light emitting thyristor L1 in the light emitting element array 71 is transferred belonging to the first transfer block TB1. The light emitting thyristor L255, which belongs to the first light emitting block LB1 and is located on the left side of the light emitting thyristor L256 in the light emitting element array 71, is simultaneously turned on by the transfer thyristor S255 belonging to the second transfer block TB2. It becomes possible. However, in the odd-numbered light-emitting chips C1, C3,..., C59, only the odd-numbered light-emitting thyristor L255 can be lit as shown in FIG. It becomes virtually impossible to light. Further, as shown in FIG. 12B, in the even-numbered light emitting chips C2, C4,..., C60, only the even-numbered light-emitting thyristor L2 can be lit for the reasons described above, and the odd-numbered light-emitting thyristor L255 is It becomes virtually impossible to light.

  Thereafter, as the lighting order decreases, in the odd-numbered light-emitting chips C1, C3,..., C59, as shown in FIG. The light emitting element array 71 is moved toward the center of the light emitting element array 71 while sequentially moving from left to right. In synchronism with this, in the even-numbered light emitting chips C2, C4,..., C60, as shown in FIG. Move toward the center while moving sequentially to the right and left of the.

  And 128th, the light-emitting thyristor L128 belonging to the second light-emitting block LB2 and located on the right side of the light-emitting thyristor L127 in the light-emitting element array 71 can be turned on by the transfer thyristor S128 belonging to the first transfer block TB1. The light-emitting thyristor L129 that belongs to the first light-emitting block LB1 and is located on the left side of the light-emitting thyristor L130 in the light-emitting element array 71 can be turned on by the transfer thyristor S129 that belongs to the second transfer block TB2. However, in the odd-numbered light-emitting chips C1, C3,..., C59, only the odd-numbered light-emitting thyristor L129 can be lit as shown in FIG. It becomes virtually impossible to light. Further, in the even-numbered light emitting chips C2, C4,..., C60, for the reason described above, only the even-numbered light-emitting thyristor L128 can be lit as shown in FIG. It becomes virtually impossible to light.

  Here, FIG. 13 is a diagram for explaining the arrangement of the light-emitting thyristors that can be turned on in the half resolution mode. In FIG. 13, only the light emitting chips C1 to C3 are extracted and shown. In the half resolution mode, as described with reference to FIGS. 11 and 12, the odd-numbered light-emitting chips C1, C3,..., C59 constituting the first chip row 63a are odd-numbered constituting the first light-emitting block LB1. The light emitting thyristors L1, L3,..., L255 can be turned on, and the even-numbered light emitting chips C2, C4,..., C60 constituting the second chip row 63b constitute the second light emitting block LB2. Only even-numbered light-emitting thyristors L2, L4,. In this embodiment, the light emitting chips C1, C3,..., C59 constituting the first chip row 63a and the light emitting chips C2,..., C58, C60 constituting the second chip row 63b are sub-scanned. The direction is reversed. For this reason, in the half resolution mode, in each of the light emitting chips C1 to C60, every other light emitting thyristor is turned on, and at the end boundary of the light emitting element array 71 in each of the light emitting chips C1 to C60, Every other light-emitting thyristor that can be turned on. Accordingly, when viewed as the entire light emitting unit 63, the light emitting thyristors that can be turned on are arranged at intervals of 42.3 μm in the main scanning direction, and from the light emitting unit 63 at equal intervals in the main scanning direction. An optical image of 600 dpi is output.

  Further, in the half resolution mode, in each of the light emitting chips C1 to C60, the right side light emitting thyristor and the left side light emitting thyristor can be alternately lit from the left and right ends of the light emitting element array 71 toward the center. For this reason, when each of the light emitting chips C1 to C60 is used for optical writing in one line in the main scanning direction to form an electrostatic latent image, the electrostatic latent image obtained by each of the light emitting chips C1 to C60 has a full resolution. It is not V-shaped as in the mode (see FIG. 9), but is more discrete. Therefore, in the half resolution mode in which the dot interval in the main scanning direction is wider than that in the full resolution mode, V-shaped stripes generated for each length in the main scanning direction of the light emitting element array 71 of each of the light emitting chips C1 to C60 are less noticeable.

<Embodiment 2>
Although the present embodiment is substantially the same as the first embodiment, the arrangement of the plurality of light emitting chips C1 to C60 constituting the light emitting unit 63 is different. Accordingly, the lighting control of the light emitting thyristor in the half resolution mode is performed. Is different from the first embodiment. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 14 is an enlarged view of a connection portion of the light emitting chips C1, C2, and C3 in the light emitting unit 63. Each of the light emitting chips C1 to C60 has the same configuration as that described in the first embodiment. In the present embodiment, the light emitting chips C1 to C60 are not arranged in a zigzag pattern, but are inclined (tilted) by a certain angle in the sub-scanning direction. Therefore, in the present embodiment, odd-numbered light emitting chips C1, C3,..., C59 and even-numbered light emitting chips C2, C4,. It is arranged to face. As shown in FIG. 14, at the end boundary of the light emitting element array 71 arranged in each of the light emitting chips C1, C2, C3, the light emitting element array 71 is connected to the light emitting chips C1, C2 and the light emitting chip C2. , C3 are arranged so as to be continuous in the main scanning direction. The arrangement interval of the 256 light emitting thyristors L1 to L256 constituting the light emitting element array 71 of each light emitting chip C1 to C60 is set slightly larger than 21.15 μm depending on the mounting angle of each light emitting chip C1 to C60. Is done.

  Here, FIG. 15 is a diagram for explaining the operation switching of the lighting signal generator 110 by the changeover switch 130 shown in FIG. When the changeover switch 130 is set to ON, the lighting signal generation unit 110, as in the first embodiment, has two sets of odd numbered and even numbered lighting signals (for example, light emission) for each of the light emitting chips C1 to C60. In the chip C3, the lighting signals φI5 and φI6) are supplied. On the other hand, when the changeover switch 130 is set to OFF, the lighting signal generator 110 outputs odd-numbered lighting signals (in the case of the light-emitting chip C3) to all the light-emitting chips C1 to C60 regardless of the odd-numbered and even-numbered. Supplies only the lighting signal φI5) and does not supply the even-numbered lighting signal (lighting signal φI6 in the case of the light emitting chip C3).

  In the full resolution mode, as in the first embodiment, by supplying odd-numbered and even-numbered lighting signals to the light-emitting chips C1 to C60, the light-emitting thyristors L1 constituting the light-emitting chips C1 to C60. ˜L256 is turned on. On the other hand, in the half resolution mode, only odd-numbered lighting signals are supplied to the light-emitting chips C1 to C60, respectively, so that only the odd-numbered light-emitting thyristors L1, L3,. The even-numbered light emitting thyristors L2, L4,..., L256 are substantially unlit. For this reason, in the half resolution mode, as in the first embodiment, in each of the light emitting chips C1 to C60, every other light emitting thyristor that can be turned on is provided, and in each of the light emitting chips C1 to C60. Even at the end boundary of the light emitting element array 71, every other light emitting thyristor that can be turned on is provided. Therefore, when viewed as the entire light emitting unit 63, the light emitting thyristors that can be turned on are arranged at intervals of 42.3 μm in the main scanning direction, and from the light emitting unit 63 at equal intervals in the main scanning direction. , 600 dpi optical image is output.

  Also in the present embodiment, for the same reason as in the first embodiment, the V-shaped stripes generated for each length in the main scanning direction of the light emitting element array 71 of each of the light emitting chips C1 to C60 are less noticeable.

  In the half resolution mode of the first embodiment, only the odd-numbered light emitting thyristors L1, L3,..., L255 in the odd-numbered light emitting chips C1, C3,. Although only the even-numbered light emitting thyristors L2, L4, and L256 in C2, C4,..., C60 are in a state that can be turned on, the present invention is not limited to this, and the reverse relationship may be employed. On the other hand, in the half resolution mode of the second embodiment, only the odd-numbered light emitting thyristors L1, L3,..., L255 in all the light emitting chips C1 to C60 can be turned on, but the present invention is not limited to this. The reverse relationship is also possible.

  Further, when the half resolution mode of the first and second embodiments is executed, the odd-numbered light-emitting thyristors L1, L3,..., L255 are turned on, for example, by disconnecting the wiring to the φI1 terminal in the odd-numbered light-emitting chip C1. When the control becomes difficult, the setting of the changeover switch 130 may be changed so that only the even-numbered light emitting thyristors L2, L4,..., L256 can be turned on in the light emitting chip C1. .

  Further, in the first and second embodiments, each of the light emitting chips C1 to C60 is configured to transfer the lightable state from the left and right ends of the light emitting element array 71 toward the center, but is not limited thereto. The lighting-enabled state may be transferred from the center of the light emitting element array 71 toward both left and right ends.

  Furthermore, in the first and second embodiments, the anode terminals of the transfer thyristors S1 to S128 are set to a common potential, and the potential of each cathode terminal is changed by the first transfer signal φ1 or the second transfer signal φ2. However, the present invention is not limited to this, and the cathode terminals of the transfer thyristors S1 to S128 may be set to a common potential, and the potential of each anode terminal may be changed by the first transfer signal φ1 or the second transfer signal φ2. On the other hand, in the first and second embodiments, the anode terminals of the light emitting thyristors L1 to L128 are set to a common potential, and the potentials of the cathode terminals are set to the first lighting signals φI1, φI3,..., ΦI119 and the second lighting signals φI2, φI4, ..., ΦI120, but the present invention is not limited to this. The cathode terminals of the light emitting thyristors L1 to L128 are set to a common potential, and the potentials of the anode terminals are set to the first lighting signals φI1, φI3,. The second lighting signals φI2, φI4,..., ΦI120 may be changed.

  In the first and second embodiments, the first transfer block TB1 and the second transfer block TB2 are each provided with an even number and the same number (128) of transfer thyristors, and the first light emission block LB1 and the second light emission block LB2 are respectively provided. Although an even number and the same number (128) of light emitting thyristors are provided, the present invention is not limited to this. For example, the number of transfer thyristors or light emitting thyristors constituting each transfer block or each light emitting block may be an odd number, or an odd number and an even number may be combined. Accordingly, the first transfer block TB1 and the second transfer block TB2 may have different numbers of transfer thyristors, and the first light emission block LB1 and the second light emission block LB2 may have different numbers of light emission thyristors. You may have it.

1 is a diagram illustrating an example of an overall configuration of an image forming apparatus to which the exemplary embodiment is applied. It is sectional drawing which showed the structure of LED print head (LPH). (A) is a top view of the circuit board and light emitting part in LPH, (b) is a top view of the rod lens array and holder in LPH. FIG. 3 is an enlarged view of a main part for illustrating the configuration of a light emitting unit in the first embodiment. It is the figure which showed the structure of the signal generation circuit mounted in a circuit board, and the wiring structure of a circuit board. It is a figure for demonstrating the circuit structure of a light emitting chip. FIG. 6 is a diagram for describing an outline of operation switching of a lighting signal generation unit by a changeover switch in the first embodiment. It is a timing chart for demonstrating operation | movement of the light emission part in full resolution mode. It is a figure for demonstrating the lighting order of each light emitting thyristor which comprises each light emitting chip in full-resolution mode. It is a figure for demonstrating arrangement | positioning of the light emitting thyristor which can be lighted in a full resolution mode. It is a timing chart for demonstrating operation | movement of the light emission part in a half resolution mode. It is a figure for demonstrating the lighting order of each light emitting thyristor which comprises each light emitting chip in a half resolution mode. It is a figure for demonstrating arrangement | positioning of the light emitting thyristor which can be lighted in a half resolution mode. FIG. 10 is an enlarged view of a main part for explaining the configuration of a light emitting unit in a second embodiment. FIG. 10 is a diagram for describing an outline of operation switching of a lighting signal generation unit by a changeover switch in the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 35 ... Image processing part, 63 ... Light emission part, 63a ... 1st chip row | line | column, 63b ... 2nd chip row | line | column, 70 ... Chip board | substrate, 71 ... Light emitting element array, 100 ... Signal generation circuit, 110 ... Lighting signal generation unit, 120 ... transfer signal generation unit, 130 ... changeover switch, LB1 ... first light emission block, LB2 ... second light emission block, TB1 ... first transfer block, TB2 ... second transfer block, φS ... start transfer signal , Φ1 ... first transfer signal, φ2 ... second transfer signal, φI1 to φI120 ... lighting signal, C1 to C60 ... light emitting chip, S1 to S256 ... transfer thyristor, L1 to L256 ... light emitting thyristor, D1 to D254 ... diode, R1 ~ R256 ... resistance

Claims (13)

A light emitting element array having a plurality of light emitting elements arranged in a line and controlled to be turned on / off by a lighting signal;
A switch element array having a plurality of switch elements that are provided corresponding to each of the plurality of light emitting elements and that turn on the corresponding light emitting elements by being set to an on state,
The light-emitting element array is
A first light emitting element group configured by light emitting elements arranged in an odd number in the light emitting element row, to which a common first lighting signal is supplied as the lighting signal;
A second light emitting element group that is configured by even-numbered light emitting elements in the light emitting element row and to which a common second lighting signal is supplied as the lighting signal;
The switch element row is
Each light emitting element of the one end side light emitting element group comprised by the light emitting element arranged in the one end side of the said light emitting element row | line | column among the light emitting elements which belong to the said 1st light emitting element group, and the light emitting element which belongs to the said 2nd light emitting element group. , A first switch element group that is set in a state capable of sequentially emitting light along the first direction;
Of the light emitting elements belonging to the first light emitting element group and the light emitting elements belonging to the second light emitting element group, each of the other end side light emitting element groups configured by light emitting elements arranged on the other end side of the light emitting element row. A light emitting device comprising: a second switch element group that sets a light emitting element in a state capable of sequentially emitting light along a second direction opposite to the first direction. A lighting signal generator for supplying the first lighting signal to the first light emitting element group and supplying the second lighting signal to the second light emitting element group;
A first mode in which the lighting signal generation unit supplies both the first lighting signal and the second lighting signal, and the lighting signal generation unit has only one of the first lighting signal and the second lighting signal. The light emitting device according to claim 1, further comprising a switching unit that switches between the second mode for supplying the light.   3. The light emitting device according to claim 1, wherein the number of the light emitting elements constituting the first light emitting element group and the number of the light emitting elements constituting the second light emitting element group are an even number and the same number.   The light emitting device according to any one of claims 1 to 3, wherein the plurality of light emitting elements and the plurality of switch elements are formed of thyristors. A plurality of first transfer thyristors are arranged in a line, and the gates of adjacent first transfer thyristors are connected so that a current flows in one direction with a diode, respectively, and the anode or cathode of each first transfer thyristor is connected to each other, A first transfer block formed by alternately connecting the first transfer signal terminal to which the first transfer signal is input and the second transfer signal terminal to which the second transfer signal is input in the arrangement direction;
A plurality of second transfer thyristors are arranged in a line adjacent to the first transfer block, and the gates of the adjacent second transfer thyristors are connected by diodes so that current flows in a direction opposite to the one direction. A second transfer block in which anodes or cathodes of the respective second transfer thyristors are alternately connected to the first transfer signal terminal and the second transfer signal terminal in the arrangement direction;
A plurality of first light-emitting thyristors are arranged in a line, and each first light-emitting thyristor gate, odd-numbered first transfer thyristor gate in the first transfer block, and odd-numbered second second in the second transfer block. A first light-emitting block which is connected to the gates of the transfer thyristors, and a common first lighting signal is supplied to the anode or cathode of each first light-emitting thyristor;
A plurality of second light-emitting thyristors are respectively arranged between the adjacent first light-emitting thyristors, each of the second light-emitting thyristors, the gate of the even-numbered first transfer thyristor of the first transfer block, and the second. A light-emitting device including a second light-emitting block that is connected to the gates of even-numbered second transfer thyristors of the transfer block, and to which a common second lighting signal is supplied to the anode or cathode of each second light-emitting thyristor. A plurality of first transfer thyristors are arranged in a line, and the gates of adjacent first transfer thyristors are connected so that a current flows in one direction with a diode, respectively, and the anode or cathode of each first transfer thyristor is connected to each other, A first transfer block formed by alternately connecting the first transfer signal terminal to which the first transfer signal is input and the second transfer signal terminal to which the second transfer signal is input in the arrangement direction;
A plurality of second transfer thyristors are arranged in a line adjacent to the first transfer block, and the gates of the adjacent second transfer thyristors are connected by diodes so that current flows in a direction opposite to the one direction. A second transfer block formed by alternately connecting an anode or a cathode of each second transfer thyristor to the first transfer signal terminal and the second transfer signal terminal;
A plurality of first light-emitting thyristors arranged in a line, and a first light-emitting block in which a common first lighting signal is supplied to the anode or cathode of each first light-emitting thyristor;
A plurality of second light emitting thyristors are alternately arranged with the plurality of first light emitting thyristors, and a second light emitting block in which a common second lighting signal is supplied to the anode or cathode of each first light emitting thyristor. Prepared,
Among the plurality of first light-emitting thyristors constituting the first light-emitting block, the gates of some of the first light-emitting thyristors are respectively connected to the gates of the first transfer thyristors constituting the first transfer block, The remaining gates of the first light emitting thyristors are respectively connected to the gates of the second transfer thyristors constituting the second transfer block,
Among the plurality of second light emitting thyristors constituting the second light emitting block, the gates of some second light emitting thyristors constitute the first transfer block and the first light emitting thyristor is not connected to the second light emitting thyristor. Connect to the gates of one transfer thyristor and connect the gates of the remaining second light-emitting thyristors to the second transfer thyristor that constitutes the second transfer block and is not connected to the first light-emitting thyristor. A light emitting device characterized by the above. In the first transfer block, the gate of each of the first transfer thyristors is connected to a common wiring through a resistor,
7. The light emitting device according to claim 5, wherein in the second transfer block, a gate of each of the second transfer thyristors is connected to the common wiring through a resistor. A lighting signal generator for supplying the first lighting signal to the first light-emitting block and supplying the second lighting signal to the second light-emitting block;
A first mode in which the lighting signal generation unit supplies both the first lighting signal and the second lighting signal, and the lighting signal generation unit has only one of the first lighting signal and the second lighting signal. The light-emitting device according to claim 5, further comprising a switching unit that switches between a second mode for supplying the light.   9. The number of light-emitting thyristors constituting the first light-emitting block and the number of light-emitting thyristors constituting the second light-emitting block are an even number and the same number. Light emitting device. An exposure apparatus for exposing a charged image carrier, comprising a light emitting section having a plurality of light emitting chips arranged in the main scanning direction and a plurality of light emitting chips arranged in the main scanning direction. ,
The light emitting chip is provided corresponding to each of the plurality of light emitting elements, and includes a switch element array having a plurality of switch elements that can be turned on by setting the corresponding light emitting elements to an on state.
The light-emitting element array is
A first light emitting element group configured by odd-numbered light emitting elements in the light emitting element row and supplied with a common first lighting signal as a lighting signal;
A second light emitting element group configured by even-numbered light emitting elements in the light emitting element row, to which a common second lighting signal is supplied as the lighting signal;
The switch element row is
Each light emitting element of the one end side light emitting element group comprised by the light emitting element arranged in the one end side of the said light emitting element row | line | column among the light emitting elements which belong to the said 1st light emitting element group, and the light emitting element which belongs to the said 2nd light emitting element group. , A first switch element group that is set in a state capable of sequentially emitting light along the first direction;
Of the light emitting elements belonging to the first light emitting element group and the light emitting elements belonging to the second light emitting element group, each of the other end side light emitting element groups configured by light emitting elements arranged on the other end side of the light emitting element row. An exposure apparatus comprising: a second switch element group configured to sequentially set the light emitting elements in a state capable of emitting light along a second direction opposite to the first direction. In the light emitting unit, light emitting chips arranged oddly in the main scanning direction and light emitting chips arranged evenly in the main scanning direction are arranged in a staggered manner by being shifted in the sub-scanning direction, and arranged in the odd numbered manner. The light emitting chips and the even-numbered light emitting chips are attached in the reverse direction in the sub-scanning direction,
A lighting signal generator for supplying the first lighting signal to the first light emitting element group and supplying the second lighting signal to the second light emitting element group;
A first mode in which the lighting signal generation unit supplies both the first lighting signal and the second lighting signal, and the lighting signal generation unit has only one of the first lighting signal and the second lighting signal. A switching unit for switching between the second mode for supplying
In the second mode, the switching unit supplies the first lighting signal or the second lighting signal to the odd-numbered light emitting chips and supplies the even-numbered light emitting chips to the odd-numbered light emitting chips. 11. The exposure apparatus according to claim 10, wherein the second lighting signal or the first lighting signal that is not supplied to the odd-numbered light emitting chips is supplied.   12. The number of light emitting elements constituting the first light emitting element group and the number of light emitting elements constituting the second light emitting element group in the light emitting chip are an even number and the same number. Exposure device.   13. The exposure apparatus according to claim 10, wherein the plurality of light emitting elements and the plurality of switch elements constituting the light emitting chip are configured by thyristors.

Images