JP5092359B2 - Print head - Google Patents

Description

  The present invention relates to a print head used in an image forming apparatus, and more particularly to a print head that performs exposure by sequentially lighting a plurality of lighting elements.

In an image forming apparatus such as a copying machine or a printer using an electrophotographic system, first, for example, the surface of a photosensitive member (photosensitive drum) formed in a drum shape is uniformly charged by a charging device. The charged photosensitive drum is exposed by an exposure device controlled based on the image data, and an electrostatic latent image is formed on the surface thereof. Subsequently, the electrostatic latent image formed on the photosensitive drum is converted into a visible image (toner image) by the developing device. Thereafter, the toner image is transported to the transfer unit as the photosensitive drum rotates, and is electrostatically transferred onto the recording paper. The toner image carried on the recording paper is subjected to a fixing process to become a permanent image.
As an exposure apparatus used in such an image forming apparatus, conventionally, an optical scanning apparatus (ROS: Raster Output Scanner) that scans and exposes laser light in the main scanning direction by combining a laser diode and a polygon mirror has been used. It was. However, in recent years, exposure using an LED print head (LPH: LED Print Head) configured by arranging a large number of LEDs (Light Emitting Diodes) in the main scanning direction due to demands for downsizing of the apparatus. Many devices are also used.

  The LPH includes an LED array in which a plurality of LED chips in which a large number of LEDs are arranged in a line are arranged in the main scanning direction. The LPH usually also includes a rod lens array in which a large number of rod lenses are arranged in order to form an image of light output from each LED on the surface of the photoreceptor. In the image forming apparatus, each LED of the LPH is driven based on input image data to output light toward the photoconductor, and the light is imaged on the surface of the photoconductor by the rod lens array. Thereby, an electrostatic latent image for one line in the main scanning direction is formed on the photosensitive member. Then, by rotating the photoconductor, the photoconductor drum and the LPH move relative to each other, thereby forming an electrostatic latent image in the sub-scanning direction of the photoconductor.

  Recently, a self-scanning light emitting device (SLED) has been proposed as this type of LPH (see Patent Document 1). In this SLED, a thyristor is used as a switch element for lighting each LED in the LED chip. In the SLED, the LED itself has a thyristor structure. In such an SLED, transfer signals CK1 and CK2 (each set to ON or OFF) are output in synchronization with the input line synchronization signal (Lsync). Then, by sequentially turning on each thyristor by these transfer signals CK1 and CK2, the LEDs (thyristors) constituting each LED chip are controlled to be sequentially lightable in the main scanning direction. On the other hand, a predetermined constant voltage is applied to one common wiring (power supply line) connected to the anode terminal of each LED, and the other common wiring (signal line) connected to the cathode terminal of each LED is lit. By applying a signal ΦI (set to ON or OFF), each LED is instructed to be turned on / off.

Japanese Patent Laying-Open No. 2005-28738 (page 5-6, FIG. 1)

  Recently, with the increase in speed and density of electronic devices such as image forming apparatuses, electromagnetic interference (EMI) emitted from electronic devices has become a problem. Here, in the LPH of Patent Document 1, common transfer signals CK1 and CK2 are output to a plurality of LED chips constituting the LED array, and the lighting timings of the LEDs in each LED chip are aligned. For this reason, the drive current for lighting the LED of each LED chip rises steeply, and electromagnetic wave radiation generated at that time increases.

  In addition, in the LPH of Patent Document 1, the transfer signals CK1 and CK2 are generated using a level shift circuit, so that the SLED can be driven at a lower voltage. In this level shift circuit, since a large transfer level shift voltage is generated in a short time, electromagnetic wave radiation during operation increases. In particular, in the LPH of Patent Document 1, since the level shift circuit supplies common transfer signals CK1 and CK2 to each LED chip, the magnitude of the electromagnetic wave radiation is increased accordingly.

  Further, in the LPH of Patent Document 1, since the level shift circuit generates a large transfer level shift voltage in a short time, the power supply voltage fluctuates instantaneously. Then, the transfer signals CK1 and CK2 output from the level shift circuit become unstable. When the transfer signals CK1 and CK2 become unstable, the thyristor constituting the SLED cannot be turned on, and there is a possibility of causing a lighting failure of the LED.

The present invention has been made to solve such technical problems, and an object of the present invention is to reduce electromagnetic radiation generated from a print head.
Another object is to stably operate a self-scanning LED composed of a plurality of LED chips.

  For this purpose, the print head to which the present invention is applied enables a lighting unit in which a plurality of lighting chips having a plurality of lighting elements are arranged, and a plurality of lighting elements in the plurality of lighting chips to be sequentially lit. A drive unit for setting, and the drive unit is characterized in that the lighting timing between the plurality of lighting chips is shifted within the range of the lighting cycle of one lighting element.

  In such a print head, the drive unit can shift the lighting timing between the plurality of lighting chips within a range of an integral multiple of the lighting cycle + less than the lighting cycle. In addition, the driving unit can shift the lighting timing for each of a plurality of groups configured by a plurality of lighting chips.

  From another point of view, the print head to which the present invention is applied includes a plurality of lighting chips each having a plurality of lighting elements and a plurality of switch elements provided corresponding to the lighting elements. A transfer signal generating unit that sequentially turns on a plurality of lighting elements in the lighting chip, and a transfer signal generating unit that generates a transfer signal for sequentially turning on a plurality of switching elements in the lighting chip A transfer start signal generation unit that outputs a transfer start signal instructing generation start of the transfer signal, and the transfer start signal generation unit corresponds to one lighting element for a plurality of groups configured by a plurality of lighting chips. The transfer start signal is output while shifting the timing within a range of less than the lighting cycle.

  Here, the transfer start signal generation unit can output a transfer start signal to a plurality of groups while shifting the timing within a range of an integral multiple of the lighting cycle + less than the lighting cycle. In addition, a lighting signal generation unit that generates lighting signals for a plurality of lighting elements in a plurality of lighting chips according to input image data can be further provided. In this case, the lighting signal generator further includes a plurality of wirings for supplying lighting signals to the plurality of lighting chips, and the two lighting chips to which the lighting signals are supplied from adjacent wirings belong to different groups. Can be a feature. The lighting signal generation unit and a plurality of lighting chips are mounted on the substrate, and the substrate is further provided with a plurality of wirings that supply a lighting signal to each of the plurality of lighting chips from the lighting signal generation unit. Two lighting chips provided side by side and supplied with lighting signals from adjacent wirings may belong to different groups. In addition, two lighting chips adjacent in the main scanning direction may belong to different groups. Further, the plurality of groups can include approximately the same number of lighting chips. The plurality of lighting chips constituting the lighting head are arranged in a staggered manner, and each of the plurality of groups is constituted by only the lighting chips arranged on the upstream side in the sub-scanning direction or the lighting chips arranged on the downstream side in the sub-scanning direction. Can be configured.

  According to the present invention, since the lighting timing of each of the plurality of lighting chips is shifted within the range of the lighting cycle for one lighting element, the rise of the drive current that flows when the lighting element is lit can be moderated. Electromagnetic radiation generated from the print head can be reduced.

The best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described below in detail with reference to the accompanying drawings.
<Embodiment 1>
FIG. 1 is a diagram illustrating an overall configuration of an image forming apparatus including a print head to which the exemplary embodiment is applied. The image forming apparatus shown in FIG. 1 is a so-called tandem type digital color printer 1. The image forming apparatus includes an image forming process unit 10, a control unit 30, and an image processing unit (IPS: Image Processing System) 40. Among these, the image forming process unit 10 forms an image corresponding to the image data of each color. The control unit 30 controls the operation of the image forming process unit 10. Further, the IPS 40 is connected to, for example, a personal computer (PC) 2 or an image reading device (IIT) 3, performs predetermined image processing on image data received from these, and outputs the image data to the image forming process unit 10.

  The image forming process unit 10 includes four image forming units 11Y, 11M, 11C, and 11K that are arranged in parallel at a predetermined interval. The image forming units 11Y, 11M, 11C, and 11K include a photosensitive drum 12, a charger 13, an LED print head (LPH) 14, a developing device 15, and a cleaner 16. Here, the photosensitive drum 12 as an image carrier forms an electrostatic latent image and carries a toner image. The charger 13 uniformly charges the surface of the photosensitive drum 12 with a predetermined potential. The LPH 14 as an exposure device exposes the photosensitive drum 12 charged by the charger 13 to form an electrostatic latent image. The developing device 15 develops the electrostatic latent image obtained by the LPH 14 with toner. The cleaner 16 cleans the surface of the photosensitive drum 12 after the primary transfer. Here, the image forming units 11Y, 11M, 11C, and 11K are configured in substantially the same manner except for the toner stored in the developing unit 15. The image forming units 11Y, 11M, 11C, and 11K respectively form yellow (Y), magenta (M), cyan (C), and black (K) toner images.

  The image forming process unit 10 includes an intermediate transfer belt 21, a primary transfer roll 22, a secondary transfer roll 23, a conveyance belt 24, and a fixing device 25. To the intermediate transfer belt 21, the toner images of the respective colors formed on the photosensitive drums 12 of the image forming units 11Y, 11M, 11C, and 11K are transferred in a multiple manner. A primary transfer roll 22 as a transfer device sequentially transfers (primary transfer) the color toner images of the image forming units 11Y, 11M, 11C, and 11K to the intermediate transfer belt 21. The secondary transfer roll 23 performs batch transfer (secondary transfer) of the superimposed toner image transferred onto the intermediate transfer belt 21 onto the paper P that is a recording material. The fixing device 25 fixes the secondary transferred image on the paper P.

  Now, an image forming operation in the digital color printer 1 will be described. In the digital color printer 1, the image forming process unit 10 performs an image forming operation based on a control signal such as a synchronization signal supplied from the control unit 30. At that time, the image data input from the PC 2 or IIT 3 is subjected to image processing by the image processing unit 40 and supplied to the image forming units 11Y, 11M, 11C, and 11K via an interface (not shown). In the yellow image forming unit 11Y, for example, the surface of the photosensitive drum 12 uniformly charged at a predetermined potential by the charger 13 is exposed by the LPH 14 that emits light based on the image data obtained from the image processing unit 40. Thus, an electrostatic latent image is formed on the photosensitive drum 12. The formed electrostatic latent image is developed by the developing device 15, and a yellow toner image is formed on the photosensitive drum 12. Similarly, magenta, cyan, and black toner images are formed in the other image forming units 11M, 11C, and 11K.

The color toner images formed by the image forming units 11Y, 11M, 11C, and 11K are sequentially electrostatically attracted by the primary transfer roll 22 onto the intermediate transfer belt 21 that rotates in the direction of arrow A in FIG. As a result, a superimposed toner image is formed on the intermediate transfer belt 21. The formed superimposed toner image is conveyed to a region (secondary transfer portion) where the secondary transfer roll 23 is disposed as the intermediate transfer belt 21 moves. When the superimposed toner image is conveyed to the secondary transfer unit, the paper P is supplied to the secondary transfer unit in accordance with the timing at which the toner image is conveyed to the secondary transfer unit. Then, the superimposed toner images are collectively electrostatically transferred onto the conveyed paper P by the transfer electric field formed by the secondary transfer roll 23 in the secondary transfer portion.
Thereafter, the sheet P on which the superimposed toner image has been electrostatically transferred is peeled off from the intermediate transfer belt 21 and conveyed to the fixing device 25 by the conveying belt 24. The unfixed toner image on the paper P conveyed to the fixing device 25 is fixed on the paper P by being subjected to a fixing process by heat and pressure by the fixing device 25. Then, the paper P on which the fixed image is formed is conveyed to a paper discharge placement portion (not shown) provided in the discharge portion of the image forming apparatus.

Next, the LPH 14 used in this image forming apparatus will be described in detail.
FIG. 2 is a diagram showing a configuration of an LED print head (LPH) 14 as a lighting unit or a lighting head. The LPH 14 includes a housing 61, an LED circuit board 62, and a self-scanning light emitting device (SLED) 63. The LPH 14 further includes a rod lens array 64, a holder 65, and a leaf spring 66. Among these, the housing 61 functions as a support for the LPH 14. Further, the LED circuit board 62 is configured by, for example, a printed circuit board, and is mounted with an SLED 63 and a drive circuit for driving the SLED 63. Further, the SLED 63 exposes the photosensitive drum 12 by emitting light. The rod lens array 64 images the light from the SLED 63 on the surface of the photosensitive drum 12. Furthermore, the holder 65 supports the rod lens array 64 and shields the SLED 63 from the outside. The leaf spring 66 biases the housing 61 toward the rod lens array 64.

The housing 61 is formed of a block or sheet metal such as aluminum or SUS, and supports the LED circuit board 62. The holder 65 supports the housing 61 and the rod lens array 64, and is set so that the light emitting point of the SLED 63 and the focal point of the rod lens array 64 coincide. Furthermore, the holder 65 is configured to seal the SLED 63. Therefore, it is possible to prevent dust from adhering to the SLED 63 from the outside. On the other hand, the leaf spring 66 urges the LED circuit board 62 toward the rod lens array 64 via the housing 61 so as to maintain the positional relationship between the SLED 63 and the rod lens array 64.
The LPH 14 configured in this manner is configured to be movable in the optical axis direction of the rod lens array 64 by an adjustment screw (not shown), and the imaging position (focal plane) of the rod lens array 64 is the surface of the photosensitive drum 12. It is adjusted so that it is located above.

  FIG. 3 is a plan view of the LED circuit board 62 shown in FIG. On the LED circuit board 62, 60 LED chips 70 (C1 to C60) as lighting chips constituting the SLED 63 are arranged in a line with high accuracy so as to be parallel to the axial direction of the photosensitive drum 12. . Here, FIG. 4 is an enlarged view of the connecting portion of each LED chip 70. As shown in FIG. 4, at the end of each LED chip 70, the end boundary of the LED array is configured to be continuously arranged in the main scanning direction. That is, the LED chips 70 are arranged in a staggered manner. In addition, in FIG. 4, the connection part of C1, C2, and C3 is shown as an example.

  In the LPH 14 according to the present embodiment, 128 LEDs (lighting elements) are mounted on each LED chip 70. Therefore, the entire SLED 63 having 60 LED chips 70 is provided with 7680 LEDs. Further, the distance from the outer end portion of C1 to the outer end portion of C60 (the length in the main scanning direction of the SLED 63) is set to 324 mm in order to correspond to the image formation on the sheet P of A3 Nobi. Therefore, the interval between adjacent LEDs is set to about 42.2 μm, and the output resolution of the LPH 14 in the main scanning direction is 600 dpi (dot per inch).

  The LED circuit board 62 is provided with a signal generation circuit 100 and a level shift circuit 104 for driving the SLED 63. In the present embodiment, the signal generation circuit 100 and the level shift circuit 104 function as a drive unit. Further, the LED circuit board 62 includes a power supply circuit 101 for stabilizing the output voltage, an EEPROM 102 for storing light amount correction value data of each LED constituting the SLED 63, and the digital color printer 1 main body. A harness 103 that performs transmission and reception is provided.

  FIG. 5 is a diagram showing a wiring configuration of the LED circuit board 62. As shown in FIG. 5, the signal generation circuit 100 outputs a lighting signal ΦI (ΦI1 to ΦI60) to each LED chip 70 (C1 to C60). Further, the signal generation circuit 100 divides each LED chip 70 (C1 to C60) into 8 groups (8 groups), and the transfer signal CK1 (CK1_1 to CK1_8) and the transfer signal CK2 (CK2_1 to CK2_8) for each group Is output. Details of grouping will be described later.

  On the LED circuit board 62, a power supply line 105 of Vcc = + 3.3V for supplying power to each LED chip 70 (Chip 1 to Chip 60) and a power supply line 106 grounded (GND) are provided. Further, lighting signal lines 107 (107_1 to 107_60) for transmitting the lighting signals ΦI (ΦI1 to ΦI60) from the signal generation circuit 100 to the LED chips 70 (C1 to C60) are also provided. Further, first transfer signal lines 108 (108_1 to 108_8) for transmitting the transfer signals CK1 (CK1_1 to CK1_8) are also provided. Furthermore, second transfer signal lines 109 (109_1 to 109_8) for transmitting the transfer signals CK2 (CK2_1 to CK2_8) are also provided.

  The corresponding lighting signals ΦI (ΦI1 to ΦI60) are input to the LED chips 70 (C1 to C60) via the lighting signal line 107. Further, each LED chip 70 (C1 to C60) receives a transfer signal CK1 (CK1_1 to CK1_8) via a first transfer signal line 108, and a transfer signal CK2 (CK2_1 to CK2_1 to CK2_1) via a second transfer signal line 109. CK2_8) are input respectively.

  FIG. 6 is a diagram for explaining grouping of the LED chips 70 (C1 to C60) described above. FIG. 6A illustrates the state of grouping, and FIG. 6B illustrates the group name, component chip name, and component chip number. In the present embodiment, sixty LED chips 70 are first divided into four in the main scanning direction, and further divided into two in the sub scanning direction, upstream and downstream, thereby forming eight groups Gr1 to Gr8. ing. Specifically, first, the first group Gr1 is configured by the odd-numbered LED chips 70 from C1 to C15. The even-numbered LED chips 70 from C2 to C14 constitute the second group Gr2. Furthermore, the third group Gr3 is configured by the odd-numbered LED chips 70 from C17 to C29. Furthermore, the fourth group Gr4 is configured by the even-numbered LED chips 70 from C16 to C30. Further, the fifth group Gr5 is configured by the odd-numbered LED chips 70 from C31 to C45. Furthermore, the sixth group Gr6 is configured by the even-numbered LED chips 70 from C32 to C44. Furthermore, the seventh group Gr7 is configured by the odd-numbered LED chips 70 from C47 to C59. And the 8th group Gr8 is comprised by the even-numbered LED chip 70 from C46 to C60. Here, each of the first group Gr1, the fourth group Gr4, the fifth group Gr5, and the eighth group Gr8 has eight LED chips 70 (8Chip). On the other hand, the second group Gr2, the third group Gr3, the sixth group Gr6, and the seventh group Gr7 each have seven LED chips 70 (7Chip).

  As shown in FIG. 5, the transfer signals CK1_1 and CK2_1 corresponding to the first group Gr1 to which the LED chip 70 (C1) belongs are input to the LED chip 70 (C1). On the other hand, the transfer signals CK1_2 and CK2_2 corresponding to the second group Gr2 to which the LED chip 70 (C2) belongs are input to the LED chip 70 (C2) adjacent to the LED chip 70 (C1). Similarly, the transfer signals CK1_3 to CK1_7 and CK2_3 to CK2_7 (not shown) corresponding to each group are input to the LED chips 70 belonging to the third group Gr3 to the seventh group Gr7. The transfer signals CK1_8 and CK2_8 corresponding to the eighth group Gr8 to which the LED chip 70 (C60) belongs are input to the LED chip 70 (C60).

FIG. 7 is a diagram illustrating the configuration of the LED chip 70, the signal generation circuit 100, and the level shift circuit 104. However, in FIG. 6, only C1 is shown among the several LED chips 70 which comprise SLED63. The other LED chips 70, C2 to C60, also have the same configuration as C1.
The LED chip 70 is connected to the signal generation circuit 100 via the level shift circuit 104. The level shift circuit 104 has a configuration in which a resistor R1B and a capacitor C1A are connected in parallel, and a resistor R2B and a capacitor C2A are connected in parallel. One end of each is connected to the input terminal of the LED chip 70 and the other end is connected to the output terminal of the signal generating circuit 100. In the level shift circuit 104, based on the transfer signals CK1R and CK1C and the transfer signals CK2R and CK2C output from the signal generation circuit 100, the transfer signal CK1 (CK1_1 in the case of the LED chip 70 (C1), and so on) and the transfer signal CK2 (CK2_1) is output to the LED chip 70 (C1). The LED chip 70 is connected to the signal generation circuit 100 via the drive current setting resistor RID. The signal generation circuit 100 outputs the lighting signal ΦI (ΦI1) to the LED chip 70 (C1) via the driving current setting resistor RID by outputting the driving signal ID. The signal generation circuit 100 receives the line synchronization signal Lsync, the video data Vdata, the clock signal clk, the reset signal RST, and the shift signal Shift. Based on these various signals, the signal generation circuit 100 generates and outputs transfer signals CK1R and CK1C, transfer signals CK2R and CK2C, and a drive signal ID.

As shown in FIG. 7, the LED chip 70 includes 128 thyristors S1 to S128 as switching elements and 128 LEDs L1 to L128 as lighting elements.
In addition, the LED chip 70 transfers 128 diodes D1 to D128, 128 resistors R1 to R128, and further prevents the excessive current from flowing through the first transfer signal line 108_1 and the second transfer signal line 109_1. Current limiting resistors R1A and R2A are provided.
In the following description, a part mainly composed of thyristors S1 to S128 and diodes D1 to D128 for controlling supply of current to the LEDs L1 to L128 is referred to as a transfer unit.

In the LED chip 70 of the present embodiment, the anode terminals (input terminals) A1 to A128 of the thyristors S1 to S128 are connected to the power supply line 105. A power supply voltage Vcc (= + 3.3 V) is supplied to the power supply line 105.
The cathode terminals (output terminals) K1, K3, ..., K125, K127 of the odd-numbered thyristors S1, S3, ..., S125, S127 are connected to the level shift circuit 104, the first transfer signal line 108 (108_1) from the signal generation circuit 100. ), And the transfer signal CK1 (CK1_1) is transmitted through the transfer current limiting resistor R1A. The cathode terminals (output terminals) K2, K4,..., K126, and K128 of the even-numbered thyristors S2, S4,. 109 (109_1) and the transfer signal CK2 (CK2_1) are transmitted via the transfer current limiting resistor R2A.

On the other hand, gate terminals (control terminals) G1 to G128 of the thyristors S1 to S128 are respectively connected to the power supply line 106 via resistors R1 to R128 provided corresponding to the thyristors S1 to S128. The power supply line 106 is grounded (GND).
The gate terminals G1 to G128 of the thyristors S1 to S128 are connected to the gate terminals of the LEDs L1 to L128 provided corresponding to the thyristors S1 to S128, respectively.
Furthermore, the cathode terminals of the diodes D1 to D128 are connected to the gate terminals G1 to G128 of the thyristors S1 to S128. The gate terminals G1 to G127 of the thyristors S1 to S127 are connected to the anode terminals of the next-stage diodes D2 to D128, respectively. That is, the diodes D1 to D128 are connected in series with the gate terminals G1 to G127 interposed therebetween.
Furthermore, the anode terminal of the diode D1 is connected to the signal generation circuit 100 via the transfer current limiting resistor R2A, the second transfer signal line 109 (109_1), and the level shift circuit 104. For this reason, the transfer signal CK2 (CK2_1) is transmitted to the diode D1. The cathode terminals of the LEDs L1 to L128 are connected to the signal generation circuit 100 via the lighting signal line 107 (107_1) and the drive current setting resistor RID, and the lighting signal ΦI (ΦI1) is transmitted.

  The LED chip 70 is provided with a light shielding mask (not shown) so as to cover the thyristors S1 to S128 and the diodes D1 to D128. During the image forming operation, the light shielding mask blocks light emission from the thyristors S1 to S128 when the current is flowing and the diodes D1 to D128 when the current is flowing, and unnecessary light is generated. Exposure of the photosensitive drum 12 is suppressed.

FIG. 8 is a diagram illustrating a configuration of the signal generation circuit 100. The signal generation circuit 100 includes an exposure control unit 110 and a block driving unit 120.
Among these, the exposure control unit 110 includes a transfer start signal generation unit 111 and a video data sorting unit 112. Here, the transfer start signal generation unit 111 receives the first transfer start signals SG1 to SG8 corresponding to the first block Gr1 to the eighth block Gr8 based on the line synchronization signal Lsync, the clock signal clk, and the shift signal Shift. A transfer start signal SG8 is generated and output. In addition, the video signal sorting unit 112 sorts the input video data Vdata for each group in units of the first block Gr1 to the eighth block Gr8, and the first group Gr1 to the eighth group Gr8. The corresponding first video data VG1 to eighth video data VG8 are output.

  On the other hand, eight (120_1 to 120_8) block driving units 120 are provided corresponding to the first block Gr1 to the eighth block Gr8. Each of the block driving units 120 (120_1 to 120_8) includes a transfer signal generation unit 121 (121_1 to 121_8) and a lighting signal generation unit 122 (122_1 to 122_8). The transfer signal generation unit 121 generates and outputs transfer signals CK1R, CK1C, CK2R, and CK2C based on the transfer start signal input from the exposure control unit 110. For example, in the case of the block driver 120_1, the transfer signal generator 121_1 generates and outputs transfer signals CK1R_1, CK1C_1, CK2R_1, and CK2C_1 based on the first transfer start signal SG1. The transfer signals CK1R_1, CK1C_1, CK2R_1, and CK2C_1 output from the transfer signal generator 121_1 are output as transfer signals CK1_1 and CK2_1 by the level shift circuit 104. The transfer signals CK1_1 and CK2_1 output from the level shift circuit 104 are input to the LED chips 70 (C1, C3, C5, C7, C9, C11, C13, C15: refer to FIG. 6) constituting the first group Gr1. The Further, the lighting signal generator 122 outputs a lighting signal ΦI based on the sorted video data input from the exposure controller 110. For example, in the case of the block driving unit 120_1, the lighting signal generation unit 122_1 is based on the first video data VG1, and the LED chips 70 (C1, C3, C5, C7, C9, C11, C13, C15: Refer to FIG. 6) and generate and output lighting signals ΦI1, ΦI3, ΦI5, ΦI7, ΦI9, ΦI11, ΦI13, and ΦI15.

FIG. 9 is a diagram showing a configuration of the lighting signal generator 122 shown in FIG. FIG. 9 illustrates the lighting signal generation unit 122_1 corresponding to the first group Gr1 among the eight lighting signal generation units 122. The lighting signal generation unit 122 includes an image data rearrangement unit 123, a lighting pulse calculation unit 124, and a pulse generator 125.
The image data rearrangement unit 123 performs serial-parallel conversion on the first video data VG1 sent from the exposure control unit 110 (see FIG. 8), and the eight LED chips 70 (C1) constituting the first group Gr1. , C3, C5, C7, C9, C11, C13, and C15 (see FIG. 6), the image data group is divided into 8 image data groups (128 dots per image). The image data rearrangement unit 123 rearranges the eight image data groups subjected to serial-parallel conversion in the order of lighting (L1 → L128).

  A total of eight lighting pulse calculation units 124 are provided corresponding to the eight LED chips 70 constituting the first group Gr1. The lighting pulse calculation unit 124 (124_1 to 124_8) includes image data corresponding to each LED chip 70 (128 LEDs) sent from the image data rearrangement unit 123 and each LED read from the EEPROM 102. The number of lighting pulses of each LED is calculated using the light amount correction value. For example, when the LED is turned on, the basic pulse number is 8 bits (256), and the light amount correction value (correction pulse number) is appropriately selected from the range of 6 bits (0 to 63). Shall. In this case, the lighting pulse calculation unit 124 calculates the number of lighting pulses = the number of basic pulses + the number of correction pulses for the LED to be lit and outputs it as lighting pulse number data. Here, the light amount correction value (the number of correction pulses) is determined in advance so that the light amounts of the respective LEDs constituting the SLED 63 are substantially uniform.

  Similar to the lighting pulse calculator 124, a total of eight pulse generators 125 are provided corresponding to the eight LED chips 70 constituting the first group Gr1. The pulse generator 125 (125_1 to 125_8) is input with lighting pulse number data corresponding to each LED chip 70 (128 LEDs) sent from the corresponding lighting pulse calculator 124 (124_1 to 124_8). The lighting time of each LED is determined using the clock signal clk. In this case, the pulse generator 125 calculates lighting period = number of lighting pulses × clock signal clk period (clock period) corresponding to each LED. Then, the pulse generator 125 (125_1 to 125_8) has a lighting signal ΦI (in this example, ΦI1, ΦI3,..., ΦI15) in which the amount of light is changed by pulse width modulation according to the lighting time obtained for each LED. 8) are generated respectively. Then, the pulse generator 125 (125_1 to 125_8) outputs the generated lighting signals ΦI1, ΦI3,..., ΦI15 to the corresponding LED chips 70 (C1, C3,..., C15), respectively. Thereby, in each LED chip 70 which comprises 1st group Gr1, LED used as lighting object will light for the set lighting time.

On the other hand, for the second group Gr2 to the eighth group Gr8, the lighting signal ΦI corresponding to each LED chip 70 is similarly determined in the lighting signal generator 122 (122_2 to 122_8).
However, the lighting signal generators 122 corresponding to the fourth group Gr4, the fifth group Gr5, and the eighth group Gr8 having the same eight LED chips 70 as the first group Gr1 are the lighting pulse calculator 124 and the pulse generator. Eight 125 each. On the other hand, unlike the first group Gr1, the lighting signal generators 122 corresponding to the second group Gr2, the third group Gr3, the sixth group Gr6, and the seventh group Gr7, which have seven LED chips 70, calculate the lighting pulse. Seven units 124 and seven pulse generators 125 are provided.

  FIG. 10 is a timing chart for explaining the operation of the transfer start signal generator 111 shown in FIG. The transfer start signal generator 111 generates the first transfer start signal SG1 to the eighth transfer start signal SG8 corresponding to the first group Gr1 to the eighth group Gr8 based on the input line synchronization signal Lsync. Then, the generated first transfer start signal SG1 to eighth transfer start signal SG8 are output to the block driving units 120 (120_1 to 120_8) provided corresponding to the first group Gr1 to the eighth group Gr8, respectively. This operation will be specifically described. The transfer start signal generation unit 111 generates a first transfer start signal SG1 synchronized with the falling timing of the line synchronization signal Lsync. Further, the transfer start signal generator 111 generates the second transfer start signal SG2 to the eighth transfer start signal SG8 that are sequentially delayed from the first transfer start signal SG1 by the delay time t. Here, a period T1 from when the first first transfer start signal SG1 is turned on to when the last eighth transfer start signal SG8 is turned off is set within a lighting cycle to be described later (in the following description, the lighting is performed). Called period T1). Therefore, the delay time t is 1/8 or less of the lighting cycle T1. The delay time t used for setting the first transfer start signal SG1 to the eighth transfer start signal SG8 is input to the transfer start signal generator 111 as a shift signal Shift. Note that the delay time t is not necessarily uniform.

Next, a signal (drive signal) for driving the SLED 63 (each LED chip 70) output from the signal generation circuit 100 and the level shift circuit 104 will be described.
FIG. 11 is a timing chart for explaining drive signals output from the signal generation circuit 100 and the level shift circuit 104. Note that the timing chart shown in FIG. 10 shows a case where all the LEDs L1 to L128 perform optical writing (light emission) in the LED chips 70 belonging to a predetermined group.

(1) First, when the reset signal RST is input to the signal generation circuit 100, the signal generation circuit 100 (transfer signal generation unit 121) sets the transfer signal CK1R to “H” and the transfer signal CK1C to “H”. To "". In response to this, the level shift circuit 104 outputs the transfer signal CK1 as “H”. On the other hand, the transfer signal generator 121 sets the transfer signal CK2R to “L” and the transfer signal CK2C to “L”. In response to this, the level shift circuit 104 outputs the transfer signal CK2 as “L”. As a result, in the LED chip 70, all the thyristors S1 to S128 are turned off (FIG. 11A).
In this state, since the video data Vdata is not input to the signal generation circuit 100, the lighting signal ΦI is set to “H” (FIG. 11 (H)).

  (2) Following the reset signal RST, when the line synchronization signal Lsync input to the signal generation circuit 100 becomes “H” for a predetermined period, the transfer start signal generator 111 generates a transfer start signal SGX (X = 1-8) is set to “H” (FIG. 11A). Thereby, the operation of the LED chip 70 is started. Then, in synchronization with the transfer start signal SGX, the transfer signal generator 121 sets the transfer signal CK2C and the transfer signal CK2R to “H” as shown in FIGS. 11E and 11F. In response to this, the level shift circuit 104 sets the transfer signal CK2 to “H” as shown in FIG. 11G (FIG. 11B).

  (3) Next, as shown in FIG. 11C, the transfer signal generator 121 sets the transfer signal CK1R to “L” (FIG. 11C). In response to this, in the level shift circuit 104, the electric charge accumulated in the capacitor C1A flows in the direction toward the resistor R1B, and eventually the potential of the transfer signal CK1 becomes GND. Here, since the potential of the transfer signal CK1C is set to + 3.3V, the potential across the capacitor C1A is + 3.3V (= Vcc).

(4) Subsequently, as shown in FIG. 11B, the transfer signal generator 121 sets the transfer signal CK1C to “L” (FIG. 11D).
In this state, the gate current starts to flow through the thyristor S1. At that time, a tri-state buffer (not shown) corresponding to the resistor R1B is set to high impedance (Hiz) to prevent current backflow.
Thereafter, the thyristor S1 starts to be turned on by the gate current flowing through the thyristor S1, and the gate current gradually increases. At the same time, as the current flows into the capacitor C1A of the level shift circuit 104, the potential of the transfer signal CK1 also gradually increases.

(5) After the elapse of a predetermined time (the time when the potential of the transfer signal CK1 becomes close to GND), the transfer signal generator 121 sets the transfer signal CK1R to “L” (FIG. 11E). Then, the potential of the transfer signal CK1 rises due to the rise of the potential of the gate terminal G1, and accordingly, a current starts to flow to the resistor R1B side of the level shift circuit 104. On the other hand, as the potential of the transfer signal CK1 increases, the current flowing into the capacitor C1A of the level shift circuit 104 gradually decreases.
When the thyristor S1 is completely turned on and enters a steady state, a current for maintaining the on state of the thyristor S1 flows to the resistor R1B of the level shift circuit 104, but does not flow to the capacitor C1A. When the transfer signal CK1R is set to “L”, a tristate buffer (not shown) corresponding to the capacitor C1A is set to high impedance (HiZ) as shown in FIG. e)).

  (6) With the thyristor S1 fully turned on, as shown in FIG. 11H, the lighting signal ΦI generated by the lighting signal generator 122 based on the video data obtained by sorting the video data Vdata. Are both set to “L” (FIG. 11F). At this time, since the potential of the gate terminal G1> the potential of the gate terminal G2, the LED L1 is turned on earlier and is lit. Since the potential of the signal line rises as the LED L1 is turned on, the LEDs L2 to L128 are not turned on. That is, only the LED L1 having the highest gate voltage is turned on (lit).

(7) Next, as shown in FIG. 11 (F), when the transfer signal generator 121 sets the transfer signal CK2R to “L” (FIG. 11 (g)), the current is the same as in FIG. 11 (c). And a voltage is generated across the capacitor C2A of the level shift circuit 104.
(8) As shown in FIG. 11E, in this state, the transfer signal generator 121 sets the transfer signal CK2C to “L” (FIG. 11H). Accordingly, thyristor S2 is turned on.
(9) Then, as shown in FIGS. 11B and 11C, when the transfer signal generator 121 simultaneously sets the transfer signals CK1C and CK1R to H (FIG. 11 (i)), the transfer signal CK1 is “H”. It becomes. When the transfer signal CK1 becomes “H”, the thyristor S1 is turned off and discharged through the resistor R1, so that the potential of the gate terminal G1 gradually decreases. At that time, the thyristor S2 is completely turned on by the rise of the potential of the gate terminal G2.

(10) In the state where the thyristor S2 is completely turned on, as shown in FIG. 11 (H), both the lighting signals ΦI are set to “L”. Thereby, LED L2 lights up. Further, the LED L2 can be turned off by setting the lighting signal ΦI to “H”. In this case, since the potential of the gate terminal G1 is already lower than the potential of the gate terminal G2, the LED L1 is not turned on.
(11) Then, as shown in FIG. 11C, the transfer signal generator 121 sets the transfer signal CK1R to L (FIG. 11 (j)). In response to this, in the level shift circuit 104, the electric charge accumulated in the capacitor C1A flows in the direction toward the resistor R1B, and eventually the potential of the transfer signal CK1 becomes GND.

(12) Thereafter, the above-described operations are sequentially performed, and the other LEDs L3 to L128 are sequentially turned on.
After the terminal LED L128 in the LED chip 70 is extinguished, the transfer signals CK1C and CK1R are set to “H”, the transfer signal CK1 is set to “H”, and the transfer signals CK2C and CK2R are set to “H”. By setting “H” to “H”, both the transfer signal CK1 and the transfer signal CK2 are kept in the “H” state for a predetermined time. As a result, all thyristors S1 to S128 are turned off. Therefore, in this state, no current flows through all the thyristors S1 to S128, so that the thyristors S1 to S128 are held in the off state (not lit).

  In FIG. 11, a period from when the transfer signal CK1 (CK2) becomes “L” to when the other transfer signal CK2 (CK1) becomes “L” is a lighting cycle T1. A period from when the transfer start signal SGX becomes “L” to when the next transfer start signal SGX becomes “L” is referred to as a one-line transfer period T2. This one-line transfer period T2 is the same as the cycle of the line synchronization signal Lsync.

  In the present embodiment, as described with reference to FIG. 10, the first transfer start signal SG1 to the eighth transfer start signal SG8 corresponding to the first group Gr1 to the eighth group Gr8 within the range of the lighting cycle T1. The output timing is different. For this reason, when it sees in the whole SLED63, the lighting timing of LED in each group changes delicately.

  FIG. 12 is a timing chart for explaining lighting timings of the LEDs in the first group Gr1, the second group Gr2, and the third group Gr3. In FIG. 12, in the first group Gr1, lighting control is performed in synchronization with the first transfer start signal SG1 output at the falling timing of the line synchronization signal Lsync. That is, based on the first transfer start signal SG1, lighting control of each LED L1 to L128 in each LED chip 70 (C1, C3, C5, C7, C9, C11, C13, C15) constituting the first group Gr1 is performed. Is called. In the second group Gr2, lighting control is performed in synchronization with the second transfer start signal SG2 output at a timing delayed by the delay time t from the first transfer start signal SG1. That is, based on the second transfer start signal SG2, lighting control of each LED L1 to L128 in each LED chip 70 (C2, C4, C6, C8, C10, C12, C14) configuring the second group Gr2 is performed. Further, in the third group Gr3, it is synchronized with the third transfer start signal SG3 output at a timing delayed by the delay time t from the second transfer start signal SG2 (timing delayed by the delay time 2t from the first transfer start signal SG1). Then, lighting control is performed. That is, based on the third transfer start signal SG3, lighting control of each LED L1 to L128 in each LED chip 70 (C17, C19, C21, C23, C25, C27, C29) configuring the third group Gr3 is performed.

  At this time, if all the LEDs are turned on as shown in FIG. 12, the lighting start timing of the LED L2 in the second group Gr2 is delayed by the delay time t with respect to the lighting start timing of the LED L1 in the first group Gr1. . Further, the lighting start timing of the LED L1 in the third group Gr3 is delayed by the delay time t with respect to the lighting start timing of the LED L2 in the second group Gr2. This also applies to the subsequent LEDs L2, L3, L4,. In addition, in the other fourth group Gr4 to eighth group Gr8 (not shown), the lighting timing of each LED is sequentially delayed.

  Then, the total value of the drive current (current flowing from the anode to the cathode of the LED) that flows when the LED is turned on gradually increases and then gradually decreases due to such a difference in lighting start time for each group. The process will be repeated. In other words, by staggering the output timing of the first transfer start signal SG1 to the eighth transfer start signal SG8 sequentially, it is possible to prevent the total value of the drive currents from rising sharply. As a result, the level of electromagnetic radiation generated from the LPH 14 and thus the color digital printer 1 can be reduced.

  Also in the level shift circuit 104, the timing of changing the transfer signals CK1 and CK2 slightly changes for each group by slightly shifting the output timing of the first transfer start signal SG1 to the eighth transfer start signal SG8. Thereby, the generation timing of the transfer level shift voltage in the level shift circuit 104 can be slightly shifted between groups, and the level of electromagnetic radiation generated from this surface can be reduced. And since the shift in the output timing of the first transfer start signal SG1 to the eighth transfer start signal SG8 is within the lighting cycle T1 necessary for emitting one dot of LED, in the electrostatic latent image obtained by exposure, It can be said that there is almost no deviation in the sub-scanning direction, and the image quality is hardly affected.

Here, FIG. 13 shows an example in which the first transfer start signal SG1 to the eighth transfer start signal SG8 are simultaneously output in synchronization with the conventional lighting control, that is, the line synchronization signal Lsync. However, in FIG. As in FIG. 12, only the first group Gr1, the second group Gr2, and the third group Gr3 are shown.
In such a case, the lighting start timing of the LEDs in each group is exactly the same. Then, unlike the one shown in FIG. 12, the total value of the drive current repeats the process of rising sharply and then falling sharply. For this reason, the generation amount of electromagnetic radiation increases more than the example shown in FIG. Also in the level shift circuit 104, the output timings of the first transfer start signal SG1 to the eighth transfer start signal SG8 are the same, so the timings at which the transfer signals CK1 and CK2 are changed are synchronized across the groups. Therefore, the level of electromagnetic radiation generated from this surface also increases.

  FIG. 14 is a timing chart for explaining another example of the lighting timing deviation of each LED in the first group Gr1, the second group Gr2, and the third group Gr3. In FIG. 14, in the first group Gr1, lighting control is performed in synchronization with the first transfer start signal SG1 output at the falling timing of the line synchronization signal Lsync. In the second group Gr2, the lighting control is performed in synchronization with the second transfer start signal SG2 output at a timing delayed by 2T1 of the lighting cycle T1 and the delay time t from the first transfer start signal SG1. Further, in the third group Gr3, lighting control is performed in synchronization with the third transfer start signal SG3 output at a timing delayed by the lighting cycle T1 and the delay time t from the first transfer start signal SG1.

  Therefore, in this example, by delaying the LED lighting start timing by an integral multiple of the lighting cycle T1 between groups, the exposure dots can be shifted in the sub-scanning direction by the number of shifted lighting cycles T1. Thereby, the sub-scanning direction deviation can be adjusted. Further, since the lighting timing is further shifted by the delay time t, generation of electromagnetic wave radiation can be suppressed as in the above-described example.

<Embodiment 2>
The present embodiment is substantially the same as the first embodiment, but the grouping method of 60 LED chips 70 constituting the SLED 63 is different. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 15 is a diagram for explaining grouping of the LED chips 70 (C1 to C60) in the present embodiment. FIG. 15A illustrates the state of grouping, and FIG. 15B illustrates the group name, the configuration chip name, and the number of configuration chips. In the present embodiment, 60 LED chips 70 are divided into an upstream side and a downstream side in the sub-scanning direction so that the LED chips 70 adjacent in the main scanning direction do not belong to the same group, and Eight groups Gr1 to Gr8 are configured so that two LED chips 70 adjacent in the scanning direction belong to the same group. The first group Gr1 includes eight LED chips 70 of C1, C2, C17, C18, C33, C34, C49, and C50. The second group Gr2 includes eight LED chips 70 of C3, C4, C19, C20, C35, C36, C51, and C52. The third group Gr3 includes eight LED chips 70 of C5, C6, C21, C22, C37, C38, C53, and C54. The fourth group Gr4 includes eight LED chips 70 of C7, C8, C23, C24, C39, C40, C55, and C56. The fifth group Gr5 includes eight LED chips 70 of C9, C10, C25, C26, C41, C42, C57, and C58. The sixth group Gr6 includes eight LED chips 70 of C11, C12, C27, C28, C43, C44, C59, and C60. The seventh group Gr7 includes six LED chips 70 of C13, C14, C29, C30, C45, and C46. The eighth group Gr8 includes six LED chips 70 of C15, C16, C31, C32, C47, and C48. Therefore, each of the first group Gr1 to the sixth group Gr6 has eight LED chips 70 (8Chip). On the other hand, the seventh group Gr7 and the eighth group Gr8 each have six LED chips 70 (6Chip).

  FIG. 16 shows an example of a wiring pattern formed on the LED circuit board 62 shown in FIG. In FIG. 16, the description of the LED circuit board 62 is omitted. In FIG. 16, C1 to C18 of the 60 LED chips 70 are illustrated, and only the wiring pattern is illustrated for C19 to C60, and the description of the LED chip 70 is omitted. In the present embodiment, the corresponding lighting signal lines 107 (107_1, 107_3,... 107_59) are routed from the upper side in the figure to the odd-numbered LED chips 70 (C1, C3,..., C59). . In the following description, the lighting signal lines 107_1, 107_3,..., 107_59 for the odd-numbered LED chips 70 are referred to as a first lighting signal line group 107A. On the other hand, for the even-numbered LED chips 70 (C2, C4,..., C60), the corresponding lighting signal lines 107 (107_2, 107_4,..., 107_60) are routed from the lower side in the drawing. In the following description, the lighting signal lines 107_2, 107_4,..., 107_60 for the even-numbered LED chips 70 are referred to as a second lighting signal line group 107B.

  In addition to the lighting signal line 107, the LED circuit board 62 includes the power supply line 105, the ground line 106, the first transfer signal line 108 (108_1 to 108_8), and the second transfer signal line 109 as described above. (109_1 to 109_8) are also formed. However, these descriptions are omitted in FIG.

  As described above, one end of each lighting signal line 107 is connected to the signal generating circuit 100 shown in FIG. 3 and the other end is connected to the corresponding LED chip 70. As shown in FIG. 3, the LED chip 70 (C1) on one end side in the main scanning direction is closest to the signal generating circuit 100, and the LED chip 70 (C60) on the other end side in the main scanning direction is a signal. They are respectively arranged on the side farthest from the generation circuit 100.

  Each of the lighting signal lines 107_1 to 107_59 constituting the first lighting signal line group 107A is wired substantially parallel to the arrangement direction of the odd-numbered LED chips 70. The lighting signal line 107_1 for supplying the lighting signal ΦI1 to the LED chip 70 (C1) is closest to the LED chip 70, and the lighting signal line 107_59 for supplying the lighting signal ΦI59 to the LED chip 70 (C59) is the LED chip 70. Each is wired on the side farthest from. In the first lighting signal line group 107A, the lighting signal ΦI3 is supplied to the LED chip 70 (C3) adjacent in the main scanning direction next to the lighting signal line 107_1 that supplies the lighting signal ΦI1 to the LED chip 70 (C1). A lighting signal line 107_3 is provided. Further, a lighting signal line 107_5 for supplying the lighting signal ΦI5 to the LED chip 70 (C5) adjacent in the main scanning direction is provided next to the lighting signal line 107_3 for supplying the lighting signal ΦI3 to the LED chip 70 (C3). ing. That is, in the first lighting signal line group 107A, odd-numbered lighting signal lines 107_1, 107_3, 107_5,..., 107_59 are sequentially wired in order from the side closer to the LED chip 70.

  On the other hand, each of the lighting signal lines 107_2 to 107_60 constituting the second lighting signal line group 107B is wired substantially in parallel with the arrangement direction of the even-numbered LED chips 70. The lighting signal line 107_2 for supplying the lighting signal ΦI2 to the LED chip 70 (C2) is on the side closest to the LED chip 70, and the lighting signal line 107_60 for supplying the lighting signal ΦI60 to the LED chip 70 (C60) is the LED chip 70. Each is wired on the side farthest from. In the second lighting signal line group 107B, the lighting signal ΦI4 is supplied to the LED chip 70 (C4) adjacent in the main scanning direction next to the lighting signal line 107_2 that supplies the lighting signal ΦI2 to the LED chip 70 (C2). A lighting signal line 107_4 is provided. A lighting signal line 107_6 for supplying the lighting signal ΦI6 to the LED chip 70 (C6) adjacent in the main scanning direction is provided next to the lighting signal line 107_4 for supplying the lighting signal ΦI4 to the LED chip 70 (C4). ing. That is, in the second lighting signal line group 107B, even-numbered lighting signal lines 107_2, 107_4, 107_6,..., 107_60 are sequentially wired in order from the side closer to the LED chip 70.

Here, in the present embodiment, grouping as shown in FIG. 15 is performed for each LED chip 70.
Therefore, as shown in FIG. 16, for example, in the first lighting signal line group 107A, adjacent lighting signal lines 107 always supply the lighting signal ΦI to the LED chips 70 belonging to another group. Become. For example, the LED chip 70 (C1) to which the lighting signal line 107_1 is connected belongs to the first group Gr1. In contrast, the LED chip 70 (C3) to which the lighting signal line 107_3 adjacent to the lighting signal line 107_1 is connected belongs to the second group Gr2. The LED chip 70 (C5) to which the lighting signal line 107_5 adjacent to the lighting signal line 107_3 is connected belongs to the third group Gr3. Furthermore, the LED chip 70 (C7) to which the lighting signal line 107_7 adjacent to the lighting signal line 107_5 is connected belongs to the fourth group Gr4. Furthermore, the LED chip 70 (C9) to which the lighting signal line 107_9 adjacent to the lighting signal line 107_7 is connected belongs to the fifth group Gr5. The LED chip 70 (C11) to which the lighting signal line 107_11 adjacent to the lighting signal line 107_9 is connected belongs to the sixth group Gr6. Further, the LED chip 70 (C13) to which the lighting signal line 107_13 adjacent to the lighting signal line 107_11 is connected belongs to the seventh group Gr7. Furthermore, the LED chip 70 (C15) to which the lighting signal line 107_15 adjacent to the lighting signal line 107_13 is connected belongs to the eighth group Gr8. The LED chip 70 (C17) to which the lighting signal line 107_17 adjacent to the lighting signal line 107_15 is connected again belongs to the first group Gr1. As described above, the odd-numbered LED chips 70 are configured to sequentially belong to the first group Gr1 to the eighth group Gr8 along the main scanning direction.

  For example, also in the second lighting signal line group 107B, the lighting signal lines 107 adjacent to each other always supply the lighting signal ΦI to the LED chips 70 belonging to another group. For example, the LED chip 70 (C2) to which the lighting signal line 107_2 is connected belongs to the first group Gr1. On the other hand, the LED chip 70 (C4) to which the lighting signal line 107_4 adjacent to the lighting signal line 107_2 is connected belongs to the second group Gr2. The LED chip 70 (C6) to which the lighting signal line 107_6 adjacent to the lighting signal line 107_4 is connected belongs to the third group Gr3. Furthermore, the LED chip 70 (C8) to which the lighting signal line 107_8 adjacent to the lighting signal 107_6 is connected belongs to the fourth group Gr4. Furthermore, the LED chip 70 (C10) to which the lighting signal line 107_10 adjacent to the lighting signal line 107_8 is connected belongs to the fifth group Gr5. The LED chip 70 (C12) to which the lighting signal line 107_12 adjacent to the lighting signal line 107_10 is connected belongs to the sixth group Gr6. Further, the LED chip 70 (C14) to which the lighting signal line 107_14 adjacent to the lighting signal line 107_12 is connected belongs to the seventh group Gr7. Furthermore, the LED chip 70 (C16) to which the lighting signal line 107_16 adjacent to the lighting signal line 107_14 is connected belongs to the eighth group Gr8. The LED chip 70 (C18) to which the lighting signal line 107_18 adjacent to the lighting signal line 107_16 is connected again belongs to the first group Gr1. As described above, the even-numbered LED chips 70 are also configured to belong to the first group Gr1 to the eighth group Gr8 sequentially along the main scanning direction.

  In a printed circuit board such as the LED circuit board 62, for example, when two signal lines are arranged close to each other in parallel, a phenomenon called crosstalk in which a signal flowing through one signal line leaks to the other signal line. Is known to occur. When crosstalk occurs, a noise component accompanying the crosstalk is superimposed on the original signal on the other wiring.

  In the present embodiment, as shown in FIG. 16, in the LED circuit board 62, for example, in the first lighting signal line group 107A, odd-numbered lighting signal lines 107_1, 107_3,. For example, in the second lighting signal line group 107B, even-numbered lighting signal lines 107_2, 107_4,..., 107_60 are arranged in parallel. For this reason, in the first lighting signal line group 107A and the second lighting signal line group 107B, the lighting signal lines 107 adjacent to each other (for example, the lighting signal line 107_1 and the lighting signal line 107_3 in the first lighting signal line group 107A). In addition, crosstalk may occur between the lighting signal line 107_2 and the lighting signal line 107_4) in the second lighting signal line group 107B.

  Here, if adjacent lighting signal lines 107 belong to the same group, the following may occur. Here, description will be made assuming that the lighting signal line 107_1 and the lighting signal line 107_3 in the first lighting signal line group 107A belong to the same group. For example, as shown in FIG. 12, the lighting timing of each LED, that is, the rising timing of the lighting signal ΦI (ΦI1 and ΦI3 in this example) is aligned within the same group. At this rising timing, the lighting signal ΦI1 and the lighting signal ΦI3 change rapidly. For this reason, the lighting signal ΦI1 flowing through the lighting signal line 107_1 is affected by crosstalk caused by the lighting signal ΦI3 flowing through the lighting signal line 107_3. Then, the shape of the lighting signal ΦI1 is distorted, and as a result, the LED emits light with a light amount different from the originally intended light amount. On the other hand, the lighting signal ΦI3 flowing through the lighting signal line 107_3 is also affected by the crosstalk caused by the lighting signal ΦI1 flowing through the lighting signal line 107_1, and similarly causes the LED to emit light with a light amount different from the originally planned light amount. Become. That is, uneven exposure due to the LPH 14 occurs due to the influence of crosstalk generated between the lighting signal lines 107.

  On the other hand, in the present embodiment, since the adjacent lighting signal lines 107 are configured to belong to different groups, the rising timings of the lighting signals ΦI in the adjacent lighting signal lines 107 are not matched, and the lighting is performed. It will shift within the range of the period T1. Therefore, it is possible to suppress the fluctuation of the lighting signal ΦI as described above, and it is possible to suppress the occurrence of unevenness in the amount of light due to crosstalk. That is, the LPH 14 can be stably operated.

  In the present embodiment, the grouping as shown in FIG. 15 is performed so that the LED chips 70 connected to the adjacent lighting signal lines 107 belong to different groups. The design may be changed as appropriate.

<Embodiment 3>
The present embodiment is substantially the same as the first and second embodiments, but in the first and second embodiments, the LED chips 70 constituting the SLED 63 are arranged in a so-called zigzag pattern as shown in FIG. On the other hand, in this embodiment, as shown in FIG. 17, 60 LED chips 70 (C1 to C60) are arranged linearly. In the present embodiment, the same components as those in the first and second embodiments are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 18 is a diagram for explaining grouping of the LED chips 70 (C1 to C60) in the present embodiment. FIG. 18 (a) illustrates the state of grouping, and FIG. 18 (b) illustrates the group name, component chip name, and component chip number. In the present embodiment, eight groups Gr1 to Gr8 are configured so that LED chips 70 adjacent in the main scanning direction do not belong to the same group. The first group Gr1 includes eight LED chips 70 of C1, C9, C17, C25, C33, C41, C49, and C57. The second group Gr2 includes eight LED chips 70 of C2, C10, C18, C26, C34, C42, C50, and C58. The third group Gr3 includes eight LED chips 70 of C3, C11, C19, C27, C35, C43, C51, and C59. The fourth group Gr4 includes eight LED chips 70 of C4, C12, C20, C28, C36, C44, C52, and C60. The fifth group Gr5 includes seven LED chips 70 of C5, C13, C21, C29, C37, C45, and C53. The sixth group Gr6 includes seven LED chips 70 of C6, C14, C22, C30, C38, C46, and C54. The seventh group Gr7 includes seven LED chips 70 of C7, C15, C23, C31, C39, C47, and C55. The eighth group Gr8 includes seven LED chips 70 of C8, C16, C24, C32, C40, C48, and C56. Accordingly, each of the first group Gr1 to the fourth group Gr4 has eight LED chips 70 (8Chip). On the other hand, each of the fifth group Gr5 to the eighth group Gr8 has seven LED chips 70 (7Chip).

  FIG. 19 shows an example of a wiring pattern formed on the LED circuit board 62 shown in FIG. In FIG. 19, the description of the LED circuit board 62 is omitted as in the second embodiment. In FIG. 19, C1 to C9 are illustrated among the 60 LED chips 70, and only the wiring pattern is shown for C10 to C60, and the description of the LED chip 70 is omitted. In the present embodiment, unlike the second embodiment, the corresponding lighting signal lines 107 (107_1 to 107_60) are drawn from the lower side in the figure for all the LED chips 70 (C1 to C60). .

  As in the second embodiment, in addition to the lighting signal line 107, the LED circuit board 62 includes the power supply line 105, the ground line 106, the first transfer signal line 108 (108_1 to 108_8), and Second transfer signal lines 109 (109_1 to 109_8) are also formed. However, these descriptions are omitted in FIG.

  As described above, one end of each lighting signal line 107 is connected to the signal generation circuit 100 shown in FIG. 17 and the other end is connected to the corresponding LED chip 70. Further, as shown in FIG. 17, the LED chip 70 (C1) on one end side in the main scanning direction is closest to the signal generating circuit 100, and the LED chip 70 (C60) on the other end side in the main scanning direction is a signal. They are respectively arranged on the side farthest from the generation circuit 100.

  Each of the lighting signal lines 107_1 to 107_60 is wired substantially parallel to the arrangement direction of the LED chips 70. Further, the lighting signal line 107_1 for supplying the lighting signal ΦI1 to the LED chip 70 (C1) is wired on the side farthest from the LED chip 70, the lighting signal line 107_60 for supplying the lighting signal ΦI60 to the LED chip 70 (C60), respectively. Has been. Next to the lighting signal line 107_1 for supplying the lighting signal ΦI1 to the LED chip 70 (C1), a lighting signal line 107_2 for supplying the lighting signal ΦI2 to the LED chip 70 (C2) adjacent in the main scanning direction is provided. . A lighting signal line 107_3 for supplying a lighting signal ΦI3 to the LED chip 70 (C3) adjacent in the main scanning direction is provided next to the lighting signal line 107_2 for supplying the lighting signal ΦI2 to the LED chip 70 (C2). ing. Further, a lighting signal line 107_4 for supplying the lighting signal ΦI4 to the LED chip 70 (C4) adjacent in the main scanning direction is provided next to the lighting signal line 107_3 for supplying the lighting signal ΦI3 to the LED chip 70 (C3). ing. Further, a lighting signal line 107_5 for supplying the lighting signal ΦI5 to the LED chip 70 (C5) adjacent in the main scanning direction is provided next to the lighting signal line 107_4 for supplying the lighting signal ΦI4 to the LED chip 70 (C4). It has been. Further, a lighting signal line 107_6 for supplying the lighting signal ΦI6 to the LED chip 70 (C6) adjacent in the main scanning direction is provided next to the lighting signal line 107_5 for supplying the lighting signal ΦI5 to the LED chip 70 (C5). ing. Further, a lighting signal line 107_7 for supplying the lighting signal ΦI7 to the LED chip 70 (C7) adjacent in the main scanning direction is provided next to the lighting signal line 107_6 for supplying the lighting signal ΦI6 to the LED chip 70 (C6). ing. Further, a lighting signal line 107_8 for supplying the lighting signal ΦI8 to the LED chip 70 (C8) adjacent in the main scanning direction is provided next to the lighting signal line 107_7 for supplying the lighting signal ΦI7 to the LED chip 70 (C7). It has been. Next to the lighting signal line 107_8 for supplying the lighting signal ΦI8 to the LED chip 70 (C8), a lighting signal line 107_9 for supplying the lighting signal ΦI9 to the LED chip 70 (C9) adjacent in the main scanning direction is provided. ing. That is, in this embodiment, the lighting signal lines 107_1, 107_2, 107_3,..., 107_60 are sequentially wired in order from the side closer to the LED chip 70.

Here, in the present embodiment, grouping as shown in FIG. 18 is performed for each LED chip 70.
For this reason, as shown also in FIG. 19, the lighting signal lines 107 adjacent to each other always supply the lighting signal ΦI to the LED chips 70 belonging to another group as in the second embodiment. For example, the LED chip 70 (C1) to which the lighting signal line 107_1 is connected belongs to the first group Gr1. On the other hand, the LED chip 70 (C2) to which the lighting signal line 107_2 adjacent to the lighting signal line 107_1 is connected belongs to the second group Gr2. The LED chip 70 (C3) to which the lighting signal line 107_3 adjacent to the lighting signal line 107_2 is connected belongs to the third group Gr3. Furthermore, the LED chip 70 (C4) to which the lighting signal line 107_4 adjacent to the lighting signal line 107_3 is connected belongs to the fourth group Gr4. Furthermore, the LED chip 70 (C5) to which the lighting signal line 107_5 adjacent to the lighting signal line 107_4 is connected belongs to the fifth group Gr5. The LED chip 70 (C6) to which the lighting signal line 107_6 adjacent to the lighting signal line 107_5 is connected belongs to the sixth group Gr6. Further, the LED chip 70 (C7) to which the lighting signal line 107_7 adjacent to the lighting signal line 107_6 is connected belongs to the seventh group Gr7. Furthermore, the LED chip 70 (C8) to which the lighting signal line 107_8 adjacent to the lighting signal line 107_7 is connected belongs to the eighth group Gr8. The LED chip 70 (C9) to which the lighting signal line 107_9 adjacent to the lighting signal line 107_8 is connected belongs to the first group Gr1 again. In this way, each LED chip 70 is configured to belong to the first group Gr1 to the eighth group Gr8 sequentially along the main scanning direction.

  Also in the present embodiment, as in the second embodiment, the adjacent lighting signal lines 107 are configured to belong to different groups. For this reason, the rising timings of the lighting signals ΦI in the adjacent lighting signal lines 107 do not coincide with each other, and shift within the lighting period T1. Therefore, as in the second embodiment, it is possible to suppress the occurrence of unevenness in the amount of light due to crosstalk. That is, the LPH 14 can be stably operated.

  In the present embodiment, the grouping as shown in FIG. 18 is performed so that the LED chips 70 connected to the adjacent lighting signal lines 107 belong to different groups. The design may be changed as appropriate.

1 is a diagram illustrating an overall configuration of an image forming apparatus equipped with an LED print head (LPH) to which the exemplary embodiment is applied. It is the figure which showed the structure of LPH. It is a top view of a LED circuit board. It is a figure explaining the connection part of a LED chip. It is the figure which showed the wiring diagram formed on a LED circuit board. (A) (b) is a figure for demonstrating grouping of an LED chip. It is a circuit diagram for demonstrating the structure of a LED chip, a signal generation circuit, and a level shift circuit. It is a figure which shows the structure of a signal generation circuit. It is a figure which shows the structure of a lighting signal generation part. It is a timing chart for demonstrating operation | movement of the transfer start signal generation part. 3 is a timing chart for explaining drive signals output from a signal generation circuit and a level shift circuit. It is a timing chart for demonstrating the lighting timing of each LED of a 1st group, a 2nd group, and a 3rd group at the time of performing the lighting control which concerns on this Embodiment. It is a timing chart for demonstrating the lighting timing of each LED of a 1st group, a 2nd group, and a 3rd group in the case of performing the conventional lighting control. It is a timing chart for demonstrating the other example of the lighting timing shift of each LED in a 1st group, a 2nd group, and a 3rd group at the time of performing the lighting control which concerns on this Embodiment. (A) (b) is a figure for demonstrating grouping of the LED chip in Embodiment 2. FIG. 6 is a diagram showing an example of a wiring pattern on an LED circuit board in Embodiment 2. FIG. 6 is a plan view of an LED circuit board according to Embodiment 3. FIG. (A) and (b) are the figures for demonstrating grouping of the LED chip in Embodiment 3. FIG. 6 is a diagram showing an example of a wiring pattern on an LED circuit board in Embodiment 3. FIG.

Explanation of symbols

11Y, 11M, 11C, 11K ... Image forming unit, 12 ... Photoconductor drum, 13 ... Charger, 14 ... LED print head (LPH), 30 ... Control unit, 40 ... Image processing unit (IPS), 63 ... Self-scanning LED (SLED), 70 (C1 to C60) ... LED chip, 100 ... signal generation circuit, 104 ... level shift circuit, 110 ... exposure control unit, 111 ... transfer start signal generation unit, 112 ... video data sorting unit, 120 DESCRIPTION OF SYMBOLS ... Block drive part 121 ... Transfer signal generation part 122 ... Lighting signal generation part 123 ... Image data rearrangement part 124 ... Lighting pulse calculation part 125 ... Pulse generator, CK1, CK2 ... Transfer signal, ΦI ... Lighting Signal, T1 ... lighting cycle, T2 ... 1 line transfer period, t ... delay time

Claims (11)

A lighting section in which a plurality of lighting chips each having a plurality of lighting elements are arranged;
A drive unit configured to sequentially turn on the plurality of lighting elements in the plurality of lighting chips,
The drive unit is configured to shift a lighting timing between the plurality of lighting chips within a lighting cycle of one lighting element.   2. The print head according to claim 1, wherein the driving unit shifts the lighting timing between the plurality of lighting chips within a range of an integral multiple of the lighting cycle + less than the lighting cycle.   The print head according to claim 1, wherein the driving unit shifts the lighting timing for each of a plurality of groups configured by a plurality of the lighting chips. A lighting head in which a plurality of lighting chips each including a plurality of lighting elements and a plurality of switch elements provided corresponding to the lighting elements are arranged;
A transfer signal generator for generating a transfer signal for sequentially turning on the plurality of switch elements in the lighting chip, and enabling a plurality of the lighting elements in the lighting chip to be sequentially turned on;
A transfer start signal generation unit that outputs a transfer start signal instructing the transfer signal generation unit to start generation of the transfer signal;
The transfer start signal generation unit outputs the transfer start signal to a plurality of groups configured by a plurality of the lighting chips while shifting the timing within a range less than the lighting cycle of the one lighting element. Print head characterized by   5. The transfer start signal generation unit outputs the transfer start signal to a plurality of the groups while shifting the timing within a range that is an integral multiple of the lighting cycle + less than the lighting cycle. Print head.   The print head according to claim 4, further comprising a lighting signal generator that generates lighting signals for the plurality of lighting elements in the plurality of lighting chips in accordance with input image data. A plurality of wires for supplying the lighting signal from the lighting signal generator to each of the plurality of lighting chips;
The print head according to claim 6, wherein the two lighting chips to which the lighting signal is supplied from the adjacent wiring belong to different groups. A substrate on which the lighting signal generator and the plurality of lighting chips are mounted;
A plurality of wirings provided on the substrate and supplying the lighting signal from the lighting signal generation unit to each of the plurality of lighting chips;
The plurality of wirings are provided side by side,
The print head according to claim 6, wherein the two lighting chips to which the lighting signal is supplied from the adjacent wiring belong to different groups.   9. The print head according to claim 7, wherein the two lighting chips adjacent in the main scanning direction belong to different groups.   The print head according to claim 4, wherein the plurality of groups include approximately the same number of the lighting chips. The plurality of lighting chips constituting the lighting head are arranged in a staggered manner,
5. The print head according to claim 4, wherein each of the plurality of groups includes only the lighting chip disposed upstream in the sub-scanning direction or the lighting chip disposed downstream in the sub-scanning direction. .

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