JP2007098772A - Driver and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress occurrence of an image shift due to difference in recording length by a print head in the main scanning direction through a simple arrangement. <P>SOLUTION: An internal clock generating section 111 generates an internal clock CLK2 by using frequency division ratio information stored in a register 112. A D-type flip-flop circuit (D-FF) 113 latches inputted image data with the internal clock CLK2 generated from the internal clock generating section 111 and outputs them as latch data. When the period of the internal clock CLK2 is set longer than the period for transferring individual image data, the latch data are compressed by thinning the image data. When the period of the internal clock CLK2 is set longer than the period for transferring individual image data, the latch data are decompressed by complementing the image data. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a driver used in a print head of an image forming apparatus.

  In an image forming apparatus adopting an electrophotographic system, an electrostatic latent image is obtained by irradiating image information onto a uniformly charged photoreceptor by an optical recording means. The electrostatic latent image formed on the photoreceptor is visualized by adding toner, and the image is formed by transferring and fixing on the recording paper. As such a recording means, an optical scanning method in which exposure is performed by scanning a laser beam in a main scanning direction using a laser has been widely used. In recent years, there has been a recording unit using an LED print head (LPH) in which a large number of LEDs (Light Emitting Diodes) are arranged in the main scanning direction in response to a request for downsizing of the apparatus. Has been adopted.

  The LPH generally has an LED array in which a plurality of LED chips in which a large number of LEDs are arranged in a line are arranged, and a large number of rods for imaging light output from the LEDs on the surface of the photosensitive member (photosensitive drum). And a rod lens array in which lenses are arranged. In the image forming apparatus, each LED of LPH is driven based on input image data, light is output toward the photoconductor, and light is imaged on the surface of the photoconductor by the rod lens array. Then, an electrostatic latent image is formed in the sub-scanning direction by relatively moving the photoconductor and LPH.

  In recent image forming apparatuses, colorization is progressing rapidly. For example, a so-called tandem type image forming apparatus that forms a full-color image by arranging four image forming units of yellow (Y), magenta (M), cyan (C), and black (K) in parallel is put into practical use. Has been. When LPH is applied to this type of image forming apparatus, each image forming unit is provided with LPH (see Patent Document 1).

JP-A-7-52468 (page 3, FIG. 7)

  By the way, since the LPH has the above-described configuration, a predetermined dimensional error (mounting error) is allowed for each LED or each LED chip on the LED chip. For this reason, in the tandem type image forming apparatus, the length of the LED array in the main scanning direction may be different in each image forming unit (each LPH). If the length of the LED array in the main scanning direction differs for each LPH, the formation position of the electrostatic latent image that should be superimposed is shifted for each color, and the resulting full color image is shifted in image (in the main scanning direction). (Registration misalignment) occurs.

  Therefore, in Patent Document 1 described above, the amount of shift in the main scanning direction of each LPH is detected by forming an image using each image forming unit (each LPH). For example, black LPH is used as a reference and changed to another LPH. By providing a doubling means, correction is performed to match the lengths in the main scanning direction of the LPHs. This correction is performed by complementing the pixels in the LPH whose main scanning direction length is shorter than that of the black LPH, and by thinning out the pixels in the LPH having a longer main scanning direction length of the LED array than the black LPH. .

  However, in the above-mentioned Patent Document 1, a circuit configuration for determining which pixel to complement or thin out when performing such correction is very complicated. Further, as the circuit configuration becomes complicated, there is a problem that the cost for manufacturing LPH increases.

  Further, in the conventional LPH, if the resolution of the input image data does not match the resolution that can be output by the LPH, there is a problem that the formed electrostatic latent image expands and contracts in the main scanning direction. . Specifically, for example, when the resolution on the LPH side is equivalent to 1200 dpi and the image data is equivalent to 600 dpi, the latent image is formed using only one half of the LED array. As a result, a toner image shrunk in half in the main scanning direction is formed.

  These problems are not limited to the LPH described above, but in a print head configured by arranging a plurality of recording elements, a ROS (Raster Output Scanner) that performs exposure by scanning a laser beam, an inkjet head, or the like. Can occur as well.

The present invention has been made to solve such a technical problem, and an object of the present invention is to provide an image shift caused by a difference in length in the main scanning direction recorded by a print head with a simple configuration. It is to suppress the occurrence of.
Another object is to perform resolution conversion of image data with a simple configuration.

  For this purpose, the present invention is a driver used in a print head for writing an image, wherein a clock is generated by a clock generating means, and input image data is supplied from the clock generating means. The latch means latches and outputs as latch data, and the latch data output from the latch means is converted into a format corresponding to the print head by the output means and output to the print head. The clock period is adjusted according to the image writing width of the print head.

  In such a driver, the clock generation means is composed of a PLL (Phase Locked Loop) frequency synthesizer that multiplies an external clock input from an externally provided oscillator and generates a clock, and the latch means includes image data. Is a D-type flip-flop circuit having D as an input and a clock as a clock input. Further, the clock cycle generated by the clock generation unit may be asynchronous with the cycle in which image data corresponding to one pixel is input to the latch unit. Furthermore, the clock cycle generated by the clock generation unit may be an integral multiple or a fraction of an integer with respect to a cycle in which image data corresponding to one pixel is input to the latch unit.

  From another viewpoint, the present invention relates to an image carrier, a charger for charging the image carrier, an exposure device for exposing the charged image carrier to form an electrostatic latent image, an image In an image forming apparatus comprising an image forming unit having a developing unit that develops an electrostatic latent image formed on a carrier with toner and a transfer unit that transfers a toner image formed on the image carrier to a recording material. The exposure unit is configured to latch a light emitting unit that exposes the image carrier by emitting light, a clock generation unit that generates a clock, and input image data based on a clock supplied from the clock generation unit. A latch unit that outputs data, and an output unit that converts the latch data output from the latch unit into a format corresponding to the light emitting unit and outputs the data to the light emitting unit, and the clock generating unit is formed by the light emitting unit The main of electrostatic latent image It is characterized by adjusting the period of the clock according to 査 direction length.

  In such an image forming apparatus, a plurality of image forming units are provided, and a clock generation period in the clock generation unit is different for each image forming unit. Further, the light emitting section may be characterized by comprising a light emitting element array configured by arranging a plurality of light emitting elements in the main scanning direction. Further, the image forming unit includes a plurality of image forming units, and further includes a register for storing clock generation period information in the clock generating unit, and the register includes a length in the main scanning direction of the exposure unit in a specific image forming unit of the plurality of image forming units The clock generation period information set on the basis of the length is stored. In this case, the plurality of image forming units include a black image forming unit that forms a black toner image, and an other color image forming unit that forms a toner image of a color other than black, and the specific image forming unit includes: It can be characterized by being a black image forming unit.

  According to the present invention, since the image data is latched and fetched with the clock adjusted appropriately, the image misalignment caused by the difference in the main scanning direction length recorded by the print head can be generated with a simple configuration. Can be suppressed.

The best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described below in detail with reference to the accompanying drawings.
<Embodiment 1>
FIG. 1 is a diagram illustrating an overall configuration of an image forming apparatus using a print head including a driver to which the present embodiment is applied. The image forming apparatus shown in FIG. 1 is a so-called tandem type digital color printer 1. The image forming apparatus includes an image forming process unit 10, a control unit 30, and an image processing unit (IPS: Image Processing System) 40. Among these, the image forming process unit 10 forms an image corresponding to the image data of each color. The control unit 30 controls the operation of the image forming process unit 10. Further, the IPS 40 is connected to, for example, a personal computer (PC) 2 or an image reading device (IIT) 3 and performs predetermined image processing on image data received from these.

The image forming process unit 10 includes four image forming units (a plurality of image forming units) 11Y, 11M, 11C, and 11K that are arranged in parallel at a predetermined interval. The image forming units 11Y, 11M, 11C, and 11K include a photosensitive drum 12, a charger 13, an LED print head (LPH) 14, a developing device 15, and a cleaner 16. Here, the photosensitive drum 12 as an image carrier forms an electrostatic latent image and carries a toner image. The charger 13 uniformly charges the surface of the photosensitive drum 12 with a predetermined potential. The LPH 14 as an exposure device exposes the photosensitive drum 12 charged by the charger 13. The developing device 15 develops the electrostatic latent image obtained by the LPH 14. The cleaner 16 cleans the surface of the photosensitive drum 12 after transfer. Here, the image forming units 11Y, 11M, 11C, and 11K are configured in substantially the same manner except for the toner stored in the developing unit 15. The image forming units 11Y, 11M, 11C, and 11K respectively form yellow (Y), magenta (M), cyan (C), and black (K) toner images.
Further, the image forming process unit 10 includes an intermediate transfer belt 21, a primary transfer roll 22, a secondary transfer roll 23, and a fixing device 25. A toner image of each color formed on the photosensitive drum 12 of each of the image forming units 11Y, 11M, 11C, and 11K is transferred onto the intermediate transfer belt 21 as a recording material. The primary transfer roll 22 as a transfer device sequentially transfers (primary transfer) the color toner images of the image forming units 11Y, 11M, 11C, and 11K to the intermediate transfer belt 21. The secondary transfer roll 23 collectively transfers (secondary transfer) the superimposed toner image transferred onto the intermediate transfer belt 21 onto the paper P as a recording material. The fixing device 25 fixes the secondary transferred image on the paper P.

  Now, an image forming operation in the digital color printer 1 will be described. In the digital color printer 1, the image forming process unit 10 performs an image forming operation based on a control signal such as a synchronization signal supplied from the control unit 30. At that time, the image data input from the PC 2 or IIT 3 is subjected to image processing by the image processing unit 40 and supplied to each of the image forming units 11Y, 11M, 11C, and 11K via the interface. In the yellow image forming unit 11Y, for example, the surface of the photosensitive drum 12 uniformly charged at a predetermined potential by the charger 13 is exposed by the LPH 14 that emits light based on the image data obtained from the image processing unit 40. Thus, an electrostatic latent image is formed on the photosensitive drum 12. The formed electrostatic latent image is developed by the developing device 15, and a yellow toner image is formed on the photosensitive drum 12. Similarly, magenta, cyan, and black toner images are formed in the other image forming units 11M, 11C, and 11K.

The color toner images formed by the image forming units 11Y, 11M, 11C, and 11K are sequentially electrostatically attracted by the primary transfer roll 22 onto the intermediate transfer belt 21 that rotates in the direction of arrow A in FIG. As a result, a superimposed toner image is formed on the intermediate transfer belt 21. The formed superimposed toner image is conveyed to an area (secondary transfer portion) where the secondary transfer roll 23 is disposed as the intermediate transfer belt 21 moves. When the superimposed toner image is conveyed to the secondary transfer unit, the paper P is supplied to the secondary transfer unit in accordance with the timing at which the toner image is conveyed to the secondary transfer unit. Then, the superimposed toner images are collectively electrostatically transferred onto the conveyed paper P by the transfer electric field formed by the secondary transfer roll 23 in the secondary transfer portion.
Thereafter, the sheet P on which the superimposed toner image has been electrostatically transferred is peeled off from the intermediate transfer belt 21 and conveyed to the fixing device 25 by the conveying belt 24. The unfixed toner image on the paper P conveyed to the fixing device 25 is fixed on the paper P by being subjected to a fixing process by heat and pressure by the fixing device 25. Then, the paper P on which the fixed image is formed is conveyed to a paper discharge mounting portion (not shown) provided in the discharge portion of the image forming apparatus.

Next, the LPH 14 used in this image forming apparatus will be described in detail.
FIG. 2 is a diagram showing the configuration of an LED print head (LPH) 14 that is a print head. The LPH 14 includes a housing 61, an LED circuit board 62, a self-scanning light emitting device (SLED) 63, a rod lens array 64, a holder 65, and a leaf spring 66. Among these, the housing 61 functions as a support for the LPH 14. The LED circuit board 62 is mounted with an SLED 63, a drive circuit for driving the SLED 63, and the like. Further, the SLED 63 has a function of exposing the photosensitive drum 12 by emitting light. The rod lens array 64 has a function of imaging light from the SLED 63 on the surface of the photosensitive drum 12. Furthermore, the holder 65 supports the rod lens array 64 and shields the SLED 63 from the outside. The leaf spring 66 biases the housing 61 toward the rod lens array 64.

The housing 61 is formed of a block or sheet metal such as aluminum or SUS, and supports the LED circuit board 62. The holder 65 supports the housing 61 and the rod lens array 64, and is set so that the light emitting point of the SLED 63 and the focal point of the rod lens array 64 coincide. Furthermore, the holder 65 is configured to seal the SLED 63. Therefore, it is possible to prevent dust from adhering to the SLED 63 from the outside. On the other hand, the leaf spring 66 urges the LED circuit board 62 toward the rod lens array 64 via the housing 61 so as to maintain the positional relationship between the SLED 63 and the rod lens array 64.
The LPH 14 configured in this way is configured to be movable in the optical axis direction of the rod lens array 64 by an adjusting screw (not shown), and the imaging position (focal plane) of the rod lens array 64 is the surface of the photosensitive drum 12. It is adjusted so that it is located above.

  FIG. 3 is a plan view of the LED circuit board 62 shown in FIG. On the LED circuit board 62, SLEDs 63 including, for example, 58 SLED chips (Chip 1 to Chip 58) as light emitting units are arranged in a line with high accuracy so as to be parallel to the axial direction of the photosensitive drum 12. Here, FIG. 4 is an enlarged view of the connecting portion of each LED chip. As shown in FIG. 4, at the end of each SLED chip (Chip 1 to Chip 58), the end boundary of the LED array is arranged continuously in the main scanning direction. That is, the LED chips (Chip 1 to Chip 58) are arranged in a staggered manner. In addition, in FIG. 4, the connection part of Chip1, Chip2, and Chip3 is shown as an example.

  And in LPH14 which concerns on this Embodiment, 256 LED is each mounted in each SLED chip (Chip1-Chip58). Therefore, in the entire SLED 63 having 58 SLED chips, 14848 LEDs are provided. Further, the distance from the outer end portion of the SLED chip Chip1 to the outer end portion of the SLED chip Chip 58 (length in the main scanning direction of the LED array) is set to about 300 mm in order to correspond to A3SEF. For this reason, the interval between adjacent LEDs is set to about 21 μm, and the output resolution of the LPH 14 is about 1200 dpi (dot per inch).

  Further, as shown in FIG. 3, the LED circuit board 62 includes a signal generation circuit 100, a power supply circuit 101, an EEPROM 102, and a harness 103. Among these, the signal generation circuit 100 generates a drive signal for the SLED 63 and the like. The power supply circuit 101 functions as a power supply for the signal generation circuit 100 and the SLED 63. The EEPROM 102 stores light amount correction value data and the like in the SLED 63. The harness 103 exchanges power and signals with the digital color printer 1 main body.

FIG. 5 is a diagram showing the configuration of the signal generation circuit 100 as a driver and the wiring configuration of the LED circuit board 62.
As shown in FIG. 5, the signal generation circuit 100 includes a lighting signal generation unit 110 that outputs a lighting signal ΦI (ΦI1 to ΦI58) to each LED chip (Chip1 to Chip58). Further, the signal generation circuit 100 divides each LED chip (Chip1 to Chip58) into six sets, and outputs a transfer signal CK1 (CK1_1 to CK1_6) and a transfer signal CK2 (CK2_1 to CK2_6) to each set. A generator 130 is provided.

On the LED circuit board 62, a power supply line 105 for supplying a power supply voltage Vcc from the power supply circuit 101 (see FIG. 3) to each SLED chip (Chip1 to Chip58) and a grounded (GND) power supply line 106 are provided. It has been. On the LED circuit board 62, signal lines 107 (107_1 to 107_58) for transmitting the lighting signals ΦI (ΦI1 to ΦI58) from the signal generation circuit 100 to the respective SLED chips are wired. In addition, signal lines 108 (108_1 to 108_6) for transmitting the transfer signal CK1 (CK1_1 to 1_6) are also wired. Further, signal lines 109 (109_1 to 109_6) for transmitting the transfer signal CK2 (CK2_1 to 2_6) are also wired.
The lighting signals ΦI (ΦI1 to ΦI58) for the Chip1 to Chip58 are input to the SLED chips (Chip1 to Chip58) via the signal line 107. Further, the transfer signal CK1 (CK1_1 to 1_6) is input to the Chip1 to Chip58 via the signal line 108 and the transfer signal CK2 (CK2_1 to 2_6) is input to the Chipline 58 via the signal line 108, respectively.

Next, the circuit configuration of the SLED 63 will be described with reference to FIG. The SLED 63 of this embodiment is connected to the signal generation circuit 100 via the level shift circuit 104. The level shift circuit 104 has a configuration in which a resistor R1B and a capacitor C1, and a resistor R2B and a capacitor C2 are arranged in parallel, one end of which is connected to the input terminal of the SLED 63, and the other end of the signal generating circuit 100 ( It is connected to the output terminal of the transfer signal generator 130). Based on the transfer signals CK1R and CK1C and the transfer signals CK2R and CK2C output from the transfer signal generator 130, the transfer signal CK1 and the transfer signal CK2 are output to the SLED 63.
In the SLED 63 of the present embodiment, 58 SLED chips (Chip 1 to Chip 58) are arranged, but FIG. 6 shows only one SLED chip. In the following description, the SLED chip is referred to as SLED 63 for convenience.

As shown in FIG. 6, the SLED 63 includes 128 thyristors S1 to S128, 128 LEDs L1 to L128, and 128 diodes D1 to D128 as switching elements. Further, the SLED 63 has 128 resistors R1 to R128, and transfer current limiting resistors R1A and R2A for preventing excessive current from flowing through a third internal wiring 183 and a fourth internal wiring 184, which will be described later. ing.
Here, a part mainly composed of thyristors S1 to S128 and diodes D1 to D128 for controlling supply of current to the LEDs L1 to L128 is referred to as a transfer unit.

In the SLED 63 of the present embodiment, the anode terminals A1 to A128 of the thyristors S1 to S128 are connected to the first internal wiring 181. The anode terminals a1 to a128 of each LED L1 to L128 are connected to a second internal wiring 182 as a power supply line branched from the first internal wiring 181. The first internal wiring 181 and the second internal wiring 182 are connected to the power supply line 105 through input terminals. As a result, the power supply voltage Vcc is supplied from the power supply circuit 101 to the first internal wiring 181 and the second internal wiring 182.
A third internal wiring 183 is connected to the cathode terminals K1, K3,..., K127 of the odd-numbered thyristors S1, S3,. The third internal wiring 183 is connected to the signal line 108 through an input terminal. As a result, the transfer signal CK1 is transmitted from the signal generation circuit 100 to the third internal wiring 183 via the level shift circuit 104 and the transfer current limiting resistor R1A.
Further, the fourth internal wiring 184 is connected to the cathode terminals K2, K4,..., K128 of the even-numbered thyristors S2, S4,. The fourth internal wiring 184 is connected to the signal line 109 via the input terminal. As a result, the transfer signal CK2 is transmitted from the signal generation circuit 100 (transfer signal generation unit 130) to the fourth internal wiring 184 via the level shift circuit 104 and the transfer current limiting resistor R2A.

On the other hand, the gate terminals G1 to G128 of the thyristors S1 to S128 are respectively connected to the fifth internal wiring 185 via resistors R1 to R128 provided corresponding to the thyristors S1 to S128. The fifth internal wiring 185 is connected to the power supply line 106 via an input terminal, and the power supply line 106 is grounded (GND) as described above.
The gate terminals G1 to G128 of the thyristors S1 to S128 and the gate terminals g1 to g128 of the LEDs L1 to L128 provided corresponding to the thyristors S1 to S128 are connected to each other.
Furthermore, the cathode terminals of the diodes D1 to D128 are connected to the gate terminals G1 to G128 of the thyristors S1 to S128. The gate terminals G1 to G127 of the thyristors S1 to S127 are connected to the anode terminals of the next-stage diodes D2 to D128, respectively. That is, the diodes D2 to D128 are connected in series with the gate terminals G1 to G127 interposed therebetween. The anode terminal of the diode D1 is connected to the fourth internal wiring 184, and as a result, the transfer signal CK2 is transmitted.

  Further, the cathode terminals k1 to k128 of the LEDs L1 to L128 are connected to a sixth internal wiring 186. A sixth internal wiring 186 as a signal line is connected to the signal line 107 via an input terminal, and a lighting signal ΦI is transmitted from the signal generation circuit 100 (lighting signal generation unit 110). The signal line 107 is provided with a drive current setting resistor RID for setting the magnitude of the current (drive current) flowing through the sixth internal wiring 186.

  Further, the light shielding mask 50 is disposed in the SLED 63 so as to cover the thyristors S1 to S128 and the diodes D1 to D128 in the transfer unit. This is because during the image forming operation, light emission from the thyristors S1 to S128 in the on state and current is flowing, and from the diodes D1 to D128 in the current flow state is blocked, and unnecessary light is removed from the photoconductor. This is for suppressing exposure of the drum 12.

Next, driving of the LPH 14 in the image forming operation (lighting operation of each LED) will be described with reference to a timing chart shown in FIG. Note that the timing chart shown in FIG. 7 shows a case where all LEDs perform optical writing (light emission).
(1) First, when a reset signal (RST) is input from the image forming apparatus to the signal generation circuit 100, the signal generation circuit 100 transfers the transfer signal CK1C to a high level (hereinafter referred to as “H”) and transfer. By setting the signal CK1R to “H”, the transfer signal CK1 is set to “H”. Further, the transfer signal CK2C is set to a low level (hereinafter referred to as “L”), and the transfer signal CK2R is set to “L”, whereby the transfer signal CK2 is set to a low level (“L”). As a result, all the thyristors S1 to S128 are set to an off state (FIG. 7A).
(2) Following the reset signal (RST), the line synchronization signal Lsync output from the signal generation circuit 100 becomes “H” (FIG. 7A), and the operation of the SLED 63 is started. Then, in synchronization with the line synchronization signal Lsync, the transfer signal CK2 is changed to “H” by setting the transfer signal CK2C and the transfer signal CK2R to “H” as shown in FIGS. “H” is set (FIG. 7B).

(3) Next, as shown in FIG. 7C, the transfer signal CK1R is set to “L” (FIG. 7C).
(4) Subsequently, as shown in FIG. 7B, the transfer signal CK1C is set to “L” (FIG. 7D).
In this state, a gate current starts to flow through the gate terminal G1 of the thyristor S1. At that time, the tri-state buffer B1R of the signal generation circuit 100 is set to high impedance (Hiz), thereby preventing current backflow.
Thereafter, the thyristor S1 starts to be turned on by the gate current of the thyristor S1, and the gate current gradually increases. At the same time, when a current flows into the capacitor C1 of the level shift circuit 104, the potential of the transfer signal CK1 also gradually increases.

(5) After the elapse of a predetermined time (the time when the transfer signal CK1 potential becomes close to GND), the tristate buffer B1R of the signal generation circuit 100 is set to “L” (FIG. 7E). Then, as the gate potential rises, the signal line Φ1 potential rises and the transfer signal CK1 potential rises, and accordingly, current starts to flow to the resistor R1B side of the level shift circuit 104. On the other hand, the current flowing into the capacitor C1 of the level shift circuit 104 gradually decreases as the potential of the transfer signal CK1 increases.
When the thyristor S1 is completely turned on and becomes a steady state, a current for maintaining the on state of the thyristor S1 flows to the resistor R1B of the level shift circuit 104, but does not flow to the capacitor C1.
At this time, as shown in FIG. 7B, the tri-state buffer B1C of the signal generation circuit 100 is set to high impedance (Hiz) (FIG. 7E).

  (6) With the thyristor S1 completely turned on, the lighting signal ΦI is set to “L” as shown in FIG. 7 (H) (FIG. 7 (f)). At this time, since the potential of the gate G1> the potential of the gate G2, the LED L1 having a thyristor structure is turned on earlier and lights up. As the LED L1 is turned on, the potential of the signal line Φ1 rises, so that the LEDs after the LED L2 are not turned on. That is, as for the LEDs L1, L2, L3, L4,..., Only the LED L1 having the highest gate voltage is turned on (lit).

(7) Next, as shown in FIG. 7 (F), when the transfer signal CK2R is set to “L” (FIG. 7 (g)), a current flows in the same manner as in FIG. A voltage is generated across the capacitor C2 104.
(8) As shown in FIG. 7E, when the transfer signal CK2C is set to “L” in this state (FIG. 7H), the thyristor switch S2 is turned on.
(9) Then, as shown in FIGS. 7B and 7C, when the transfer signals CK1C and CK1R are simultaneously set to “H” (FIG. 7 (i)), the thyristor switch S1 is turned off and passes through the resistor R1. As a result, the potential of the gate G1 gradually decreases. At that time, the thyristor switch S2 is completely turned on. Therefore, the LED L2 can be turned on / off by setting the lighting signal ΦI corresponding to the image data from the lighting signal terminal to “L” / “H”. In this case, since the potential of the gate G1 is already lower than the potential of the gate G2, the LED L1 is not turned on.

  (10) After the above-described operation is sequentially performed, the LEDs L1 to L128 are sequentially turned on, and after the “transfer operation period” in FIG. 7 in which the terminal LED L128 is extinguished, the transfer signals CK1C and CK1R are set to “H”. The transfer signal CK1 is set to “H”, the transfer signals CK2C and CK2R are set to “H”, the transfer signal CK2 is set to “H”, and both the transfer signal CK1 and the transfer signal CK2 are kept in the “H” state for a predetermined time ( FIG. 7 “Transfer Thyristor Off”). As a result, all thyristors S1 to S128 are turned off. Therefore, in this state, no current flows through all the thyristors S1 to S128, so that the thyristors S1 to S128 are held off (not lit).

(11) Further, after the transfer signals CK1 and CK2 are both kept at the “H” state for a predetermined time, the transfer signals CK2C and CK2R are set to “L” and the transfer signal CK2 is set to “L” (see “transfer” in FIG. 7). "Period during which no current flows through the part"). Thereby, since no current flows through the diodes D1 to D128, all the diodes D1 to D128 are also kept in the non-lighted state.
Accordingly, after the lighting signal ΦI is output and the image formation is completed, during the unsteady operation including the state where the photosensitive drum 12 (see FIG. 1) stops rotating, the transfer unit of the SLED 63 is operated. No current is applied. For this reason, in a state where the photoconductor 12 is stopped from rotating, current does not flow through the thyristors S1 to S128 and the diodes D1 to D128 arranged in the transfer unit together with the LEDs L1 to L128, and the thyristors S1 to S128 and Since no light is emitted from the diodes D1 to D128, unnecessary exposure of the photosensitive drum 12 is suppressed.

  By the way, as shown in FIG. 1, in the tandem type digital color printer, the LPH 14 is mounted on each of the four image forming units 11Y, 11M, 11C, and 11K. A predetermined error is allowed in the mounting accuracy of the SLED chips (Chip 1 to Chip 58) in each LPH 14 and the mounting accuracy of the LEDs in each SLED chip (Chip 1 to Chip 58). For this reason, a difference may occur in the length in the main scanning direction of the LED array (comprising 14848 LEDs) for each LPH 14.

  Here, FIG. 8 illustrates misalignment in the main scanning direction when four LPHs 14 (specifically, yellow LPH 14Y, magenta LPH 14M, cyan LPH 14C, and black LPH 14K) are mounted on the image forming apparatus. It is a figure for doing. In this example, the positions of the first dot LEDs in the LPHs 14Y, 14M, 14C, and 14K in the main scanning direction are matched. In this description, the distance from the first LED to the 14848th LED in the black LPH 14K is referred to as a black main scanning direction distance Lk. Further, yellow, magenta, and cyan are also referred to as a yellow main scanning direction distance Ly, a magenta main scanning direction distance Lm, and a cyan main scanning direction distance Lc, respectively. In this example, the cyan main scanning direction distance Lc is shorter than the black main scanning direction distance Lk by two LEDs (for two dots). Further, the magenta main scanning direction distance Lm is longer than the black main scanning direction distance Lk by two dots. Further, the yellow main scanning direction distance Ly is the same as the black main scanning direction distance Lk. In this way, when the main scanning direction distance of the LED array is different for each LPH 14, the formation position of the electrostatic latent image that should be superimposed is shifted for each color. As a result, an image shift (registration shift in the main scanning direction) occurs in the formed full-color image, and the image quality is deteriorated. In the case of this image forming apparatus, an error of ± 0.1% (± 0.3 mm) is allowed for a length of 300 mm in the main scanning direction corresponding to A3SEF. Therefore, it can be said that there is no particular problem with the deviation up to about 15 dots of LED.

  Therefore, in the present embodiment, the image data for driving the yellow LPH 14Y, the magenta LPH 14M, and the cyan LPH 14C is adjusted based on the black LPH 14K, thereby suppressing the occurrence of image shift. Therefore, in the present embodiment, the black image forming unit 11K functions as a specific image forming unit. For example, in the case where a shift as shown in FIG. 8 occurs, the magenta LPH 14M whose main scanning direction distance is longer than the black LPH 14K uses data obtained by partially thinning out magenta image data. On the other hand, in the cyan LPH 14C whose distance in the main scanning direction is shorter than the black LPH 14K, data partially complemented with cyan image data is used.

Such adjustment of the image data is performed by the lighting signal generation unit 110 (see FIG. 5) of the signal generation circuit 100 as a driver provided in each LPH 14. FIG. 9 is a block diagram showing the configuration of the lighting signal generator 110.
The lighting signal generation unit 110 receives the image data sent from the IPS 40 and the line synchronization signal Lsync sent from the control unit 30. The lighting signal generator 110 is connected to a crystal oscillator 150 provided outside. The lighting signal generator 110 also receives an external clock CLK 1 sent from the crystal oscillator 150. The cycle of the external clock CLK1 is set to be the same as the cycle of transferring individual image data as will be described later. Further, the lighting signal generation unit 110 outputs the lighting signals ΦI1 to ΦI58 to 58 SLED chips constituting the LPH 14.

The lighting signal generation unit 110 includes an internal clock generation unit 111, a register 112, a D-type flip-flop (D-FF) 113, and a staggered array correction unit 114. The lighting signal generator 110 further includes a lighting time calculator 115, a serial / parallel converter 116, and a pulse generator 117 (117_1 to 117_58).
The internal clock generation unit 111 as a clock generation unit (clock generation unit) is a so-called PLL (Phase Locked Loop) circuit, and receives the line synchronization signal Lsync input from the outside and the frequency division ratio information stored in the register 112. The internal clock (clock) CLK2 is generated from the external clock CLK1. The internal clock CLK2 can be different for each LPH 14. Details of the internal clock generation unit 111 and the register 112 will be described later.

  Further, image data sent from the IPS 40 is input to the D input of the D-FF 113 functioning as a latch unit (latch unit). Further, the internal clock CLK2 generated by the internal clock generator 111 is input to the clock input of the D-FF 113. Accordingly, the D-FF 113 creates corrected image data (referred to as latch data in the following description) by latching the image data when the internal clock CLK2 is turned on, and outputs it as an output Q.

  The staggered array correction unit 114 has a function of shifting the light emission timing of the SLED chips (see FIGS. 3 and 4) arranged in a staggered pattern. Specifically, the light emission timing of the SLED chip arranged on the downstream side in the sub-scanning direction is delayed by a predetermined time from the light emission timing of the SLED chip arranged on the upstream side in the sub-scanning direction. Thereby, it is possible to align the electrostatic latent image formed by the SLED chip arranged on the upstream side in the sub scanning direction and the electrostatic latent image formed by the SLED chip arranged on the downstream side in the sub scanning direction. become.

The lighting time calculation unit 115 uses the zigzag array corrected latch data sent from the staggered array correction unit 114 and the correction value for each LED read from the EEPROM 102 to turn on the lighting time of each LED (lighting clock). Number).
The serial / parallel converter 116 converts the number of lighting clocks for each LED calculated by the lighting time calculator 115 into parallel data. Further, the pulse generator 117 (117_1 to 117_58) generates each of the lighting signals ΦI1 to ΦI58 by changing the amount of light by performing pulse width modulation on each signal converted in parallel by the serial / parallel converter 116, and configures the LPH14. Output to each LED chip. In the present embodiment, the staggered array correction unit 114, the lighting time calculation unit 115, the serial / parallel conversion unit 116, and the pulse generator 117 constitute an output means (output unit).

  FIG. 10 is a diagram illustrating a detailed configuration of the internal clock generation unit 111 provided in the lighting signal generation unit 110. The internal clock generator 111 includes a frequency divider 1 / M 121, a phase comparator 122, a loop filter 123, a VCO (Voltage Controlled Oscillator) 124, a frequency divider 1 / N 125, and a frequency division ratio setting unit 126. Yes. That is, the internal clock generator 111 is configured with a PLL (Phase Locked Loop) frequency synthesizer.

  The frequency divider 1 / M 121 divides the external clock CLK1 sent from the crystal oscillator 150 by 1 / M and outputs it to one input terminal of the phase comparator 122. The phase comparator 122 receives an input signal from the frequency divider 1 / M 121 (external clock CLK1 divided by 1 / M) and an input signal from the frequency divider 1 / N 125 (internal clock CLK2 as will be described later). ) Is detected and output to the loop filter 123. The loop filter 123 smoothes the DC signal that is the output from the phase comparator 122 and outputs it to the VCO 124. The loop filter 123 can be configured by a low-pass filter or the like that removes a low-frequency ripple component. The VCO 124 controls the oscillation frequency according to the DC signal input from the loop filter 123, and outputs it to the D-FF 113 (see FIG. 9) as the internal clock CLK2. The frequency divider 1 / N 125 divides the internal clock CLK2 output from the VCO 124 by 1 / N and outputs the result to the other input terminal of the phase comparator 122. Then, the frequency division ratio setting unit 126 is based on the frequency division ratio information stored in the register 112 and the frequency division ratio 1 / M in the frequency divider 1 / M 121 and the frequency division ratio in the frequency divider 1 / N 125. Set 1 / N. By adopting such a configuration, the internal clock generator 111 can generate and output the internal clock CLK2 obtained by scaling the external clock CLK1 to N / M times.

Now, acquisition of frequency division ratio information (frequency division ratio / 1M and frequency division ratio 1 / N) in each LPH 14 will be described with reference to the flowchart shown in FIG.
First, in the image forming apparatus, exposure is performed using each LPH 14 based on predetermined image data, and then development, transfer (primary transfer, secondary transfer), and fixing are executed. That is, a test pattern is formed on the paper P and output (step 101). In creating the test pattern, all the LEDs emit light in each LPH 14, and the respective main scanning direction distances (yellow main scanning direction distance Ly, magenta main scanning direction distance Lm, cyan main scanning direction distance Lc, and black It is preferable to obtain a main scanning direction distance Lk).

  Next, the test pattern output in step 101 is read by IIT3 (step 102). Then, the main scanning direction distance of each color test pattern, that is, the yellow main scanning direction distance Ly, the magenta main scanning direction distance Lm, the cyan main scanning direction distance Lc, and the black main scanning direction distance Lk are acquired from the read image data ( Step 103). Next, yellow (Y color), magenta (M color), and cyan (C color) main scanning direction distances (yellow main scanning direction distance Ly, magenta mains) with black (K color) black main scanning direction distance Lk as a reference. The magnification (ratio) of the scanning direction distance Lm and the cyan main scanning direction distance Lc) is calculated (step 104). That is, the degree of expansion / contraction of the yellow main scanning direction distance Ly, the magenta main scanning direction distance Lm, and the cyan main scanning direction distance Lc with respect to the black main scanning direction distance Lk is acquired.

  Furthermore, in order to make the main scanning direction length at the time of light emission of these Y, M, and C colors coincide with the black main scanning direction distance Lk from the magnifications of Y, M, and C obtained in step 104. The value of the necessary internal clock CLK2 is obtained. Next, a frequency division ratio 1 / M and a frequency division ratio 1 / N for obtaining the obtained value of the internal clock CLK2 are calculated (step 105). Then, the frequency division ratio 1 / M and the frequency division ratio 1 / N obtained in step 105 are stored in the register 112 provided in the corresponding signal generation circuit 100 (lighting signal generation unit 110) of each LPH 14 (step 106). ), A series of operations are terminated. In step 106, a value of the frequency division ratio 1 / M = frequency division ratio 1 / N = 1 is written in the register 112 provided in the black LPH 14 serving as the reference color.

  Next, the operation of the D-FF 113 during the image forming operation (exposure operation) will be described with a specific example. FIG. 12 is a timing chart showing the relationship among the line synchronization signal Lsync, the image data from the IPS 40, the internal clock CLK2 from the internal clock generator 111, and the latch data from the D-FF 113. Among these, FIG. 12A shows a case where N / M = 1, that is, the cycle of the external clock CLK1 is set to be the same as the cycle of transferring individual image data. FIG. 12B shows a case where N / M> 1, that is, the cycle of the internal clock CLK2 is set shorter than the cycle of transferring individual image data. In this example, N / M = 10/7. Further, FIG. 12C shows a case where N / M <1, that is, the cycle of the internal clock CLK2 is set longer than the cycle of transferring individual image data. In this example, N / M = 7/10.

  Now, the basic operation of the D-FF 113 will be described. When the line synchronization signal Lsync rises, input of image data is started from the IPS 40 after a predetermined time has elapsed. At this time, the image data is 1 (image data to be supplied to the first dot LED: see FIG. 5), 2, 3..., 14847, 14848 (image data to be supplied to the 14848 dot LED: see FIG. 5). Are entered in the order. The D-FF 113 latches the value of the image data at the rising timing of the internal clock CLK2, and outputs it as latch data.

Here, in the example shown in FIG. 12A, the cycle of the internal clock CLK2 is set to be the same as the cycle of transferring individual image data. Therefore, the D-FF 113 acquires the latch data 1, 2, 3,..., 14847, 14848 from the image data 1, 2, 3,. That is, in this example, the image data and the number of latch data are the same, although some phase lag occurs with respect to the image data. Therefore, for example, image data 1 is supplied as latch data 1 to the LED of the first dot, and image data 10 is supplied as latch data 10 to the LED of the 10th dot, for example.
That is, in this case, the image data itself is output as latch data. For this reason, for example, in the example shown in FIG. 8, such a setting may be made for the black LPH 14K as the reference color and the yellow LPH 14Y having the same main scanning direction distance as the black LPH 14K.

In the example shown in FIG. 12B, the cycle of the internal clock CLK2 is set shorter than the cycle of transferring individual image data and is asynchronous. For this reason, in the D-FF 113, for example, after the latch data 1 is acquired from the image data 1, the next latch data 2 is also acquired from the image data 1. The next latch data 3 is acquired from the image data 2. That is, in this example, a situation occurs in which a plurality of latch data is acquired from the same image data, and as a result, the number of latch data is larger than the number of image data. Therefore, for example, image data 1 is supplied as latch data 1 to the LED of the first dot, but image data 7 is supplied as latch data 10 to the LED of the 10th dot, for example. Note that the timing at which a plurality of latch data is acquired from the same image data is not periodic but random.
That is, in this case, the image data expanded in the main scanning direction is output as latch data. Therefore, for example, in the example shown in FIG. 8, such a setting may be made for the cyan LPH 14C having a shorter main scanning direction distance than the black LPH 14K as the reference color.

Further, in the case of the example shown in FIG. 12C, the cycle of the internal clock CLK2 is set longer than the cycle of transferring individual image data and is asynchronous. For this reason, for example, after acquiring the latch data 1 from the image data 1, the next latch data 2 is acquired from the image data 3 by skipping the image data 2. The next latch data 3 is acquired from the image data 4. That is, in this example, image data that is not adopted as latch data is generated, and as a result, the number of latch data is smaller than the number of image data. Therefore, in this example, the image data 1 is supplied as the latch data 1 to the LED of the first dot, for example, but the image data 13 is supplied to the LED of the 10th dot, for example. Note that the timing at which image data that is not employed as latch data is generated is not periodic but random.
That is, in this case, the image data compressed in the main scanning direction is output as latch data. For this reason, for example, in the example shown in FIG. 8, such a setting may be made for the magenta LPH 14M having a longer main scanning direction distance than the black LPH 14K as the reference color.

  As described above, in this embodiment, by using the D-FF 113 and appropriately changing the setting of the internal clock CLK2, image data (latch data) that is actually supplied to each LPH 14 is generated from the input image data. In this case, data can be thinned out or complemented easily. As a result, it is possible to suppress the occurrence of displacement in the main scanning direction (image displacement) when images created using the LPHs 14 are superimposed. Since the data thinning position or complementary position at the time of obtaining the latch data is randomly determined by the set value of the internal clock CLK2, the influence of the image due to the data thinning or complementing can be suppressed. If the cycle of the line synchronization signal Lsync shown in FIG. 12 (the exposure cycle of one line) and the cycle of the internal clock CLK2 are set asynchronously, the synchronous relationship between the image data and the internal clock changes for each line. Then, the data thinning position or the complementary position in the latch data can be changed for each line, and the influence on the image by the data thinning or the complementary can be further reduced.

<Embodiment 2>
The first embodiment aims to perform alignment (magnification adjustment) of the four LPHs 14 mounted in the tandem type image forming apparatus in the main scanning direction, and adjusts the internal clock CLK2 to correct the magnification of the image data. Had gone. On the other hand, in the present embodiment, a coping method when the resolution (input resolution) of the image data sent from the PC 2 or IIT 3 shown in FIG. 1 is different from the resolution (output resolution) of the LPH 14 is shown. It is. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  Next, the operation of the D-FF 113 during the image forming operation (exposure operation) will be described with a specific example. FIG. 13 is a timing chart showing the relationship among the line synchronization signal Lsync, the image data from the IPS 40, the internal clock CLK2 from the internal clock generator 111, and the latch data from the D-FF 113. Among these, FIG. 13A shows a case where N / M = 1, that is, the cycle of the external clock CLK1 is set to be the same as the cycle of transferring individual image data. That is, the input resolution and the output resolution are the same. As described above, since the output resolution of the LPH 14 is 1200 dpi, in this case, the input resolution is also 1200 dpi. FIG. 13B shows a case where N / M = 2, that is, the cycle of the internal clock CLK2 is set to twice the cycle of transferring individual image data. That is, the input resolution is half of the output resolution. Since the output resolution of the LPH 14 is 1200 dpi, in this case, the input resolution is 600 dpi. Further, FIG. 13C shows a case where N / M> 1/2, that is, the cycle of the internal clock CLK2 is set to half the cycle of transferring individual image data. That is, the input resolution is twice the output resolution. Since the output resolution of the LPH 14 is 1200 dpi, in this case, the input resolution is 2400 dpi.

  In the example shown in FIG. 13A, image data and latch data correspond in a one-to-one relationship. That is, the same latch data as the image data is output. In the example shown in FIG. 13B, two pieces of latch data are output from one piece of image data. That is, twice the latch data of the image data is output, and the output resolution is apparently doubled. Further, in the example shown in FIG. 13C, latch data is output while skipping image data one by one. That is, half of the image data is output as latch data, and the output resolution is apparently half.

  As described above, in the present embodiment, resolution conversion can be easily performed only by adjusting the internal clock CLK2. Therefore, even when the input resolution and the output resolution do not match, by performing such resolution conversion, expansion and contraction of the image with respect to the main scanning direction can be prevented when performing output using the LPH 14. .

  In the first and second embodiments, the LPH 14 has been described as an example. However, the present invention is not limited to this, and the present invention is not limited to this. For a print head using a liquid crystal shutter, an organic EL element, etc. Can be applied as well. Further, the present invention is not limited to the type that forms an electrostatic latent image by exposure, but can be similarly applied to an apparatus that forms an image, such as an inkjet head.

1 is a diagram showing an overall configuration of an image forming apparatus equipped with an LED print head (LPH) to which the present embodiment is applied. It is the figure which showed the structure of LPH. It is a top view of a LED circuit board. It is a figure explaining the connection part of each SLED chip. It is the figure which showed the wiring diagram currently formed on the LED circuit board. It is a circuit diagram for demonstrating the structure of a SLED chip (SLED). 6 is a timing chart for explaining LPH driving (lighting operation) in an image forming operation. FIG. 6 is a diagram for explaining a positional deviation in a main scanning direction when four LPHs are mounted on an image forming apparatus. It is the block diagram which showed the structure of the lighting signal generation part. It is the block diagram which showed the detailed structure of the internal clock generation part. It is a flowchart about the acquisition operation of the frequency division ratio information (frequency division ratio / 1M and frequency division ratio 1 / N) in each LPH. (a)-(c) is a timing chart for demonstrating operation | movement of the D-type flip-flop circuit in Embodiment 1. FIG. (a)-(c) is a timing chart for demonstrating operation | movement of the D-type flip-flop circuit in Embodiment 2. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Digital color printer, 2 ... PC (personal computer), 3 ... IIT (image reading apparatus), 14 ... LPH, 30 ... Control part, 40 ... IPS (image processing part), 62 ... LED circuit board, 63 ... SLED , 64 ... Rod lens array, 100 ... Signal generation circuit, 110 ... Lighting signal generation unit, 111 ... Internal clock generation unit, 112 ... Register, 113 ... D-type flip-flop circuit (D-FF), 114 ... Staggered array correction unit , 115 ... lighting time calculation section, 116 ... serial / parallel conversion section, 117 ... pulse generator, 130 ... transfer signal generation section, 150 ... crystal oscillator, Lsync ... line synchronization signal, CLK1 ... external clock, CLK2 ... internal clock

Claims (9)

A driver used in a print head for writing an image,
Clock generating means for generating a clock;
Latch means for latching input image data based on the clock supplied from the clock generation means and outputting as latch data;
Output means for converting the latch data output from the latch means into a format corresponding to the print head and outputting the converted data to the print head;
The driver, wherein the clock generation means adjusts the period of the clock according to the image writing width of the print head. The clock generation means includes a PLL (Phase Locked Loop) frequency synthesizer that generates the clock by multiplying an external clock input from an externally provided oscillator,
2. The driver according to claim 1, wherein the latch means comprises a D-type flip-flop circuit having the image data as a D input and the clock as a clock input.   2. The driver according to claim 1, wherein a cycle of the clock generated by the clock generation unit is asynchronous with a cycle in which the image data corresponding to one pixel is input to the latch unit.   2. The cycle of the clock generated by the clock generation means is an integral multiple or a fraction of an integer with respect to a period in which the image data corresponding to one pixel is input to the latch means. The listed driver. An image carrier;
A charger for charging the image carrier;
An exposure device that exposes the charged image carrier to form an electrostatic latent image;
A developing device for developing the electrostatic latent image formed on the image carrier with toner;
In an image forming apparatus comprising an image forming unit having a transfer device for transferring a toner image formed on the image carrier to a recording material,
The exposure device
A light emitting unit for exposing the image carrier by emitting light; and
A clock generator for generating a clock;
A latch unit that latches input image data based on the clock supplied from the clock generation unit, and outputs the latched data.
An output unit that converts the latch data output from the latch unit into a format corresponding to the light emitting unit and outputs the converted data to the light emitting unit;
The image forming apparatus, wherein the clock generation unit adjusts a cycle of the clock according to a length in a main scanning direction of an electrostatic latent image formed by the light emitting unit. A plurality of the image forming units;
6. The image forming apparatus according to claim 5, wherein a generation cycle of the clock in the clock generation unit is different for each image forming unit.   The image forming apparatus according to claim 5, wherein the light emitting unit includes a light emitting element array configured by arranging a plurality of light emitting elements in a main scanning direction. A plurality of the image forming units;
A register for storing the clock generation period information in the clock generation unit;
6. The clock generation period information set on the basis of a main scanning direction length of an exposure device in a specific image forming unit of the plurality of image forming units is stored in the register. The image forming apparatus described. The plurality of image forming units include a black image forming unit that forms a black toner image, and an other color image forming unit that forms a toner image of a color other than black,
The image forming apparatus according to claim 8, wherein the specific image forming unit is the black image forming unit.

Images