JP2003224072A - Semiconductor structure and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress crack generation at the time of epitaxially growing a nitride semiconductor on an Si based substrate and to improve crystal quality. <P>SOLUTION: An Ni layer is formed on the Si substrate by a sputtering method, and Ni<SB>3</SB>N layer is formed by heat-treating it at 500 to 900°C in an ammonia air flow. It is turned to a template layer and an AlN layer and a GaN layer are epitaxially grown successively. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device made of a nitride semiconductor formed on a Si-based substrate, a semiconductor device such as a transistor and a diode constituting a light emitting and receiving device, and more particularly to a substrate and a nitride semiconductor. Regarding the structure of the interface with.

[0002]

2. Description of the Related Art GaN-based nitride semiconductors have high dielectric breakdown field strength, electron saturation rate, and thermal conductivity, and are particularly promising as high frequency power device materials. Large diameter and inexpensive Si
If the nitride semiconductor can be formed on the substrate, not only the cost of the nitride semiconductor element can be reduced, but also the light emitting / receiving element made of the nitride semiconductor, the high frequency power element and the Si-based LSI can be realized in one chip. .

Incidentally, the Si-based substrate described in this specification means
Not only the Si substrate but also a Si substrate having at least a part of a mixed crystal layer such as SiGe or SiGeC, or a substrate having at least a part of the substrate surface made of Si. Also,
A nitride semiconductor refers to a semiconductor containing N and at least one element of B, Al, Ga, and In.

Is a nitride semiconductor generally hexagonal
In the case of using a Si-based material for the substrate,
A substrate with a (111) plane orientation that serves as a hexagonal template
used. -17% of GaN with respect to Si (111)
Lattice mismatch and + 2 × 10 ^-6Difference in thermal expansion coefficient
Have. The growth temperature of GaN depends on the growth method.
Although it depends also on, it is about 700 to 1000 ° C, and after growth
Causes tensile stress on the GaN layer even during growth
The film thickness of 1 to 1 can grow without cracks.
It is about 2 μm or less. Note that prior to the growth of the GaN layer
Generally, SiC layers, AlN layers, AlGaN layers, etc.
Formed as a buffer layer.

When a (100) substrate, which is the mainstream in Si-based LSI processes, is used, the cubic phase tends to coexist in the nitride semiconductor, but the cubic phase is precipitated by controlling the epitaxial growth conditions. Can be suppressed. For example, "Applied Physics Letter
s Vol. 79 (2001) L1459 to L1461 "describes that a hexagonal GaN thin film (film thickness 2 μm) could be grown on a Si (100) substrate via an AlN buffer layer without cracks. ing.

[0006]

However, since the distribution of the a-axis orientation in the C-plane is large, there is a concern that the carrier mobility in the C-plane will decrease.

Therefore, the present invention suppresses the occurrence of cracks when epitaxially growing a nitride semiconductor on a Si-based substrate, improves the crystal quality, and contributes to the improvement of the electrical characteristics and reliability of the semiconductor device having this structure. The purpose is to

[0008]

In order to achieve the above object, a semiconductor structure according to the present invention has a transition metal element X (X is V, Cr, Co, Ni, Z) formed on a Si-based substrate.
a layer containing an element selected from the group consisting of r, Nb, Mo, Hf, Ta and W), and a semiconductor layer containing a group III element and N formed on the layer containing the transition metal element X. There is. In the above structure, the layer containing the transition metal element X preferably contains the transition metal elements X and N.
Further, it is preferable that the content of N in the layer containing the transition metal element X increases from the side in contact with the Si-based substrate to the side in contact with the semiconductor layer containing the group III element and N. Further, it is preferable that the lattice constant of the layer containing the transition metal element X decreases from the side in contact with the Si-based substrate to the side in contact with the semiconductor layer containing the group III element and N.

A semiconductor structure according to another invention is a transition metal element X (X is V, Cr, Co,) formed on a Si-based substrate.
A layer containing Ni, Zr, Nb, Mo, Hf, Ta, and W) and N, and a group III element and N formed on the layer containing the transition metal elements X and N A hexagonal semiconductor layer, and the atomic arrangement of the layer containing the transition metal elements X and N is hexagonal at the interface with the hexagonal semiconductor layer containing the group III element and N. . In the above structure, the atomic arrangement of the layer containing the transition metal elements X and N is preferably cubic at the interface with the Si-based substrate. Further, the plane direction of the Si-based substrate is preferably {100}.

Further, it is preferable that the surface of the Si-based substrate has a stepped shape composed of periodic recessed stripes, and an air gap is formed above the recessed portion.

The method of manufacturing a semiconductor structure according to the present invention comprises:
Transition metal element X (X is V, Cr, Co, N
i, Zr, Nb, Mo, Hf, Ta, and W), and a step of forming a layer containing a transition metal element X by a sputtering method, and a step of heat-treating the layer containing the transition metal element X in a stream containing ammonia. And II on the layer containing the transition metal element X.
And a step of forming a semiconductor layer containing a group I element and N by a metal organic chemical vapor deposition method.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a semiconductor structure and a method of manufacturing the same according to the present invention will be described in detail below.

(First Embodiment) FIG. 1 is a sectional view schematically showing a semiconductor structure according to the present invention. This semiconductor structure comprises a Ni (102), N (N),
The i ₃ N layer 103, the AlN layer 104, and the GaN layer 105 are sequentially laminated.

The structure of each layer and the manufacturing method thereof will be described below. Although the (100) plane is used for the Si substrate 101, a Si substrate having another plane orientation can also be used. For example, the (111) plane can be used. Generally, in order to epitaxially grow a hexagonal nitride semiconductor, Si atoms are hexagonally arranged (11
It is preferable to use the 1) plane. Further, not only the low index surface but also a substrate having an off angle in a certain direction may be used. For example, a substrate having a 6 ° off angle from the (100) plane in the [011] direction, or a substrate having a 0.2 ° off angle from the (100) plane in the [01-1] direction can be used. Since these can control the state and structure of the interface layer formed on the substrate surface, it is possible to control the density of dislocations generated due to lattice mismatch and the orientation distribution of crystal axes. . The conductivity type of the substrate may be either n-type or p-type. A high resistance substrate may be used depending on the application. In addition to the Si substrate,
A Si substrate having at least a part of a mixed crystal layer such as SiGe or SiGeC, or a substrate having at least a part of the substrate surface made of Si may be used.

The Ni layer 102 is a layer for reflecting the crystallographic orientation of the Si substrate 101 in the Ni ₃ N layer 103, and a layer for relaxing the tensile stress applied to the AlN layer 104 and the GaN layer 105. It is provided. N
The i layer 102 is not necessarily a single crystal layer, and may be an oriented polycrystal layer. The film thickness is about 1 to 100 nm, preferably about 1 to 10 nm. This suppresses the occurrence of cracks in the nitride semiconductor layer.

The crystal structure of Ni is a cubic system (face centered cubic lattice), and the lattice mismatch with respect to Si is about -9% and AlN and G.
It is about half of the lattice mismatch of aN with respect to Si. And N
The coefficient of thermal expansion of i is about 10 times that of Si, and that of AlN is about 9 times that of GaN.
It is as large as about 7 times the thermal expansion coefficient. Therefore, Al
The tensile stress applied to the N layer 104 and the GaN layer 105 during the growth is reduced as compared with the case where the Ni layer 102 is not interposed, and is further reduced after the growth. Therefore, the occurrence of cracks in the nitride semiconductor layer is significantly suppressed.

The Ni ₃ N layer 103 has an AlN layer 1 formed thereon.
04 and GaN layer 105 are provided as a template for growing. The Ni ₃ N layer 103 does not necessarily have to be a single crystal layer, and may be an oriented polycrystal layer. The film thickness is about 1 to 100 nm, preferably 5 to
It is about 50 nm. As a result, c in the nitride semiconductor layer
The orientation distribution of the axis and the a-axis is improved, and a high quality nitride semiconductor crystal can be obtained.

The crystal structure of Ni ₃ N is a hexagonal system in which N atoms have penetrated into the Ni crystal, and the AlN layer 104 and the GaN layer 1
05 serves as a template for growth by orienting c-axis. The lattice mismatch for AlN is about -14% and the coefficient of thermal expansion is about 8 times that for AlN. Although Ni ₃ N is used in the present embodiment, N forms a compound at various ratios with respect to Ni, so N is not necessarily limited to this composition. That is, a NiN layer having a desired lattice constant can be formed as the template layer. Further, the composition may change in the NiN layer, and for example, the N content may continuously or stepwise increase from the interface with the Ni layer 102 to the interface with the AlN layer 104.

The AlN layer 104 has the GaN layer 10 formed thereon.
5 provided as a single crystal template for growing. The film thickness is about 5 to 500 nm, preferably 10
Is about 200 nm. Epitaxial growth proceeds two-dimensionally in this layer, the orientation distribution of the c-axis and the a-axis in the GaN layer 105 is improved, and a high-quality nitride semiconductor crystal can be obtained. Although the AlN layer is used in the present embodiment, in addition to this, an AlGaN layer, an AlGaInN layer,
A GaInN layer, an InN layer or the like may be used.

With the above structure, the GaN layer 105 can be grown while preventing the generation of cracks if the film thickness is about 3 μm or less. There are threading dislocations that are considered to be caused by lattice mismatch with the underlayer, and their density is 10 ⁸ to
It is about 10 ⁹ cm ^-2 . Not only GaN but also other nitride semiconductors can be formed in the portion corresponding to the GaN layer 105. Therefore, it is possible to form the nitride semiconductor multilayer film necessary for forming a light emitting / receiving element, a high frequency power element, etc. on the AlN layer 104. AlN
If a GaInN layer with a film thickness of about 30 to 100 nm is inserted between the layer 104 and the GaN layer 105, the generation of cracks can be suppressed more effectively.

Although the case where the Ni layer 102 is formed on the Si substrate 101 has been described in the present embodiment, V, Cr, Co, Zr, Nb, Mo and H are used in addition to Ni.
A transition metal element selected from the group consisting of f, Ta, and W can be used, and the same effect can be obtained.

Next, a method of manufacturing the semiconductor structure as shown in FIG. 1 will be described. The surface of the Si substrate 101 is terminated with hydrogen by cleaning with hydrofluoric acid, and the Ni layer 10 is formed.
Prevents the surface from being oxidized by the time 2 is formed.

To form the Ni layer 102, a sputtering method is used to give orientation of crystal axes. An appropriate method may be selected from various existing sputtering methods such as DC sputtering, magnetron sputtering, and ECR sputtering. By sputtering the Ni target with argon, the Ni layer 10 is formed on the Si substrate 101 facing the Ni target.
2 is formed with a film thickness of about 15 nm. The Si substrate 101 may be heated to, for example, about 400 ° C. in order to enhance the orientation. Further, in order to prevent the Ni layer 102 from balling up during heating for forming the Ni ₃ N layer 103 or the AlN layer 104 thereon, the Si substrate 10
A metal layer for improving the wettability of 1 and the Ni layer 102 may be interposed at the interface between the two. For example, a Ti layer is formed with a film thickness of about 5 nm.

To form a layer above the Ni layer 102, a heat treatment in an ammonia (NH ₃ ) stream in a metal organic vapor phase epitaxial growth (MOVPE) apparatus and a MOVPE method are used.

Si substrate 101 on which Ni layer 102 is formed
Was placed in the reaction chamber of the MOVPE device and evacuated,
1 atm of NH₃10 minutes at 500-900 ° C in airflow
Heat and Ni₃The N layer 103 is formed. Ni in this process
N is diffused in the layer 102, and the depth from the surface is 10 nm, for example.
Layers up to Ni₃It becomes the N layer 103. Ni₃N layer 103 surface
The atomic arrangement of the plane is a hexagonal lattice. As aforementioned,
In this embodiment, Ni ₃N was used, but N is Ni
To form compounds in various proportions, and not necessarily
The composition is not limited to this composition. Heat treatment
Since the N content increases as the processing temperature increases, temperature control
The composition can be controlled by. Also, during heat treatment
The film thickness can be controlled by controlling the
It Therefore, by controlling the heat treatment temperature and time
Structure from Ni layer 102 to NiN layer 103 and
The lattice constant can be controlled. For example, Ni layer 1
02 to the interface with the AlN layer 104.
To increase the quantity continuously or in steps, heat treatment
If you increase the processing temperature continuously or stepwise
Yes. In addition, N is diffused to the interface with the Si substrate 101,
Sufficient heat treatment to substantially eliminate the Ni layer 102
It is also possible to do so.

Subsequently, the AlN layer 104 and the GaN layer 105 are grown by the MOVPE method. That is, the substrate temperature is 1
The temperature is set to 100 ° C., hydrogen and nitrogen are used as carrier gases, and trimethylaluminum (TMA) and NH ₃ are used as raw materials so that the supply molar ratio (V / III ratio) of the group V / group III is 1500, and the AlN layer 104 is grown. Let The film thickness is, for example, about 100 nm, and the growth rate is 5 nm / m.
It is about in. Then, the supply of TMA is stopped, the substrate temperature is set to 1050 ° C., hydrogen and nitrogen are used as carrier gases, and trimethylgallium (TMG) and NH ₃ are used as raw materials so that the V / III ratio becomes 7,000 to form the GaN layer 105. Grow. The film thickness is, for example, about 3 μm,
The growth rate is about 30 nm / min. Then TM
The supply of G and NH ₃ is stopped and the temperature is cooled to room temperature to obtain a semiconductor structure as shown in FIG.

The method of manufacturing the semiconductor structure according to the present invention is not limited to the method described in this embodiment, and M
In the process using the OVPE method, instead of the hydride vapor phase epitaxial growth (HVPE) method or the molecular beam epitaxial growth (MBE) method, all the methods that have been proposed to grow a nitride semiconductor crystal are applied. it can. Further, in order to form the Ni ₃ N layer 103, a reactive sputtering method may be used instead of the heat treatment of the Ni layer 102 in the ammonia stream. That is, following the formation of the Ni layer 102, nitrogen is also introduced and sputtering is performed. Further, with respect to the step using the sputtering method, all methods proposed so far to grow highly oriented metal film and nitride film crystal such as MBE method and MOCVD method can be applied instead of using the sputtering method. .

(Second Embodiment) FIG. 2 is a sectional view schematically showing a semiconductor structure according to the present invention. This semiconductor structure comprises a Zr layer 202, A
1N layer 203 and GaN layer 204 are sequentially stacked.

Hereinafter, the structure of each layer and the manufacturing method thereof will be described while referring to differences from the first embodiment.

The Zr layer 202 has a hexagonal crystal structure, and the crystallographic orientation of the Si substrate 201 is controlled by the AlN layer 203.
And a layer for relieving the tensile stress applied to the AlN layer 203 and the GaN layer 204. That is, the Zr layer 202 does not necessarily have to be a single crystal layer, and may be an oriented polycrystal layer. The film thickness is about 1 to 100 nm, preferably about 1 to 10 nm. This suppresses the occurrence of cracks in the nitride semiconductor layer.

To form the Zr layer 202, a sputtering method is used to give the orientation of crystal axes. An appropriate method may be selected from various existing sputtering methods such as DC sputtering, magnetron sputtering, and ECR sputtering. The Zr layer 20 is formed on the Si substrate 201 facing the Zr target by sputtering the Zr target with argon.
2 is formed with a film thickness of about 5 nm, for example. The Si substrate 201 may be heated to, for example, about 400 ° C. in order to enhance the orientation. Further, a metal layer for improving the wettability of the Si substrate 201 and the Zr layer 202 is formed on the interface between the Si substrate 201 and the Zr layer 202 in order to prevent the Zr layer 202 from being balled up during heating to form the AlN layer 203 on this. You may intervene.

The MOVPE method is used to form the AlN layer 203 and the GaN layer 204. The Si substrate 201 on which the Zr layer 202 is formed is placed in the reaction chamber of the MOVPE apparatus and evacuated, then the substrate temperature is set to 1100 ° C., the pressure is set to 0.2 atm, and hydrogen and nitrogen are used as carrier gases for TMA and NH _3. Is supplied as a raw material so that the V / III ratio becomes 2000, and the AlN layer 203 is grown. The film thickness is, for example, about 200 nm, and the growth rate is about 10 nm / min. Next, the supply of TMA is stopped and the substrate temperature is adjusted to 105
TMG with hydrogen and nitrogen as carrier gas
Then, NH ₃ is supplied as a raw material so that the V / III ratio becomes 9000, and the GaN layer 204 is grown. The film thickness is, for example, about 3 μm, and the growth rate is about 30 nm / min. After that, the supply of TMG and NH ₃ is stopped and the temperature is cooled to room temperature to obtain a semiconductor structure as shown in FIG.

Although the case where the Zr layer 202 is formed on the Si substrate 201 has been described in the present embodiment, V, Cr, Co, Ni, Nb, Mo and H are used in addition to Zr.
A transition metal element selected from the group consisting of f, Ta, and W can be used, and the same effect can be obtained.

(Third Embodiment) As described in the first embodiment, high density threading dislocations are generated in the nitride semiconductor crystal on the Si-based substrate. It can be reduced by several orders of magnitude, and high quality crystals can be easily obtained. 3 to 6 are sectional views schematically showing a semiconductor structure according to the present invention according to a manufacturing procedure. This semiconductor structure is used for a heterojunction field effect transistor (HFET), and includes an NbN layer 30 on a Si (100) substrate 301 having a step shape composed of periodic recessed stripes.
2, AlGaN layer 303, GaN layer 305, AlGaN
Spacer layer 306, n-type AlGaN electron supply layer 307,
It has a structure in which AlGaN cap layers 308 are sequentially stacked, and has an air gap 304 above the recess portion. 309 is a source electrode, 310 is a gate electrode, 311
Is a drain electrode.

The structure of each layer and the manufacturing method thereof will be described below. Here, as the substrate 301, a substrate having a step shape formed of periodic recessed stripes was used.

In the present embodiment, the MOVPE method is used as a method for growing a nitride semiconductor crystal, but the method for manufacturing a semiconductor structure according to the present invention is not limited to the MOVPE method, and a nitride such as HVPE method is used. All the methods proposed so far can be applied to selectively grow a semiconductor crystal.

First, a resist is coated on a Si substrate, and the resist is stripe-width-approx. 1 by photolithography.
Processing is performed in a stripe shape in a direction parallel to [-1-12] with a μm and a cycle of about 4 μm. Using the resist as a mask, the substrate 301 is processed into a recess shape (concave shape) by wet etching. At this time, the width of the recess portion is about 3 μm, and the width of the ridge portion (the portion where the resist is) is about 1 μm. The depth of the recess is about 30 to 800 nm. Then, the striped resist is removed to obtain a substrate 301 having a step shape (FIG. 3). The length of the stripe (length in the direction perpendicular to the paper surface in FIG. 3) may be sufficiently longer than the stripe width, but in order to suppress the occurrence of cracks, it is about several to 100 times the stripe width. Is preferred.

Next, an NbN layer 302 is formed by ECR sputtering on the Si substrate 301 which has been hydrogen terminated by hydrofluoric acid cleaning. By sputtering the Nb target with argon and nitrogen, the NbN layer 302 is formed on the Si substrate 301 facing the Nb target, for example, with a film thickness of about 15 nm. As a result, the step of the substrate is NbN
Covered with layer 302 (FIG. 4). The Si substrate 301 may be heated to, for example, about 400 ° C. in order to enhance the orientation of the crystal axes.

The crystal structure of NbN is a hexagonal system with an arbitrary composition from Nb ₂ N to NbN, and the lattice constant changes with the composition. Therefore, by controlling the sputtering conditions, NbN having a lattice constant desired as a template layer can be obtained.
The layer 302 can be formed. In addition, the NbN layer 30
2 may have a different composition, for example, the Si substrate 30.
N from the interface with AlGaN layer 303 to the interface with AlGaN layer 303
The content may be continuously or stepwise increased or decreased.

In order to form the NbN layer 302, in addition to the reactive sputtering method, MBE method, MOCVD method and the like, all of which have been proposed so far to grow highly oriented metal films and nitride film crystals. The method can be applied. Also,
It is also possible to form an Nb layer and heat-treat this in an NH ₃ stream to nitride.

To form a layer above the NbN layer 302, M
The OVPE method is used.

Si substrate 30 on which NbN layer 302 is formed
1 was placed in the reaction chamber of the MOVPE apparatus and evacuated, then the substrate temperature was 1100 ° C., the pressure was 0.1 atm, and hydrogen was used as a carrier gas and TMA, TMG, and NH ₃ were supplied as raw materials. In this process, AlG is also used in the recess.
Although the aN layer 303 grows, the growth rate in the film thickness direction is slow and the lateral growth rate of AlGaN formed on the top of the ridge is high.
To obtain an AlGaN layer 303 whose main surface is composed of only the C-plane and whose surface is flattened (FIG. 4). The film thickness of the AlGaN layer 303 formed on the top of the ridge is about 1 μm, and the Al content is about 2 to 6%. An air gap 304 is formed above the recess portion.

At the beginning of this process, TMG is not supplied at all or a small amount of it is supplied to form an AlN single crystal template on the NbN layer 302. afterwards,
In order to promote the lateral selective growth of AlGaN crystal nuclei formed on the top of the ridge, the supply amount of TMG is increased,
Reduce TMA supply.

In FIG. 5, a vertical line extending upward from the vicinity of the center of the air gap 304 indicates a portion where the AlGaN layers 303 laterally grown from the tops of the left and right ridges are united. The density of threading dislocations is less than 10 ⁶ cm ^{-2 in} the region above the air gap 304 excluding the merged portion. Also, N
The tilt angle between the C axis in the region in contact with the substrate 301 via the bN layer 302 and the C axis in the region above the air gap 304 is 0.01 to 0.03 degrees. The reason why a high-quality nitride semiconductor layer can be formed in this manner is that the lower surface of the AlGaN layer 303 laterally selectively grown does not contact the lower AlGaN layer 303 due to the presence of the recessed step.

Following the formation of the AlGaN layer 303,
With hydrogen and nitrogen as carrier gases, 1060 ° C,
The HFET structure is grown at 0.4 atm. That is, G
aN layer 305 (film thickness 2 μm), AlGaN spacer layer 3
06 (film thickness 5 to 7 nm), n-type AlGaN electron supply layer 3
07 (film thickness 15 to 20 nm), AlGaN cap layer 3
08 (thickness 3 to 5 nm) are sequentially formed (FIG. 6). Al
The content is, for example, 30%. Silane, for example, is used for n-type doping, and the carrier concentration is 5 × 10 ¹⁸ cm ⁻³ .

The semiconductor wafer obtained by the above crystal growth is subjected to processes such as photolithography, electron beam lithography, dry etching, element isolation, surface passivation, and electrode deposition to produce an HFET element. For surface passivation, for example, SiN, SiO
_{Use 2} . As the gate electrode 310, for example, Ni /
The Au film is formed as the source electrode 309 and the drain electrode 311 by, for example, a Ti / Al film by vapor deposition or the like. In order to suppress the leak current due to the interface state along the threading dislocation, the electron transit region from the end of the source electrode 309 to the end of the drain electrode 311 may be arranged on the air gap 304 where the dislocation density is low. preferable. In particular, it is preferable to dispose the gate electrode 310 immediately below the region with a low dislocation density.

In the present embodiment, the mask for so-called selective growth is not used on the surface of the recess portion, but in order to suppress the crystal growth of the recess portion, the surface of the recess portion is covered with a SiN film or the like. Alternatively, it may be used as a mask layer. Also,
In the present embodiment, the NbN layer 302 is formed on the entire surface of the Si substrate 301, but the NbN layer 302 is formed only on the ridge portion by using lift-off and the recess portion is formed on the Si substrate 30.
1 may be exposed. In this case, the AlGaN layer 3
If the substrate is heated in a NH ₃ stream before forming 03,
Si reacts with NH ₃ to cover the recess with the SiN film.

In this embodiment, the case where the nitride semiconductor structure on the Si-based substrate and the method for manufacturing the same are applied to the electronic device has been described, but a nitride semiconductor crystal having a low dislocation density can be obtained. It can also be applied to a light emitting / receiving element, particularly a semiconductor laser structure and its manufacture, and can obtain high reliability and high yield at low cost.

[0049]

As described above, according to the present invention, it is possible to suppress the occurrence of cracks during epitaxial growth of a nitride semiconductor on a Si-based substrate and obtain a high-quality nitride semiconductor crystal. The electrical characteristics of the semiconductor device provided,
A remarkable effect of improving reliability can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a semiconductor structure according to an embodiment of the present invention.

FIG. 2 is a schematic sectional view of a semiconductor structure according to an embodiment of the present invention.

FIG. 3 is a schematic sectional view illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

FIG. 4 is a schematic sectional view illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

FIG. 5 is a schematic sectional view illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

FIG. 6 is a schematic sectional view illustrating a method of manufacturing a semiconductor structure according to an embodiment of the present invention.

[Explanation of symbols]

101 Si (100) Substrate 102 Ni Layer 103 Ni ₃ N Layer 104 AlN Layer 105 GaN Layer 201 Si (111) Substrate 202 Zr Layer 203 AlN Layer 204 GaN Layer 301 Si (100) Substrate 302 NbN Layer 303 AlGaN Layer 304 Air Gap 305 GaN layer 306 AlGaN spacer layer 307 n-type AlGaN electron supply layer 308 AlGaN cap layer 309 source electrode 310 gate electrode 311 drain electrode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/812 F term (reference) 5F045 AA04 AB09 AB14 AC12 AD14 AD15 AF03 AF13 BB13 HA06 HA24 5F052 KA01 KA05 5F102 GB01 GC01 GD01 GJ03 GL04 GM04 GM08 GR01 GR06 GS01 GS04 GT01 HC01 HC02 HC11 HC21

Claims (9)

[Claims] 1. A transition metal element X formed on a Si-based substrate.
(X is V, Cr, Co, Ni, Zr, Nb, Mo, H
a layer containing an element selected from the group consisting of f, Ta, and W), and a semiconductor layer containing a group III element and N formed on the layer containing the transition metal element X. Semiconductor structure. 2. The semiconductor structure according to claim 1, wherein the layer containing the transition metal element X contains the transition metal elements X and N. 3. The content of N in the layer containing the transition metal element X increases from the side in contact with the Si-based substrate to the side in contact with the semiconductor layer containing the group III element and N. Semiconductor structure. 4. The lattice constant of the layer containing the transition metal element X is S
3. The semiconductor structure according to claim 1, wherein the amount decreases from the side in contact with the i-type substrate to the side in contact with the semiconductor layer containing the group III element and N. 5. A transition metal element X formed on a Si-based substrate.
(X is V, Cr, Co, Ni, Zr, Nb, Mo, H
a layer containing an element selected from the group consisting of f, Ta and W) and N, and a hexagonal semiconductor layer containing a group III element and N formed on the layer containing the transition metal elements X and N. A semiconductor structure characterized in that the atomic arrangement of the layer containing the transition metal elements X and N is hexagonal at the interface with the hexagonal semiconductor layer containing the group III element and N. . 6. The semiconductor structure according to claim 5, wherein the atomic arrangement of the layer containing the transition metal elements X and N is cubic at the interface with the Si-based substrate. 7. The semiconductor structure according to claim 1, wherein the Si-based substrate has a plane orientation of {100}. 8. The surface of the Si-based substrate has a stepped shape composed of periodic recessed stripes, and an air gap is formed above the recessed portion.
7. The semiconductor structure according to any one of 1 to 7. 9. A transition metal element X (X is V,
Cr, Co, Ni, Zr, Nb, Mo, Hf, Ta, W
On the layer containing the transition metal element X; a step of forming a layer containing an element selected from the group) by a sputtering method; a step of heat-treating the layer containing the transition metal element X in an air stream containing ammonia; And a step of forming a semiconductor layer containing a group III element and N by a metal organic chemical vapor deposition method.