JP2003223793A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory capable of reducing a load of current supply of a booster circuit and also capable of suppressing increase of occupied space of the booster circuit when an input/output bit becomes multi-bits. <P>SOLUTION: At writing, a current detection circuit 3 always monitors a Vpp power supply current Ipp supplied from a booster circuit 2. When the Ipp is less than the reference current value, a write control circuit 5 makes Write signals WT[15]-WT[15] an active level sequentially at a constant time interval. When the Ipp increases more than the reference current, the current detection circuit 3 makes the detection signal DTCT the active level and sends it to the write control circuit 5. Upon receipt of this signal, the write control circuit 5 stops generation of write signals. When the Ipp decreases less than the reference current and the detection signal DTCT returns to the inactive level, the write control circuit 5 restarts generation of a next write signal. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory, and more particularly to a non-volatile semiconductor memory having a booster circuit for generating a program voltage.

[0002]

2. Description of the Related Art In a non-volatile semiconductor memory such as an EEPROM or a flash memory, a memory cell is composed of a cell transistor having a floating gate between a gate and a surface of a semiconductor substrate. Data is stored by changing the threshold voltage of the transistor. Writing "1" data to the memory cell is performed by, for example, the gate voltage Vg = 9.
By setting V, drain voltage Vd = 5V, and source voltage = 0V (ground potential), electrons moving from the source to the drain are taken into the floating gate to increase the threshold voltage of the cell transistor. Figure 1
0 (a) is a diagram showing the time change of the drain current of the cell transistor and the time change of the threshold voltage of the cell transistor when writing "1" data. When writing "1" data, the drain current of the cell transistor once rises to several hundreds .mu.A, and then the threshold voltage increases and the drain current decreases due to the injection of electrons into the floating gate.

In a non-volatile semiconductor memory such as an EEPROM or a flash memory, such memory cells are arranged in an array, and data is written or read in the memory cells selected by an external address.
2. Description of the Related Art Recent nonvolatile semiconductor memories generally have a built-in booster circuit that generates a program power supply (Vpp power supply) voltage for supplying a high voltage to the drain and gate of a cell transistor during writing. Figure 10 (b)
FIG. 4 is a circuit diagram of an example of a booster circuit. Periodic signal PA,
The power supply voltage VCC supplied from the outside is boosted by the signal PB having the opposite phase to generate a Vpp power supply voltage. The current supply capability of the booster circuit depends on the frequencies of PA and PB and the capacitance value of the boosting capacitor. However, in order to increase the frequency, a MOS transistor with a large channel width is required, and in order to increase the capacitance value, it is necessary to increase the size of the boosting capacitor. Therefore, a booster circuit with a large current supply capacity occupies a small area. It will be remarkably large. Assuming that the booster circuit has a practical size, in a nonvolatile semiconductor memory having a multi-bit input / output bit configuration, the program power supply (Vpp power supply) current Ipp at the time of writing exceeds the current supply capability of the booster circuit, and the Vpp power supply voltage This may cause deterioration and may lead to writing failure. For this reason,
For example, in a flash memory in which one word has 16 bits, the number of bits to be written at the same time is set to 4 bits, and a divided write technique for writing 1 word (16 bits) by writing four times is used. For example, if the maximum value of the drain current flowing when writing data “1” into one cell transistor is 250 μA, the Vpp power supply current Ipp in 16-bit batch writing is 0.25 mA × 16 = 4 m
A, the current supply capacity of the booster circuit is doubled to 8 mA in consideration of variations in the writing characteristics of the cell transistor.
However, it is difficult to incorporate the booster circuit in the nonvolatile semiconductor memory. On the other hand, in the case of divided writing of 4 bits each, the Vpp power supply current Ipp becomes 0.25 mA × 4 = 1 mA, and the current supply of the booster circuit is considered even if the variation in the writing characteristics of the cell transistors is taken into consideration. Since the capacity may be about 2 mA, the booster circuit can be built in the nonvolatile semiconductor memory.

[0004]

However, the divisional writing technique of the first conventional example has a new problem that the writing time increases. If 16 bits can be collectively written, for example, if the writing is completed in 2 μS, the writing time of 2 μS × 4 = 8 μS is required in the divided writing of 4 bits.

A second conventional technique for reducing the writing time is disclosed in Japanese Patent Laid-Open No. 11-260084. Figure 11
FIG. 3A is a block diagram of a nonvolatile semiconductor memory using the second conventional technique. In FIG. 11A, the read system is omitted and only the write system is shown for the sake of simplicity. A memory cell in the memory cell array is selected by an address signal (not shown) input to the X decoder and the Y decoder in the flash memory unit 51. At the time of writing, the Vpp power supply current Ipp supplied from the booster circuit 52 to the flash memory unit 51 is measured by the Ipp measuring circuit 53. The measured value of the Ipp measuring circuit 53 rapidly increases with the start of writing and then decreases with an increase in the threshold voltage of the memory cell. When the measured value becomes smaller than the current value preset in the judgment current value setting circuit 56, the pulse stop judgment circuit 55 detects this and stops the writing operation of the writing circuit 54. In the second conventional technique, Ipp
Since the change in the threshold voltage is indirectly measured by the change in the current value and the writing is completed by detecting that the memory cell has been written to a practical threshold voltage, the writing time is not constant. Instead, writing is performed in the required minimum writing time for each selected memory cell.

The second prior art is effective in shortening the write time, but is not improved in that the booster circuit has to supply a large Vpp power supply current Ipp. By combining the second conventional technology with the first conventional technology, it is possible to reduce the current supply load of the booster circuit and shorten the writing time. That is, as shown in FIG. 11B, in the case where divided writing is performed in units of 4 bits, assuming that an average writing time of 4 bits simultaneous writing TA = 1 μS, a writing time of 1 word (16 bits) is obtained. The speed can be increased to 4 μS, and the current supply capacity of the booster circuit can be reduced to 2 mA.

As a third conventional technique for improving the writing time and the burden of supplying current to the booster circuit, Japanese Patent Laid-Open No. 11-17617 has been proposed.
There is a technique described in Japanese Patent No. FIG. 12 is a block diagram of the third conventional technique. In the 16-bit input / output flash memory section 61, the voltage is boosted from the booster circuit 62 through the write circuits 63-0 to 63-15 provided for each input / output bit.
A pp power source flow Ipp is supplied. Write time control circuit 6
In No. 4, the write circuits 63-0 to 63-15 are sequentially put in the write operation state while being shifted by a constant time. Figure 12 (b)
FIG. 9 is a diagram showing a current in writing according to a third conventional technique. Ip0 to Ip1 represent the currents of the respective write circuits, and Ipp represents the Vpp power supply current of these sums.
Since the writing of each writing circuit is carried out by deviating by a fixed time, the peak value of Ipp is reduced, so that the current supply capability of the booster circuit can be reduced. For example, if the writing time per bit is 2 μS and writing is performed by shifting by 0.2 μS for each bit, the writing time will be 0.2 μS × 15 + 2 μS = 5 μS for 16 bits. The current supply capability of the booster circuit may be about 4 times the average characteristic (250 μA) such as Ip0 and Ip1 in consideration of the characteristic variation of the memory cells such as Ip5 and Ip7.
It becomes A.

As described above, by applying the first conventional technique and the second conventional technique in combination to the nonvolatile semiconductor memory, or by applying the third conventional technique to the nonvolatile semiconductor memory. It is possible to obtain a non-volatile semiconductor memory in which the current supply load of the booster circuit is small and the writing time is shortened.

However, it is inevitable that the number of input / output bits of the non-volatile semiconductor memory will increase as the word of the instruction of the microcomputer increases from 16 bits to 32 bits to 64 bits. It is necessary to further reduce the load of current supply of the booster circuit to a level that can be realized by combining the conventional technology of No. 1 and the second conventional technology or by the third conventional technology.

An object of the present invention is to combine the first prior art with the second prior art and maintain the practical writing time almost equal to that of the third prior art while maintaining the first and second prior arts. The load of the current supply of the booster circuit can be further reduced as compared with the level realized by the third prior art in combination with the second prior art, and the increase of the occupied area of the booster circuit is suppressed even when the number of bits is increased. It is to provide a nonvolatile semiconductor memory capable of performing the above.

[0011]

A non-volatile semiconductor memory according to the present invention is a non-volatile semiconductor memory having a booster circuit for generating a program power supply voltage and a non-volatile memory section having a plurality of input / output bit configurations. The program power supply current supplied to the non-volatile memory unit is monitored, and when the program power supply current is less than a preset reference current value, the write operation of the write circuit provided corresponding to each of the plurality of input / output bits is performed. A means is provided for sequentially starting at predetermined time intervals and for stopping the start of the write circuit corresponding to the next bit until the program power supply current decreases below the reference current value again when the program power supply current is greater than or equal to the reference current value. Consists of

The nonvolatile semiconductor memory of the present invention is
The booster circuit that generates the program power supply voltage and the input / output are n
In a non-volatile semiconductor memory having a non-volatile memory unit of (n ≧ 4) bit configuration, a program signal power supply current supplied from the booster circuit is monitored, and a detection signal is detected during a period equal to or more than a preset reference current value. Of a current detection circuit for outputting a write start signal to start write control, and when the detection signal is an inactive level, a write signal corresponding to each of the n input / output bits is predetermined. And a write control circuit for sequentially outputting as an active level at time intervals of, and stopping the output of the next write signal when the detection signal is at an active level, and corresponding to n input / output bits. And n write circuits that start the write operation when the active level of the write signal is input.

Further, the write control circuit receives a write start signal to start write control, and a predetermined subtraction value m (m ≧ 2) among write signals corresponding to n input / output bits. (Integral number of) write signals are output as active levels at the same time when write control is started, and the detection signals of write signals corresponding to the remaining (nm) input / output bits are inactive levels. When, the write signal corresponding to each of the input / output bits is sequentially output as the active level at a predetermined time interval, and when the detection signal is at the active level, the output of the next write signal is stopped. Good.

Furthermore, the write control circuit receives the write start signal to start write control, and when the detection signal is at the inactive level, the write signal corresponding to each of the n input / output bits is output. Among them, only the write signal corresponding to the bit whose input data is the data value for writing the memory cell in the high threshold voltage state is selected and sequentially output as the active level at a time interval of a predetermined time or more, and the detection signal becomes active. When the level is reached, the output of the next write signal may be stopped.

Furthermore, a write circuit is provided corresponding to n input / output bits, and a predetermined number of simultaneous write bits p (p
(Integer of ≧ 2) or less, and the write control circuit is configured to start the write operation when the active level of the write signal corresponding to each group is input. To start the write control, and when the detection signal is at the inactive level for the plurality of write circuit groups, the write signals corresponding to the plurality of write circuit groups are sequentially output at predetermined time intervals. The output may be performed as an active level, and the output of the next write signal may be stopped when the detection signal is at the active level.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of a nonvolatile semiconductor memory of the present invention. The nonvolatile semiconductor memory includes a flash memory unit 1 having 16-bit input / output bits, a booster circuit 2, a current detection circuit 3,
It has the same number of write circuits 4-0 to 4-15 as the number of input / output bits, a write control circuit, a timer 6, and an oscillator 7.
In FIG. 1, the read system is omitted and only the write system is shown for the sake of simplicity.

The flash memory unit 1 includes lower memory cell arrays B0 to B0 corresponding to 16 input / output bits.
A memory cell array including B15, a Y decoder and Y selector for selecting a digit line, and an X decoder for selecting a word line are provided. One word line and a total of 16 digit lines, one in each lower memory cell array, are selected by the address signal, and 16 memories connected to the selected word line and the selected digit line are selected. A cell is selected in the memory cell array.

Each of the write circuits 4-0 to 4-15 has
At the time of writing, the corresponding input data D [0] to D [1
[5] is a predetermined value "1", the Vpp power supply voltage is supplied to the selected digit line of each lower memory cell array of the flash memory unit 1.

The booster circuit 2 generates a Vpp power supply voltage at the time of writing, and the flash memory section 1 and the write circuits 4-0 to 4-0.
4-15.

The current detection circuit 3 has a voltage V supplied by the booster circuit.
The current value of the pp power supply current Ipp is monitored, and when it exceeds the reference current value Iref, this is detected and the detection signal DTCT is output as an active level.

The write control circuit 5 detects the active level of the write start signal WST in synchronization with the clock signal CLK to start the write control, and when the detection signal DTCT is at the inactive level, 16 input / output bits. The write signals WT [15] to WT [0] corresponding to are sequentially output as active levels at predetermined time intervals, and the detection signal DTCT is output.
Is at an active level, the output of the write signal is stopped and the time-up signal TM [i] (i is 0, 1 ... 15)
When the active level is input, the corresponding write signal WT [i] is set to the inactive level.

The timer 6 has write signals WT [15] to WT.
An internal timer circuit corresponding to each [0] is provided, and when the active level of the write signal WT [i] is input, the corresponding internal timer circuit starts counting the clock signal CLK and outputs the time-up signal TM [i]. The time-up signal TM [i] is output as an inactive level when the counting of a predetermined number of clocks is completed. The oscillator 7 has a clock signal CL
Generate and output K.

FIG. 2 is a diagram showing an internal block of the write control circuit 5 in the first embodiment. Write control circuit 5
Is a count pulse generation circuit 11, a counter 12,
It has a write signal generation circuit 13.

The count pulse generation circuit 11 outputs the count pulse CP synchronized with the clock signal CLK when the detection signal DTCT from the current detection circuit 1 is at the inactive level of low level, and the detection signal DTCT is at the active level. The generation of the count pulse CP is stopped during the high level period. The counter 12 sets the initial value of the count value CNT when the first count pulse is input after the write start signal WST is input, and the counter 12 counts down by 1 each time the count pulse CP is input and outputs the count value CNT. . The write signal generation circuit 13 outputs the write signal WT [i] corresponding to the count value CNT (i) as a high level which is an active level every time the count value CNT is input, and the time-up signal from the timer 6 is output. When TM [i] becomes the active level of high level, the write signal WT [i] is set to the inactive level of low level.

In the present invention, the current detection circuit 3 monitors the Vpp power supply current Ipp flowing from the booster circuit 2 to the write circuits 4-0 to 4-15 and the flash memory unit 1 to obtain Vpp.
The reference current value I in which the power supply current Ipp is preset
When it becomes equal to or higher than ref, the detection signal DTCT is set to a high level which is an active level.

When the detection signal DTCT is at a low level of inactive level (that is, Vpp power supply current Ip
When p is less than the reference current Iref), the count pulse generation circuit 11 in the write control circuit 5 generates the count pulse CP synchronized with the clock signal CLK and outputs the count pulse CP to the counter 12, and the counter 12 outputs the count pulse CP. Each time CP is input, the count value CNT is decremented by 1 to update the count value CNT and output to the write signal generation circuit 13. The write signal generation circuit 13 outputs the write signal WT [i] corresponding to the input count value CNT (i) to the write circuit 4-i as an active high level. For example, when the count value CNT (15) is input, the write signal WT [15] becomes high level. Next, when the count value CNT (14) is input, the write signal WT [1
4] becomes high level. When the write signal WT [i] changes to the high level, the write circuit 4-i starts the write operation.

In the timer 6, when the write signal WT [i] becomes high level, the corresponding internal timer circuit starts measuring time, and when a predetermined write time (for example, 2 μS) elapses, the corresponding time up. The signal TM [i] is output to the write signal generation circuit 16 as an active high level. The write signal generation circuit 13 outputs the time-up signal T
M [i] is input and the corresponding write signal WT [i] is changed to the inactive low level. When the write signal WT [i] changes to the low level, the write circuit 4-
i completes the write operation.

When the detection signal DTCT is at the high level of the active level (that is, when the Vpp power supply current Ipp is greater than or equal to the reference current Iref), the count pulse generation circuit 11 waits until the detection signal DTCT becomes low level again. Meanwhile, the generation of the count pulse CP is stopped. Counter 1 by stopping generation of count pulse CP
2 also stops the counting operation, and the write signal generation circuit 13 stops generating the next write signal. For example, the write signal WT
When Vpp power supply current Ipp increases above the reference current value when [12] becomes high level and the write operation of the write circuit 4-12 is started, the detection signal DTCT becomes high level and the count pulse is generated. Since the generation of CP stops and the counter 12 stops counting down at the count value CNT (12), the write signal generation circuit 13 temporarily stops the generation of write signals after the write signal WT [11]. Since the write circuit is not newly operated due to the stop of the generation of the write signal, the Vpp power supply current Ipp decreases and Vp
When the p power supply current Ipp becomes less than the reference current value Iref, the detection signal DTCT becomes low level and the generation of the count pulse is restarted, and the write signal generation circuit 13 generates the write signals after the write signal WT [11]. To resume.

FIG. 3 is an operation timing chart of the first embodiment. The operation of the first embodiment will be described with reference to FIGS. 1, 2 and 3.

In the flash memory unit 1, first, a memory cell in the memory cell array is selected by an address signal through an X decoder and a Y selector. 16 memory cells are selected, one for each lower memory cell array, corresponding to each of the 16 input / output bits.
Preparations are made to supply a potential to the terminals of the selected memory cell.

Next, Vpp boosted by the booster circuit 2
The power supply voltage is passed through the current detection circuit 3 to write circuits 4-0 to 4-4.
The word voltage Vg is supplied to the word line which is supplied to -15 and selected by the X decoder. At this point, the Vpp power supply current Ipp flowing through the current detection circuit 1 is small, so the detection signal DTCT is output as a low level. Since the detection signal DTCT is at the low level, the count pulse generation circuit 11 outputs the count pulse CP synchronized with CLK to the counter 12. Write control circuit 5
When the first count pulse CP generated after the write start signal WST is input to the counter 12, the count value CNT (15) is set as an initial value in the counter 12 and the count value CNT (15) is written. The signal is output to the signal generation circuit 13. The write signal generation circuit 13 outputs the write signal WT corresponding to the input count value CNT (15).
[15] is output to the write circuit 4-15 to start the write operation. At the same time, the write signal generation circuit 13 causes the write signal WT
[15] is sent to the timer 6, and the timer 6 starts measuring the writing time, and the time-up signal TM [15] becomes low level.

Similarly, the count pulse generation circuit 11
When the second count pulse CP is output from the counter 12, the counter 12 counts down by 1 and the count value CNT
(14), and the write signal generation circuit 13 outputs the write signal WT [1 corresponding to the input count value CNT (14).
4] to the writing circuit 4-14 to start the writing operation. At the same time, the write signal generation circuit 13 causes the write signal WT [1
4] to the timer 6, and the timer 6 starts measuring the writing time and the time-up signal TM [14] becomes low level. Similarly, when the third count pulse CP is output from the count pulse generation circuit 11, the counter 12 outputs the count value CNT (13) and the write signal generation circuit 13 outputs the write signal WT [13]. Write circuit 4-1
3 starts the writing operation, the timer 6 starts measuring the writing time, and the time-up signal TM [13] becomes low level.

As long as the Vpp power supply current Ipp is less than the reference current value, the count pulse is output by the count pulse generation circuit 11 at a constant cycle in synchronization with the clock signal CLK, and thus the write signal WT [1
5], WT [14], WT [13] are sequentially output as high levels at regular time intervals.

Next, the count pulse generation circuits 11 to 4
When the th count pulse CP is output, the counter 1
2 becomes the count value CNT (12), and the write signal generation circuit 13 outputs the write signal WT [12] corresponding to the input count value CNT (12) to the write circuit 4-12 to perform the write operation. To start. At the same time, the write signal generation circuit 13 sends the write signal WT [12] to the timer 6, and the timer 6 starts measuring the write time and the time-up signal TM [12] is started.
Becomes low level. At this time, since the write circuit 4-12 starts the write operation, the Vpp power supply current Ipp becomes equal to or higher than the reference current value Iref, so the detection signal D
TCT becomes high level, and count pulse generation circuit 1
1 stops the generation of the count pulse CP. While the Vpp power supply current Ipp is equal to or higher than the reference current value Iref, the count pulse generation circuit 11 continues to stop generating the count pulse CP.

When the Vpp power supply current Ipp decreases below the reference current value Iref and the detection signal DTCT becomes low level, the count pulse generation circuit 11 outputs the fifth count pulse CP and the counter 12 outputs the count value CNT (11 ), The write signal generation circuit 13 outputs the write signal WT [11] corresponding to the input count value CNT (11) to the write circuit 4-11 to start the write operation. At the same time, the write signal generation circuit 13 causes the write signal W
T [11] is sent to the timer 6, and the timer 6 starts measuring the writing time, and the time-up signal TM [11] becomes low level. The operation after the generation of the sixth count pulse is the same, so its explanation is omitted.

When the high level of the write signal WT [15] is input, the timer 6 starts counting the time of the corresponding internal counting circuit and outputs the time-up signal TM [15] as a low level for a predetermined write time. When Twi has passed, the time-up signal TM [15] is output as a high level. The write signal generation circuit 13 receives the write signal W when the high level of the time-up signal TM [15] is input.
Write circuit 4-15 by changing T [15] to low level
The write operation of is ended. Write signal WT [0] to WT
[14] and time-up signals TM [0] to WT [14]
Is also the same.

FIG. 4 is a diagram for explaining the effect of the first embodiment, and is a diagram corresponding to FIG. 12 (b) showing the effect of the third prior art of FIG. 12 (a). Ip0, IP1 ...
IP15 are write circuits 4-0, 4-1 ... 4-15, respectively.
Indicates the current flowing through. In FIG. 4 and FIG. 12B, the current characteristics of the memory cells are the same. Figure 12 (b)
Then, from time T6 to time T9, the Vpp power supply current Ipp is at a level that continuously increases, so the booster circuit is required to have the ability to continuously supply this level of Ipp, and if the current supply ability is not satisfied, The Vpp power supply voltage decreases and it becomes impossible to write the cell transistor to a sufficiently high threshold voltage.

On the other hand, in FIG. 4, Vpp power supply current I
When pp exceeds the reference current value Iref, the start of the write circuit corresponding to the next bit is stopped, so Ipp
Is temporarily increased and the Vpp power supply voltage is lowered, Vpp is restored to the normal voltage when the writing circuit of the next bit is started, and therefore the writing failure of the cell transistor is prevented. It As in the case of the third prior art, assuming that the 1-bit writing time is 2 μS and the cycle of the count pulse CP is 0.2 μS, the 1-word (16-bit) writing time in the case of FIG. 2 μS x 17 + 2
μS = 5.4 μS. The current supply capacity of the booster circuit is
Even if the characteristic variations of the memory cells such as Ip5 and Ip7 are taken into consideration, the average characteristics such as Ip0 and Ip1 (250 μ
It is sufficient to make it about 3 times with a margin of about 2 times that of A), which is about 750 μA. Reference current value Iref
Is preferably set to a value between the average Ipp (500 μA in the example) and the current supply capacity of the booster circuit (750 μA in the example).

As mentioned above, the first prior art and the second prior art
In the case of combining with the prior art of 16 bits, the average writing time per 4 bits can be shortened to 1 μS and the 16-bit writing time becomes 4 μS.
Although writing can be performed in a short time, the current supply capacity of the booster circuit is required to be about 2 mA, which is 2.7 times that of the present embodiment.
In the third conventional technique, the 16-bit writing time is 5 μS, and the writing can be performed in 8% shorter time than the present embodiment, but the current supply capacity of the booster circuit is required to be about 1 mA. 33% larger. As described above, in the nonvolatile semiconductor memory to which this embodiment is applied, the first conventional technique and the second conventional technique are used.
Than the level that can be realized by the combination of the first conventional technique and the second conventional technique or the third conventional technique while maintaining the practical writing time close to the combination of the conventional technique of No. 1 and the third conventional technique. Further, the load of current supply of the booster circuit can be reduced.

Next, another embodiment of the nonvolatile semiconductor memory of the present invention will be described. FIG. 5 is a diagram showing an internal block of the write control circuit in the second embodiment.
The second embodiment differs from the first embodiment in that a plurality of write circuits are simultaneously started at the start of writing, and is configured by replacing the write control circuit 5 of FIG. 1 with a write control circuit 5a. . The write control circuit 5a detects the active level of the write start signal WST in synchronization with the clock signal CLK, starts write control, and writes the write signals WT [15] to WT [15] -corresponding to 16 input / output bits. A predetermined number of write signals WT [1] of WT [0] with a subtraction value m (m ≧ 2).
5] to WT [15-m + 1] are output as active levels at the same time when the write control is started, and the remaining write signals WT [15-m] to WT [0] are detected by the detection signal D.
When the TCT is at the inactive level, it is sequentially output as an active level at predetermined time intervals, and the detection signal DT is output.
When CT is at the active level, the output of the write signal is stopped, and when the active level of the time-up signal TM [i] is input, the corresponding write signal WT [i] is set to the inactive level.

Referring to FIG. 5, the write control circuit 5a of the second embodiment includes a count pulse generation circuit 11, a counter 12, a count value shift circuit 21, a start signal generation circuit 22, and a write signal. And a generating circuit 23.

The count pulse generation circuit 11 outputs the count pulse CP synchronized with the clock signal CLK when the detection signal DTCT from the current detection circuit 1 is at the inactive level of low level, and the detection signal DTCT is at the active level. The generation of the count pulse CP is stopped during the high level period. The counter 12 receives the write start signal WST and then outputs the first count pulse C.
When P is input, the initial value of the count value CNT is set,
Every time the count pulse CP is input, it counts down by 1 and outputs the count value CNT. The count value shift circuit 21 inputs the count value CNT, subtracts a predetermined subtraction value m from the count value CNT, and outputs it as a shifted count value CNTS. When the write start signal WST is input, the start signal generation circuit 22 simultaneously outputs as many write signals as the subtractive value m counted from the initial value set in the counter 12 as a high level of the active level, and responds. When the time-up signal becomes the active level, that is, the high level, the write signals corresponding to the subtracted value are simultaneously set to the low level. Write signal generation circuit 23
Is a write signal WT corresponding to the shifted count value CNTS (i) every time the shifted count value CNTS is input.
[I] is output as a high level which is an active level, and when the time-up signal TM [i] from the timer 6 becomes a high level of an active level, the write signal WT [i]
To the inactive low level.

FIG. 6 is an operation timing chart of the nonvolatile semiconductor memory of the second embodiment configured with the subtraction value m = 2. The operation of the second embodiment will be described below with reference to FIGS. 1, 5 and 6.

When the write start signal WST is input, the write signals WT [15] and WT [14] corresponding to the subtracted value (2) from the initial value (15) of the counter 12 are simultaneously output as a high level. , And the write operation of the write circuits 4-15 and 4-14 is started. The timer 6 writes the write signals WT [15], WT
When the high level of [14] is input, clocking is started and the time-up signals TM [15] and TM [14] are output as low levels. Next, the count pulse CP is output from the count pulse generation circuit 11, and the counter 1
The count value CNT (15) is actually set to 2 and output, and the count value shift circuit 21 subtracts 2 to output the shifted count value CNTS (13).
The write control circuit 23 uses the shifted count value CNTS (1
Enter 3) to enter the shifted count value CNTS (13)
The write signal WT [13] corresponding to is output as a high level, and the write operation of the write circuit 4-13 is started. When the high level of the write signal WT [13] is input, the timer 6 starts clocking and outputs the time-up signal TM [13] as a low level.

The subsequent operation is similar to that of the first embodiment,
When the Vpp power supply current Ipp increases above the reference current Iref, the detection signal DTCT becomes high level, and the count pulse generation circuit 11 stops generating the count pulse CP until the detection signal DTCT becomes low level again. When the start signal generation circuit 22 inputs the high level of the time-up signals TM [15] and TM [14] from the timer 6, the start signal generation circuit 22 simultaneously sets the write signals WT [15] and WT [14] to the low level, and the write circuit The write operation of 4-15 and 4-14 is completed. When the high level of the time-up signal TM [i] from the timer 6 is input, the write control circuit 23 sets the write signal WT [i] to the low level and ends the write operation of the write circuit 4-i. .

In the present embodiment, since the writing circuits of the reduced value are started at the same time when writing is started, there is a new effect that the writing time can be shortened as compared with the first embodiment.

FIG. 7 is a block diagram of a third embodiment of the nonvolatile semiconductor memory of the present invention. In the third embodiment,
FIG. 1 is that only the write circuit corresponding to the input / output bit for which the input data is “1” and the data “1” needs to be written is operated.
Unlike the first embodiment, the write control circuit 5b in the first embodiment is replaced with the write control circuit 5b which also inputs the input data D [15] to D [0]. The write control circuit 5b synchronizes with the clock signal CLK to write start signal W.
Detects the active level of ST and starts write control,
1 when the detection signal DTCT is at the inactive level
Write signal WT [1 corresponding to 6-bit input / output bits
5] to WT [0], only the write signal WT [k] corresponding to the bit whose input data is the data “1” is sequentially output as the active level at a time interval of a predetermined time or longer, and the detection signal DTCT is output. When the active level of the time-up signal TM [k] is input, the corresponding write signal WT [k] is set to the inactive level.

FIG. 8 shows a write control circuit 5b of the third embodiment.
It is a figure which shows the internal block of. The write control circuit 5b is
A count pulse generation circuit 31, a counter 12, a write count value determination circuit 32, and a write control circuit 13 are provided. The count pulse generation circuit 31 receives the clock signal CLK when the detection signal DTCT from the current detection circuit 1 is a low level which is an inactive level.
When the next pulse generation request signal NPR is input from the write count value determination circuit 32 as an active level, the count pulse CP being output is interrupted to a low level, and then a new clock signal is generated. A count pulse CP synchronized with CLK is generated and output. Further, the count pulse generation circuit 31 stops the generation of the count pulse CP during the high level period when the detection signal DTCT is the active level. Counter 1
2, when the first count pulse CP is input after the write start signal WST is input, the initial value of the count value CNT is set, and each time the count pulse CP is input, it counts down by 1 and outputs the count value CNT. . The write count value determination circuit 32 uses the input data D [1
5] to D [0] and the count value CNT are input, and when the count value CNT is the count value corresponding to the input / output bit of the data “0” which is not written, the next pulse generation request signal NW Is output as an active level to the count pulse generation circuit 31. Write count value determination circuit 32
When the count value CNT is the count value corresponding to the input / output bit of the data “1” to be written, the next pulse generation request signal NW is set to the inactive level and the count value CNT is set to the write count value. It is output to the write signal generation circuit 13 as the CNTC. Write signal generation circuit 1
3 outputs the write signal WT [k] corresponding to the write count value CNTC (k) as a high level which is an active level every time the write count value CNTC is input, and the time-up signal TM from the timer 6 is output. When [k] becomes the active level of high level, the write signal WT [k] is set to the inactive level of low level.

The operation of the third embodiment will be described. Input data D [15] to D [0] are input to the write count value determination circuit 32 in the write control circuit 5b. Next, the count value CNT sequentially counted by the counter 12 is input to the write count value determination circuit 32. The write count value determination circuit 32 compares the input count value CNT with the input data D [15] to D [0] to determine the count value C.
If NT is a value corresponding to the input / output bit whose data is "1", it is output to the write signal generation circuit 13 as the write count value CNTC. The write signal generation circuit 13 outputs the write signal WT corresponding to the input write count value CNTC (k).
Output [k].

If the count value CNT input to the write count value determination circuit 32 is a value corresponding to the input / output bit whose data is "0", the write count value determination circuit 32 determines the next pulse generation request signal NPR. Is sent to the count pulse generation circuit 31 as an active level, and the count pulse generation circuit 31 interrupts the output count pulse and once returns it to the low level, then newly generates the count pulse CP and outputs it to the counter 12. Since the counter 12 receives the count pulse CP and counts down, the count value CN input to the write count value determination circuit 32 is counted.
When T is a value corresponding to the input / output bit whose data is “0”, the counter 12 is synchronized with the next clock immediately without waiting for the original count pulse generation timing.
Will count down. As a result, the present embodiment has a new effect that the writing time can be further shortened as compared with the first and second embodiments. Also in this embodiment, the Vpp power supply current Ipp is equal to the reference current I.
When it is increased to more than ref, the detection signal DTCT becomes high level, and the count pulse generation circuit 11 detects the detection signal DTC.
Count pulse C until T becomes low level again
Stopping the generation of P is the same as in the first and second embodiments.

FIG. 9 is a block diagram of the nonvolatile semiconductor memory according to the fourth embodiment of the present invention. 1 in the fourth embodiment
Unlike the first embodiment in that a plurality of (two in FIG. 9) write circuits are simultaneously started by one write signal, the write control circuit 5 of the first embodiment is replaced with a write control circuit 5c. Consists of Write control circuit 5c detects the active level of write start signal WST in synchronization with clock signal CLK to start write control, and the write circuit corresponding to 16 input / output bits is divided. The detection signal D is applied to a plurality of write circuit groups each including a write circuit with a predetermined number of simultaneous write bits p (an integer of p ≧ 2, p = 2 in FIG. 9) or less.
When TCT is at the inactive level, write signals WT [14-15] to WT [0 corresponding to the write circuit group.
−1] is sequentially output as an active level at predetermined time intervals, and when the detection signal DTCT is at an active level, the output of the write signal is stopped and the time-up signal TM [i
When the active level of -j] is input, the corresponding write signal WT [i-j] is set to the inactive level.

The internal block of the write control circuit 5c is shown in FIG.
The internal block of the write control circuit 5 of the first embodiment can be configured almost the same, and the initial value of the count value of the counter 12 is set to 1
5 to 7, the write signal generated by the write signal generation circuit 13 is set to eight write signals WT [14-15] to WT [0-1], and the time-up signal input from the timer 6 is the write signal. T to correspond to WT [14-15] to WT [0-1]
This can be realized by changing the number of lines from M [14-15] to TM [0-1].

In the operation of this embodiment, the write signal WT [i-
Every time j] changes to a high level, the two write circuits 4-i, 4-j included in the write circuit group corresponding to the j] are simultaneously started, which is different from the first embodiment. Other operations are similar to those of the first embodiment, and when the Vpp power supply current Ipp increases above the reference current Iref, the detection signal DTCT is generated.
Becomes high level and the count pulse generation circuit 11 stops generating the count pulse CP until the detection signal DTCT becomes low level again.

In this embodiment, since p write circuits are simultaneously started to perform writing, a nonvolatile semiconductor memory is provided with a booster circuit capable of supplying Vpp power supply current Ipp necessary for p simultaneous write. When mounted, the writing time can be shortened as compared with the first embodiment and the second embodiment.

In the above description, the input data D
Although [15] to D [0] are described as being external input data, they may be internally generated input data such as code data in a non-volatile semiconductor memory equipped with an ECC (error correction code). .

In the above description, the nonvolatile semiconductor device has been described as having 16-bit input / output bits. However, the present invention is not limited to this, and 4-bit, 8-bit, 32-bit, or the like. Input / output of n (integer of n ≧ 4) bits is generally applicable because it may have a power of 2 input / output bits, and in addition to this, a configuration having extra parity bits and ECC code bits is also applicable. It is applicable to a semiconductor circuit having a bit.

Further, the state in which the threshold voltage of the cell transistor is increased by writing in the memory cell is set to the data "1" holding state, and the erase operation is performed and the threshold voltage of the cell transistor is lowered. Although the state has been described as the holding state of the data “0”, these are definitions for convenience, and the correspondence relationship between the high and low of the threshold voltage and the data “1” and “0” may be reversed.

The write start signal WST has been described as a signal input from the outside, but it may be a signal generated in the nonvolatile semiconductor memory based on a write command input from the outside. .

Further, the write control circuits 5, 5a, 5b, 5c
The counter 12 therein has been described as a down counter that counts down each time the count pulse CP is input, but instead, it may be an up counter that counts up each time the count pulse CP is input. In this case, since the initial value of the counter 12 is set to 0, the write signal WT [0] first becomes the active level, and WT [1] and subsequent ones sequentially become the active level each time counting up.

[0060]

As described above, in the nonvolatile semiconductor memory to which the present invention is applied, the current detection circuit constantly monitors the Vpp power supply current Ipp supplied from the booster circuit at the time of writing, and Ipp is the reference current Iref. When it increases above, the detection signal is sent to the write control circuit as an active level, and the write control circuit operates so as to stop the generation of a new write signal until the detection signal returns to the inactive level. As a result, the first conventional technology and the second conventional technology are maintained while maintaining a practical writing time which is almost the same as the combination of the first conventional technology and the second conventional technology or the third conventional technology. The load of current supply to the booster circuit can be further reduced as compared with the level that can be realized by the combination or the third conventional technique. Therefore, in the nonvolatile semiconductor memory to which the present invention is applied, even when the number of input / output bits is further increased, it is possible to suppress an increase in the area occupied by the booster circuit, and it is possible to reduce the cost with a small chip area.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a diagram showing an internal block of a write control circuit in the first embodiment.

FIG. 3 is an operation timing chart of the first embodiment.

FIG. 4 is a diagram illustrating an effect of the first embodiment.

FIG. 5 is a diagram showing an internal block of a write control circuit according to a second embodiment.

FIG. 6 is an operation timing chart of the second embodiment.

FIG. 7 is a block diagram of a third embodiment.

FIG. 8 is a diagram showing an internal block of a write control circuit 5 according to a third embodiment.

FIG. 9 is a block diagram of a fourth embodiment.

FIG. 10A is a diagram showing a time change of the drain current of the cell transistor and a time change of the threshold voltage of the cell transistor at the time of writing “1” data,
(B) is a circuit diagram of an example of a booster circuit.

11A is a block diagram of a nonvolatile semiconductor memory using a second conventional technique, and FIG. 11B is a Vpp in the case where the second conventional technique and the first conventional technique are combined.
It is a figure which shows a power supply current.

FIG. 12A is a block diagram of a third conventional technique, and FIG. 12B is a diagram showing a current in writing by the third conventional technique.

[Explanation of symbols]

1 Flash memory section 2 booster circuit 3 Current detection circuit 4 Writing circuit 5, 5a, 5b, 5c Write control circuit 6 timer 7 oscillator 11,31 Count pulse generation circuit 12 counter 13, 23 Write signal generation circuit 21 Count value shift circuit 22 Start-up signal generation circuit 32 Write Count Value Discrimination Circuit DTCT detection signal WT write signal

Claims (8)

[Claims] 1. A non-volatile semiconductor memory having a booster circuit for generating a program power supply voltage and a non-volatile memory unit having a plurality of input / output bits, wherein the booster circuit monitors a program power supply current supplied to the non-volatile memory unit. When the program power supply current is less than the preset reference current value, the write operation of the write circuit provided corresponding to each of the plurality of input / output bits is sequentially started at a predetermined time interval, and the program power supply current is A non-volatile semiconductor memory, comprising means for stopping the start of the write circuit corresponding to the next bit during the period until the program power supply current decreases below the reference current value again when the reference current value is exceeded. 2. A non-volatile semiconductor memory having a booster circuit for generating a program power supply voltage and a non-volatile memory unit having n (n ≧ 4 integer) bit inputs and outputs, the program power supply current supplied by the booster circuit. Current detection circuit that outputs a detection signal as an active level during a period when the current is higher than a preset reference current value, and a write start signal is input to start write control and the detection signal is an inactive level. Write control for sequentially outputting the write signal corresponding to each of the n input / output bits at a predetermined time interval as the active level, and stopping the output of the next write signal when the detection signal is at the active level. A circuit and a write operation when the active level of the write signal corresponding to each of the n input / output bits is input. A non-volatile semiconductor memory, comprising n write circuits for starting operation. 3. The count pulse generation circuit, wherein the write control circuit outputs a count pulse synchronized with a clock signal when the detection signal is at an inactive level, and stops the generation of the count pulse when the detection signal is at an active level. And (n-1) is set as the initial value of the count value at the first count pulse after the write start signal is input, and the counter counts down by 1 each time the count pulse is input and outputs the count value. 3. The nonvolatile semiconductor memory according to claim 2, further comprising a write signal generation circuit that outputs a write signal corresponding to the count value as an active level each time the count value is input. 4. A non-volatile semiconductor memory having a booster circuit for generating a program power supply voltage and a non-volatile memory section having n (n ≧ 4 integer) bit inputs / outputs, the program power supply current supplied by the booster circuit. And a current detection circuit that outputs a detection signal as an active level during the period when it is equal to or more than a preset reference current value, and a write start signal is input to start write control to set n input / output bits. Of the corresponding write signals, a predetermined number of write signals m (m ≧ 2 integers) of write signals are output as the active level at the same time when the write control is started, and the remaining (n−m) write signals are output. Regarding the write signals corresponding to the input / output bits, when the detection signal is at the inactive level, the write signals corresponding to the input / output bits are sequentially activated at predetermined time intervals. And a write control circuit that outputs the next write signal when the detection signal is at the active level, and a write control circuit provided corresponding to n input / output bits. A non-volatile semiconductor memory, comprising: n write circuits that start a write operation when an active level is input. 5. The count pulse generation circuit, wherein the write control circuit outputs a count pulse synchronized with a clock signal when the detection signal is at an inactive level, and stops the generation of the count pulse when the detection signal is at an active level. And (n-1) is set as the initial value of the count value at the first count pulse after the write start signal is input, and the counter counts down by 1 each time the count pulse is input and outputs the count value. , A predetermined subtraction value m (m
A count value shift circuit for subtracting (> 2) from the count value and outputting it as a shifted count value, and the number of subtractive values m counted from the initial value set in the counter when the write start signal is input. Start signal generating circuit for simultaneously outputting minute write signals as an active level, and a write signal generating circuit for outputting a write signal corresponding to the shifted count value as an active level each time the shifted count value is input The nonvolatile semiconductor memory according to claim 4, further comprising: 6. A non-volatile semiconductor memory having a booster circuit for generating a program power supply voltage and a non-volatile memory unit having an input / output of n (n ≧ 4 integer) bits, wherein a program power supply current supplied by the booster circuit. Current detection circuit that outputs a detection signal as an active level during a period when the current is higher than a preset reference current value, and a write start signal is input to start write control and the detection signal is an inactive level. , The write signal corresponding to each of the n input / output bits is selected for a predetermined time only for the write signal corresponding to the bit whose input data is the data value for writing the memory cell to the high threshold voltage state. Writing is performed in sequence as the active level at the above time intervals, and when the detection signal is at the active level, the output of the next write signal is stopped. A control circuit and n write circuits that are provided corresponding to n input / output bits and start a write operation when an active level of a write signal corresponding to each is input. And a non-volatile semiconductor memory. 7. The write control circuit outputs a count pulse synchronized with the clock signal when the detection signal is at the inactive level, and is outputting the count pulse when the active level of the next pulse generation request signal is input. With a count pulse generation circuit that generates a new count pulse and outputs it, and stops the generation of the count pulse when the detection signal is at the active level, and (n) the first count pulse after the write start signal is input. -1) is set as an initial value of the count value and a counter that counts down by 1 each time a count pulse is input and outputs the count value; and a memory cell having a high threshold value as the input data by inputting the count value Determine whether the data value to be written to the voltage state matches the count value corresponding to the input bit When they match, the next pulse generation request signal is set to an inactive level and the count value is output as a write count value. When the count value does not match the count value corresponding to the bit, the next pulse generation request signal is output as an active level. And a write signal generation circuit that outputs a write signal corresponding to the write count value as an active level each time the write count value is input. Item 6
The nonvolatile semiconductor memory described. 8. A non-volatile semiconductor memory having a booster circuit for generating a program power supply voltage and a non-volatile memory unit having an input / output of n (n ≧ 4 integer) bits, wherein a program power supply current supplied by the booster circuit. Current detection circuit that outputs a detection signal as an active level during a period of time equal to or more than a preset reference current value, and a predetermined number of simultaneous write bits p (n) provided corresponding to n input / output bits. n write circuits that start the write operation when the active level of the write signal corresponding to each group is input into a plurality of groups equal to or smaller than p). To start write control, and when the detection signal is at the inactive level for a plurality of write circuit groups, each of the plurality of write circuit groups is And a write control circuit that sequentially outputs the write signal corresponding to the above as an active level at predetermined time intervals, and stops the output of the next write signal when the detection signal is at the active level. Non-volatile semiconductor memory.