JP2003222510A - Imaging method of wiring pattern - Google Patents

Imaging method of wiring pattern

Info

Publication number
JP2003222510A
JP2003222510A JP2002023068A JP2002023068A JP2003222510A JP 2003222510 A JP2003222510 A JP 2003222510A JP 2002023068 A JP2002023068 A JP 2002023068A JP 2002023068 A JP2002023068 A JP 2002023068A JP 2003222510 A JP2003222510 A JP 2003222510A
Authority
JP
Japan
Prior art keywords
wiring pattern
illumination
image
imaging
outermost
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002023068A
Other languages
Japanese (ja)
Inventor
Mitsusachi Mihashi
光幸 三橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP2002023068A priority Critical patent/JP2003222510A/en
Publication of JP2003222510A publication Critical patent/JP2003222510A/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging method of a wiring pattern capable of acquiring a clear image by removing influence of a bedding internal layer wiring pattern when imaging the outermost-layer wiring pattern of a high-density semiconductor packaging multilayer interconnection board. <P>SOLUTION: An object tape 1 comprising a semiconductor packaging multilayer interconnection board is positioned and fixed by a work fixing mechanism 7, and the outermost-layer wiring pattern of the object tape 1 is imaged by an imaging means comprising a sensor 2, an imaging lens 3, a filter 4 and an illumination 5. In this case, this method is characterized by imaging the outermost-layer wiring pattern of the semiconductor packaging multilayer interconnection board by using the illumination 5 having a wave range below 450 nm which is a low wave range of a transmission spectral sensitivity characteristic and a reflection spectral sensitivity characteristic of an insulating base material comprising a polyimide film or a polyimide resin and an insulating layer, or by using a band-pass filter 4. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は絶縁基材の両面に配
線パターン及び絶縁層が順次形成された半導体パッケー
ジ用多層配線板の最外層の配線パターンの撮像方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for picking up an outermost wiring pattern of a multilayer wiring board for a semiconductor package in which a wiring pattern and an insulating layer are sequentially formed on both sides of an insulating base material.

【0002】[0002]

【従来の技術】一般に電子機器の小型・軽量化を目的と
して使用される半導体パッケージ用多層配線板(キャリ
アテープとも言う)は、ポリイミドフィルムを絶縁基材
として、銅箔を接着剤等でラミネートして導体層を形成
し、導体層をパターニング処理して第1配線パターンを
形成し、さらにポリイミド樹脂からなる絶縁層を形成し
て、サブトラクティブ法やセミアディティブ法により配
線パターンを形成する工程を必要回数繰り返して所望の
半導体パッケージ用多層配線板を形成する。ここで、高
密半導体パッケージ用多層配線板では度配線パターンの
厚さは5〜10μm、最も集積度を有する部分で配線パ
ターンの幅が10μm程度である。
2. Description of the Related Art In general, a multilayer wiring board (also called a carrier tape) for a semiconductor package, which is generally used for the purpose of reducing the size and weight of electronic equipment, has a polyimide film as an insulating base material and a copper foil laminated with an adhesive or the like. To form a conductor layer, patterning the conductor layer to form a first wiring pattern, further forming an insulating layer made of a polyimide resin, and forming a wiring pattern by a subtractive method or a semi-additive method. The desired multilayer wiring board for a semiconductor package is formed by repeating the process. Here, in the multilayer wiring board for a high-density semiconductor package, the thickness of the degree wiring pattern is 5 to 10 μm, and the width of the wiring pattern is about 10 μm in the portion having the highest degree of integration.

【0003】この半導体パッケージ用多層配線板の製造
工程中において、配線パターンの細り(欠け)、断線、
ショート、太り(突起)等の重欠陥が発生する。このた
め従来これら欠陥の有無は導通検査や目視検査によって
判別されてきた。しかし、目視検査は、パターンの微細
化、熟練を要すること、検査員の体調等により検査規格
がばらつく、検査人員の問題、生産数量の増大に対する
対応等の問題がある。そこで、最近ではカメラを使用し
て自動的に欠陥有無を検査する自動検査装置が各種提案
されている。また、上記半導体パッケージ用多層配線板
において最小10μm幅の配線パターン上に存在する各
種欠陥を目視にて検査することは不可能に近く自動検査
が不可欠である。
During the manufacturing process of this multilayer wiring board for a semiconductor package, the wiring pattern is thinned (broken), broken,
Heavy defects such as shorts and fat (protrusions) occur. Therefore, conventionally, the presence or absence of these defects has been discriminated by a continuity inspection or a visual inspection. However, the visual inspection has problems such as a finer pattern, skill required, inspection standard variations due to the physical condition of the inspector, problems of inspection personnel, and correspondence to increase in production quantity. Therefore, recently, various automatic inspection apparatuses have been proposed which automatically inspect the presence or absence of defects by using a camera. Further, in the above-mentioned multilayer wiring board for semiconductor package, it is almost impossible to visually inspect various defects existing on a wiring pattern having a minimum width of 10 μm, and automatic inspection is indispensable.

【0004】一般にカメラを使用して自動的に欠陥の有
無を検査する自動検査装置は、複数台のカメラ(ライン
センサやエリアセンサ等)で同一半導体パッケージ用多
層配線板上の複数の配線パターンを同時、時間差、エリ
ア分割等で撮像し、その画像を認識処理することによっ
てパターン上に存在する細り、断線、ショート、太り等
の欠陥検出を行っている。その認識処理は、CADデー
タや良品サンプルをマスター画像として取り込み、この
マスター画像と検査画像(検査対象パターン画像)とを
比較することにより差異のあった部分を欠陥として判断
している。このときの検査画像は半導体パッケージ用多
層配線板の最外層に形成されたパターンに注目して映し
出されたものであり、下地配線パターンの影響を考慮せ
ずに撮像を行っているのがほとんどである。この理由と
しては、下地配線パターンが存在しない製品であるこ
と、下地配線パターンが存在する製品であっても配線パ
ターンと配線パターンとの間に介在する絶縁基材もしく
は絶縁層の種類、絶縁基材厚もしくは絶縁層厚によって
最外層パターンの画像化に影響を及ぼさないこと、下地
配線パターンが存在し多少影響を及ぼしたとしても画像
化時の閾値調整等で簡単に影響をなくすことができ、最
初から下地配線パターンの写り込み影響を光学的に問題
視する必要がない等が挙げられる。
In general, an automatic inspection apparatus for automatically inspecting for defects using a camera uses a plurality of cameras (line sensors, area sensors, etc.) to form a plurality of wiring patterns on a multilayer wiring board for the same semiconductor package. At the same time, images are picked up by time difference, area division, etc., and the images are subjected to recognition processing to detect defects such as thinning, disconnection, short-circuiting, and thickening existing in the pattern. In the recognition processing, CAD data or a non-defective sample is taken in as a master image, and the difference between the master image and the inspection image (inspection target pattern image) is determined as a defect. The inspection image at this time was displayed by paying attention to the pattern formed on the outermost layer of the semiconductor package multilayer wiring board, and most of the images are taken without considering the influence of the underlying wiring pattern. is there. The reason for this is that the product does not have the underlying wiring pattern, and even if the product has the underlying wiring pattern, the type of insulating base material or insulating layer interposed between the wiring patterns and the insulating base material, the insulating base material The thickness of the outermost layer does not affect the imaging of the outermost layer pattern, and even if there is an underlying wiring pattern and it has some effect, it can be easily eliminated by adjusting the threshold value during imaging. Therefore, it is not necessary to consider the influence of the reflection of the underlying wiring pattern as an optical problem.

【0005】しかし、上記高密度半導体パッケージ用多
層配線板では、配線パターンと配線パターンとの間に介
在するポリイミドフィルム等からなる絶縁層厚が10〜
25μm程度と薄く、最外層パターンの画像化を試みよ
うとした際下地に存在する内層配線パターンが写り込
み、最外層配線パターンのみに着目した鮮明な配線パタ
ーン画像を得ることができないという問題を有する。
However, in the above-mentioned multilayer wiring board for a high-density semiconductor package, the thickness of the insulating layer made of a polyimide film or the like interposed between the wiring patterns is 10 to 10.
The thickness is as thin as about 25 μm, and when an attempt is made to image the outermost layer pattern, the inner layer wiring pattern existing in the base is reflected, and there is a problem that a clear wiring pattern image focusing only on the outermost layer wiring pattern cannot be obtained. .

【0006】また、カメラにより配線パターンを撮像画
像として取り込み、撮像画像を用いて検査を行うために
は、照明条件も重要であり、照明によって欠陥が顕在化
できなければ処理アルゴリズムを高度化しても確実な検
査は不可能である。従って、各検査毎に適正な照明条件
を設定する必要がある。
Further, in order to capture the wiring pattern as a picked-up image by a camera and inspect using the picked-up image, the illumination condition is also important, and even if the processing algorithm is sophisticated if a defect cannot be revealed by the illumination. A reliable test is impossible. Therefore, it is necessary to set appropriate illumination conditions for each inspection.

【0007】[0007]

【発明が解決しようとする課題】本発明は上記問題点に
鑑みなされたものであり、高密度半導体パッケージ用多
層配線板の最外層の配線パターンを撮像する際下地内層
配線パターンの影響を除去して鮮明な画像を得ることが
できる配線パターンの撮像方法を提供することを目的と
する。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and eliminates the influence of the underlying inner layer wiring pattern when imaging the wiring pattern of the outermost layer of a multilayer wiring board for high density semiconductor packages. An object of the present invention is to provide a method for imaging a wiring pattern that can obtain a clear and clear image.

【0008】[0008]

【課題を解決するための手段】本発明に於いて上記問題
を解決するため、請求項1においては、絶縁基材の両面
に配線パターン及び絶縁層が順次形成された半導体パッ
ケージ用多層配線板の最外層の配線パターンを画像とし
て撮像する方法であって、450nm以下の波長域を有
する照明、もしくはバンドパスフィルタを用いた撮像手
段によって、半導体パッケージ用多層配線板の最外層の
配線パターンを撮像することを特徴とする配線パターン
の撮像方法としたものである。
In order to solve the above problems in the present invention, in a first aspect of the present invention, there is provided a multilayer wiring board for a semiconductor package in which a wiring pattern and an insulating layer are sequentially formed on both surfaces of an insulating base material. A method for picking up an image of the wiring pattern of the outermost layer, wherein the wiring pattern of the outermost layer of the multilayer wiring board for a semiconductor package is imaged by illumination having a wavelength range of 450 nm or less, or an image pickup means using a bandpass filter. This is an image pickup method for a wiring pattern.

【0009】また、請求項2においては、請求項1記載
の撮像方法において、高角度反射照明を用いた撮像手段
によって半導体パッケージ用多層配線板の最外層の配線
パターンを撮像することを特徴とする配線パターンの撮
像方法としたものである。
According to a second aspect of the present invention, in the image pickup method according to the first aspect, the wiring pattern of the outermost layer of the multilayer wiring board for a semiconductor package is imaged by the image pickup means using high-angle reflective illumination. This is a method for imaging a wiring pattern.

【0010】さらにまた、請求項3においては、前記絶
縁基材及び前記絶縁層がポリイミドフィルムまたはポリ
イミド樹脂からなることを特徴とする請求項1または2
に記載の配線パターンの撮像方法としたものである。
Furthermore, in claim 3, the insulating base material and the insulating layer are made of a polyimide film or a polyimide resin.
The method for imaging the wiring pattern described in (1) is used.

【0011】本発明の配線パターンの撮像方法は、半導
体パッケージ用多層配線板の絶縁基材及び絶縁層として
ポリイミドフィルムもしくはポリイミド樹脂を用い、ポ
リイミドフィルムもしくはポリイミド樹脂の透過分光感
度特性及び反射分光感度特性の低い波長領域である45
0nm以下の波長域を有する照明、もしくはバンドパス
フィルタ及び高角度反射照明を有する撮像手段を用いて
最外層パターンを撮像することにより、鮮明度の高い最
外層配線パターン画像を得ることができることを見いだ
した。
The wiring pattern imaging method of the present invention uses a polyimide film or a polyimide resin as an insulating base material and an insulating layer of a multilayer wiring board for a semiconductor package, and a transmission spectral sensitivity characteristic and a reflection spectral sensitivity characteristic of the polyimide film or the polyimide resin. Is a low wavelength region of 45
It has been found that an image of the outermost layer wiring pattern having a high definition can be obtained by imaging the outermost layer pattern by using an illumination device having a wavelength range of 0 nm or less, or an imaging means having a bandpass filter and a high-angle reflective illumination. It was

【0012】[0012]

【発明の実施の形態】以下、本発明の実施形態を図に従
って説明する。図1は本発明の実施形態を概念的に示し
たものである。半導体パッケージ用多層配線板からなる
対象テープ1をワーク固定機構7により位置固定させ
る。このときのワーク固定方法としては、表面に反射防
止膜を施した透明光学ガラスによるガラスサンドイッチ
やバキューム吸着等を行うことによって撮像光学系の焦
点深度内にワーク平坦性を確立でき、ワーク反りに対し
ても補正できる固定方法が望ましい。また、ワークがリ
ール形態を有するものであればワーク固定機構7の両側
に搬送用テープランナー機構を付加することも可能であ
る。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 conceptually shows an embodiment of the present invention. The target tape 1 made of a multilayer wiring board for a semiconductor package is fixed in position by a work fixing mechanism 7. As the work fixing method at this time, it is possible to establish work flatness within the depth of focus of the image pickup optical system by performing glass sandwich or vacuum adsorption with transparent optical glass with an antireflection film on the surface, and against work warpage. However, a fixing method that can be corrected is desirable. Further, if the work has a reel shape, it is possible to add a transport tape runner mechanism to both sides of the work fixing mechanism 7.

【0013】センサ2、結像レンズ3、フィルタ4及び
照明5は、ポリイミドフィルムもしくはポリイミド樹脂
の透過分光感度が低い波長域である450nm以下の波
長域に合わせて選択、構成する。センサ2及び結像レン
ズ3は、対象テープ1の配線パターンが最小で10μm
と微細であるため撮像によって得られる画像が高分解能
となるように光学設計したものを使用する。そのときの
分解能は、パターンエッジ情報が十分クリアに得られる
1μm及び2μm程度が望ましいが、この分解能設定は
対象となるパターン幅の1/9〜1/10程度が目安と
なる。
The sensor 2, the imaging lens 3, the filter 4 and the illumination 5 are selected and constructed in accordance with a wavelength range of 450 nm or less, which is a wavelength range in which the transmission spectral sensitivity of the polyimide film or the polyimide resin is low. As for the sensor 2 and the imaging lens 3, the wiring pattern of the target tape 1 is at least 10 μm.
Since it is fine, an optical design is used so that the image obtained by imaging has high resolution. The resolution at that time is preferably about 1 μm and 2 μm so that the pattern edge information can be obtained sufficiently sufficiently, but the target of this resolution setting is about 1/9 to 1/10 of the target pattern width.

【0014】照明5は、可視域全域に渡って発光する高
輝度照明を使用し、かつフィルタ4はポリイミドフィル
ムもしくはポリイミド樹脂の分光反射感度特性及び分光
透過感度特性から450nm以上の波長域をカットする
バンドパスフィルタを使用する。または、ポリイミドフ
ィルムもしくはポリイミド樹脂の分光感度から必要な波
長域のみを発光する光源を使用する。同一テープ上に存
在する複数パターン像を得るために必要ならばセンサ
2,結像レンズ3、フィルタ4等で構成される撮像部及
びワーク固定機構を必要取込方向に動かす機構も含め
る。
The illumination 5 uses high-intensity illumination that emits light over the entire visible range, and the filter 4 cuts a wavelength range of 450 nm or more from the spectral reflection sensitivity characteristics and spectral transmission sensitivity characteristics of the polyimide film or polyimide resin. Use a bandpass filter. Alternatively, a light source that emits light only in a required wavelength range is used due to the spectral sensitivity of the polyimide film or the polyimide resin. If necessary in order to obtain a plurality of pattern images existing on the same tape, a mechanism for moving the image pickup section composed of the sensor 2, the imaging lens 3, the filter 4 and the like, and the work fixing mechanism in the necessary take-in direction is also included.

【0015】センサ2は、パーソナルコンピュータ、キ
ーボード、マウス、ディスプレイ等から構成される演算
部6に接続され、ここで結像された像をパターン画像と
して再構成し、各種演算、認識処理を行う。また、ワー
ク固定機構やユーザーインターフェースの役割も受け持
つ。
The sensor 2 is connected to an arithmetic unit 6 composed of a personal computer, a keyboard, a mouse, a display, etc., and the image formed here is reconstructed as a pattern image to perform various arithmetic operations and recognition processing. It is also responsible for the work fixing mechanism and user interface.

【0016】[0016]

【実施例】図2は半導体パッケージ用多層配線板の絶縁
基材及び絶縁層に使用したポリイミドフィルム及びポリ
イミド樹脂の分光透過率特性及び分光反射率特性データ
を、図3は配線パターン形成に使用した銅箔の分光反射
率特性データをそれぞれ示す。このような絶縁基材、絶
縁層及び配線パターンを形成する基材分光感度情報を事
前に得ておき、ポリイミドフィルム及び銅箔に含まれる
基材材料による光の吸収影響を避けた波長域を活用して
鮮明なパターン画像を得る。
EXAMPLE FIG. 2 shows spectral transmittance characteristics and spectral reflectance characteristics data of a polyimide film and a polyimide resin used for an insulating base material and an insulating layer of a multilayer wiring board for a semiconductor package, and FIG. 3 is used for forming a wiring pattern. The spectral reflectance characteristic data of the copper foil are shown below. Utilize the wavelength range that avoids the light absorption effect of the base material contained in the polyimide film and copper foil by obtaining the base material spectral sensitivity information for forming such an insulating base material, insulating layer and wiring pattern in advance. To obtain a clear pattern image.

【0017】照明5として、RGB照明を使用し、照明
条件の違いによる配線のパターンの撮像例を図4及び図
5に示す。R成分(650nm付近)、G成分(520
nm付近)、B成分(450nm付近)の波長域を発光
するRGB照明を使用し、RGB全点灯した場合とB成
分(450nm付近)の波長域を点灯させた場合につい
ての撮像比較例を示す。RGB全点灯させた場合は図4
に示すように、最外層配線パターンの他に内層配線パタ
ーンが確認できるのに対し、450nm付近のB成分を
点灯させた場合は図5に示すように最外層配線パターン
だけがはっきり見える。このように基材材料による光の
吸収の影響を避けた波長域を活用して鮮明なパターン画
像を得ることができる。
RGB illumination is used as the illumination 5, and an example of an image of the wiring pattern depending on the illumination conditions is shown in FIGS. 4 and 5. R component (near 650 nm), G component (520
Next, an image capturing comparative example will be shown for the case where RGB illumination that emits wavelength ranges of B component (around 450 nm) and B component (around 450 nm) are used, and the case where all wavelengths of B component (around 450 nm) are turned on. Figure 4 when all RGB are turned on
As shown in FIG. 5, the inner layer wiring pattern can be confirmed in addition to the outermost layer wiring pattern, whereas when the B component near 450 nm is turned on, only the outermost layer wiring pattern is clearly visible as shown in FIG. In this way, a clear pattern image can be obtained by utilizing the wavelength range avoiding the influence of light absorption by the base material.

【0018】次に側方照明(テーパー照明)と高角度照
明で照明角度の違いによる半導体パッケージ用多層配線
板の配線パターンの撮像例を図6及び図7に示す。側方
照明では、図6に示すように最外層配線パターンの他に
内層配線パターンが確認できるのに対し、高角度照明で
は、図7に示すように最外層配線パターンだけがはっき
り見えることが分かる。一般に同軸(高角度)照明のみ
の場合配線パターンのトップ面のみが明るく映し出さ
れ、エッチング不良による突起やスペース不良は顕在化
できない。しかし、そこに側方照明を加えることによっ
てわずかなエッチング残りによると突起も明るく顕在化
することができる。このように高角度照明と側方照明と
の長所を掛け合わせた照明系を活用することにより下地
パターンの影響のない鮮明なパターン画像を得ることが
可能である。
Next, FIGS. 6 and 7 show examples of image pickup of the wiring pattern of the multilayer wiring board for semiconductor package depending on the difference in the illumination angle between the side illumination (tapered illumination) and the high angle illumination. In the side illumination, the inner layer wiring pattern can be confirmed in addition to the outermost layer wiring pattern as shown in FIG. 6, whereas in the high-angle illumination, only the outermost layer wiring pattern is clearly visible as shown in FIG. . Generally, in the case of only coaxial (high angle) illumination, only the top surface of the wiring pattern is brightly projected, and protrusions and space defects due to etching defects cannot be revealed. However, by applying lateral illumination thereto, the protrusion can be made bright and visible due to slight etching residue. By utilizing an illumination system that combines the advantages of high-angle illumination and side illumination in this way, it is possible to obtain a clear pattern image that is not affected by the underlying pattern.

【0019】[0019]

【発明の効果】上記したように、本発明の配線パターン
の撮像方法によれば、半導体パッケージ用多層配線板の
絶縁基材及び絶縁層としてポリイミドフィルムもしくは
ポリイミド樹脂を用いることにより、内層配線パターン
の影響を受けずに、最上層配線パターンだけを鮮明な画
像として撮像でき、半導体パッケージ用多層配線板の配
線パターンの自動検査等に使用する有効な画像として提
供することができる。
As described above, according to the wiring pattern imaging method of the present invention, by using the polyimide film or the polyimide resin as the insulating base material and the insulating layer of the multilayer wiring board for the semiconductor package, the inner layer wiring pattern can be formed. Only the uppermost layer wiring pattern can be picked up as a clear image without being affected, and it can be provided as an effective image used for automatic inspection of the wiring pattern of the semiconductor package multilayer wiring board.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の配線パターンの実施形態を概念的に示
した説明図である。
FIG. 1 is an explanatory view conceptually showing an embodiment of a wiring pattern of the present invention.

【図2】絶縁基材及び絶縁層に使用したポリイミドフィ
ルムもしくはポリイミド樹脂の分光透過率特性及び分光
反射率特性を示すグラフである。
FIG. 2 is a graph showing spectral transmittance characteristics and spectral reflectance characteristics of a polyimide film or a polyimide resin used for an insulating base material and an insulating layer.

【図3】配線パターンの形成に使用した銅箔の分光反射
率特性を示すグラフである。
FIG. 3 is a graph showing a spectral reflectance characteristic of a copper foil used for forming a wiring pattern.

【図4】照明としてRGB照明を使用して撮像した配線
パターンの画像例である。
FIG. 4 is an image example of a wiring pattern imaged by using RGB illumination as illumination.

【図5】照明としてB照明(450nm付近)を使用し
て撮像した配線パターンの画像例である。
FIG. 5 is an image example of a wiring pattern imaged using B illumination (around 450 nm) as illumination.

【図6】照明として側方照明(テーパー照明)を使用し
て撮像した配線パターンの画像例である。
FIG. 6 is an image example of a wiring pattern imaged by using side illumination (tapered illumination) as illumination.

【図7】照明として高角度照明を使用して撮像した配線
パターンの画像例である。
FIG. 7 is an image example of a wiring pattern imaged by using high-angle illumination as illumination.

【符号の説明】[Explanation of symbols]

1……対象テープ 2……センサ 3……結像レンズ 4……フィルタ 5……照明 6……演算部 7……ワーク固定機構 1 ... Target tape 2 ... Sensor 3 ... Imaging lens 4 ... Filter 5 ... Lighting 6 ... Calculator 7: Work fixing mechanism

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】絶縁基材の両面に配線パターン及び絶縁層
が順次形成された半導体パッケージ用多層配線板の最外
層の配線パターンを画像として撮像する方法であって、
450nm以下の波長域を有する照明、もしくはバンド
パスフィルタを用いた撮像手段によって、半導体パッケ
ージ用多層配線板の最外層の配線パターンを撮像するこ
とを特徴とする配線パターンの撮像方法。
1. A method for picking up an image of a wiring pattern of an outermost layer of a multilayer wiring board for a semiconductor package in which a wiring pattern and an insulating layer are sequentially formed on both surfaces of an insulating base material.
An image pickup method for a wiring pattern, characterized by picking up an image of the wiring pattern of the outermost layer of a semiconductor package multilayer wiring board by an image pickup means using an illumination having a wavelength range of 450 nm or less or a bandpass filter.
【請求項2】請求項1記載の撮像方法において、高角度
反射照明を用いた撮像手段によって半導体パッケージ用
多層配線板の最外層の配線パターンを撮像することを特
徴とする配線パターンの撮像方法。
2. The image pickup method according to claim 1, wherein an image pickup means using high-angle reflective illumination picks up an image of the outermost wiring pattern of the multilayer wiring board for a semiconductor package.
【請求項3】前記絶縁基材及び前記絶縁層がポリイミド
フィルムまたはポリイミド樹脂からなることを特徴とす
る請求項1または2に記載の配線パターンの撮像方法。
3. The wiring pattern imaging method according to claim 1, wherein the insulating base material and the insulating layer are made of a polyimide film or a polyimide resin.
JP2002023068A 2002-01-31 2002-01-31 Imaging method of wiring pattern Pending JP2003222510A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002023068A JP2003222510A (en) 2002-01-31 2002-01-31 Imaging method of wiring pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002023068A JP2003222510A (en) 2002-01-31 2002-01-31 Imaging method of wiring pattern

Publications (1)

Publication Number Publication Date
JP2003222510A true JP2003222510A (en) 2003-08-08

Family

ID=27745882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002023068A Pending JP2003222510A (en) 2002-01-31 2002-01-31 Imaging method of wiring pattern

Country Status (1)

Country Link
JP (1) JP2003222510A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007010497A (en) * 2005-06-30 2007-01-18 Ckd Corp Inspection device of substrate
JP2010016244A (en) * 2008-07-04 2010-01-21 Nitto Denko Corp Method of manufacturing wiring circuit board
JP2012059756A (en) * 2010-09-06 2012-03-22 Nitto Denko Corp Wiring circuit board and method of manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007010497A (en) * 2005-06-30 2007-01-18 Ckd Corp Inspection device of substrate
JP2010016244A (en) * 2008-07-04 2010-01-21 Nitto Denko Corp Method of manufacturing wiring circuit board
JP2012059756A (en) * 2010-09-06 2012-03-22 Nitto Denko Corp Wiring circuit board and method of manufacturing the same
US9084359B2 (en) 2010-09-06 2015-07-14 Nitto Denko Corporation Wired circuit board having enhanced contrast between conductive pattern and insulating layer during inspection
US9839137B2 (en) 2010-09-06 2017-12-05 Nitto Denko Corporation Wired circuit board and producing method thereof

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