JP2003218251A - Electronic device and method of manufacturing the same - Google Patents

Electronic device and method of manufacturing the same

Info

Publication number
JP2003218251A
JP2003218251A JP2002018213A JP2002018213A JP2003218251A JP 2003218251 A JP2003218251 A JP 2003218251A JP 2002018213 A JP2002018213 A JP 2002018213A JP 2002018213 A JP2002018213 A JP 2002018213A JP 2003218251 A JP2003218251 A JP 2003218251A
Authority
JP
Japan
Prior art keywords
circuit element
cavity
resin
package
electronic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002018213A
Other languages
Japanese (ja)
Inventor
Hideki Shinkai
秀樹 新開
Masato Higuchi
真人 日口
Etsuo Nishikawa
悦生 西川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2002018213A priority Critical patent/JP2003218251A/en
Publication of JP2003218251A publication Critical patent/JP2003218251A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic device and a method of manufacturing the same which enables to stop the flow of resin to fill a space between a circuit element and a package at a certain position to form a hollow section accurately. <P>SOLUTION: The electronic device comprises the circuit element 10 having a function section 12 and electrodes 13 on the bottom, and a package 1 having a cavity 2 wherein the circuit element 10 is stored and has electrode pads 3 formed on the bottom. The electrodes 13 of the circuit element 10 and the electrode pads 3 of the package 1 are connected by bumps 15, and a space between the circuit element 10 and the cavity 2 is sealed by the resin 20. In an inside wall of the cavity 2 which faces a side face of the circuit element 10, a step section 4 is formed on the entire circumference so that a space δbetween the cavity and the side face of the circuit element 10 is larger on the bottom side than on the opening side. Then, the resin 20 is supplied into part of the cavity 2 from the opening to the step section 4, and is hardened. As a result, the hollow section 21 is formed between the bottom of the circuit element 10 and the bottom of the cavity 2. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は回路素子をキャビテ
ィを有するパッケージにフリップチップ実装するととも
に、回路素子とパッケージとの間を樹脂で封止した電子
デバイスおよびその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device in which a circuit element is flip-chip mounted in a package having a cavity and a resin is provided between the circuit element and the package, and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来、半導体素子などの回路素子をキャ
ビティタイプのパッケージにフリップチップ実装した電
子デバイスの場合、その封止を取るために、蓋をパッケ
ージに接着したものが知られている(特開平10−65
071号公報)。しかし、蓋をするためには、接着剤を
塗布する工程と、蓋とパッケージとを接着する工程とが
必要になり、工程数が増えるとともに、蓋のためにサイ
ズを小型化、低背化するには限界があった。
2. Description of the Related Art Conventionally, in the case of an electronic device in which a circuit element such as a semiconductor element is flip-chip mounted in a cavity type package, it is known that a lid is adhered to the package in order to remove the sealing. Kaihei 10-65
No. 071). However, in order to cover the lid, a step of applying an adhesive and a step of adhering the lid and the package to each other are required, and the number of steps increases, and the size and size of the lid are reduced. There was a limit.

【0003】[0003]

【発明が解決しようとする課題】そこで、工程数を減ら
し、小型・低背化する構造として、特開2000−13
8321号公報には、蓋の代わりに樹脂で封止する電子
デバイスが提案されている。図8は上記電子デバイスの
一例を示す。図において、30はパッケージ、31はキ
ャビティ、32はキャビティ31の底面に形成された電
極パッド、33は回路素子、34,35は回路素子33
の下面に形成された電極および機能部、36は電極34
と電極パッド32とを接合するバンプ、37は封止用樹
脂である。
Therefore, as a structure for reducing the number of steps, downsizing, and height reduction, Japanese Unexamined Patent Publication No. 2000-13 has been proposed.
Japanese Patent No. 8321 proposes an electronic device which is sealed with a resin instead of a lid. FIG. 8 shows an example of the electronic device. In the figure, 30 is a package, 31 is a cavity, 32 is an electrode pad formed on the bottom surface of the cavity 31, 33 is a circuit element, and 34 and 35 are circuit elements 33.
Electrodes and functional portions formed on the lower surface of the
Is a bump for joining the electrode pad 32 with the electrode pad 32, and 37 is a sealing resin.

【0004】上記電子デバイスの場合、キャビティ31
の内側壁と回路素子33の側面との隙間が奥行き方向に
ほぼ一定しているため、キャビティ31の開口部に流し
込まれた樹脂37がその毛細管現象によってキャビティ
31の内側壁と回路素子33の側面との隙間を通り、機
能部35が設けられた回路素子33の下面側にまで回り
込んでしまう。このように樹脂37が回路素子33の下
面側にまで回り込むと、樹脂37の材料特性である誘電
率や誘電損失によって回路素子33の電気的特性が影響
を受けるという問題がある。また、回路素子33がSA
W素子のような圧電振動子の場合、振動部35が樹脂3
7でダンピングされるので、特性自体が発現しないとい
う問題を生じる。樹脂37が回路素子33の下面側まで
回り込まないように、高粘度樹脂を用いる方法もある
が、回路素子33とキャビティ31との隙間が4辺でば
らつくと、樹脂の浸入深さを均一にできず、封止性や固
定強度にばらつきが生じる可能性があった。
In the case of the above electronic device, the cavity 31
Since the gap between the inner wall of the cavity 31 and the side surface of the circuit element 33 is substantially constant in the depth direction, the resin 37 poured into the opening of the cavity 31 is capillarized to cause the inner wall of the cavity 31 and the side surface of the circuit element 33. Will pass through the gap between and to the lower surface side of the circuit element 33 provided with the functional portion 35. When the resin 37 wraps around to the lower surface side of the circuit element 33 in this way, there is a problem that the electrical characteristics of the circuit element 33 are affected by the dielectric constant and the dielectric loss that are material characteristics of the resin 37. In addition, the circuit element 33 is SA
In the case of a piezoelectric vibrator such as a W element, the vibrating part 35 is made of resin 3
Since it is dumped by 7, there arises a problem that the characteristic itself is not expressed. There is also a method of using a high-viscosity resin so that the resin 37 does not go around to the lower surface side of the circuit element 33, but if the gap between the circuit element 33 and the cavity 31 varies on four sides, the resin penetration depth can be made uniform. However, there is a possibility that the sealing property and the fixing strength may vary.

【0005】そこで、本発明の目的は、回路素子とパッ
ケージとの隙間に充填される樹脂の流れを一定位置で止
め、精度よく中空部を形成できる電子デバイスおよびそ
の製造方法を提供することにある。
Therefore, it is an object of the present invention to provide an electronic device and a method for manufacturing the same which can accurately form a hollow portion by stopping the flow of the resin filled in the gap between the circuit element and the package at a fixed position. .

【0006】[0006]

【課題を解決するための手段】上記目的を達成するた
め、請求項1に係る発明は、下面に機能部と電極とを有
する回路素子と、この回路素子を収容し、底面に電極パ
ッドが形成されたキャビティを有するパッケージとを備
え、上記回路素子の電極とパッケージの電極パッドとを
バンプにより接続するとともに、回路素子とキャビティ
との間を樹脂で封止した電子デバイスにおいて、上記回
路素子の側面と対向するキャビティの内側壁に、回路素
子の側面との隙間が開口部側より底部側の方が大きくな
る段差部が実質的に全周に設けられ、上記樹脂は上記キ
ャビティの開口部から段差部までの1囲に充填・硬化さ
れ、上記回路素子の下面とキャビティの底面との間に中
空部が形成されていることを特徴とする電子デバイスを
提供する。
In order to achieve the above object, the invention according to claim 1 is such that a circuit element having a functional portion and an electrode on the lower surface, the circuit element is accommodated, and an electrode pad is formed on the bottom surface. A package having a cavity formed therein, the electrodes of the circuit element and the electrode pads of the package are connected by bumps, and the circuit element and the cavity are sealed with a resin. The inner wall of the cavity facing the side surface of the cavity is provided with a step portion whose gap with the side surface of the circuit element is larger on the bottom side than on the opening side, and the resin is stepped from the opening of the cavity. The electronic device is characterized in that a hollow portion is formed between the lower surface of the circuit element and the bottom surface of the cavity, which is filled and hardened in one area up to the portion.

【0007】また、請求項4に係る発明は、下面に機能
部と電極とを有する回路素子を準備する工程と、上記回
路素子を収容するため、底面に電極パッドが形成された
キャビティを有し、上記回路素子の側面と対向するキャ
ビティの内側壁に、回路素子の側面との隙間が開口部側
より底部側の方が大きくなる段差部が実質的に全周に設
けられたパッケージを準備する工程と、上記回路素子の
電極上およびパッケージの電極パッド上の少なくとも一
方にバンプを形成する工程と、上記回路素子の電極とパ
ッケージの電極パッドとをバンプにより接続する工程
と、上記回路素子とキャビティとの間を樹脂で封止する
工程であって、上記回路素子の下面とキャビティの底面
との間に中空部を残した状態で、上記樹脂を上記キャビ
ティの開口部から段差部までの範囲に充填し、硬化させ
る工程と、を有することを特徴とする電子デバイスの製
造方法を提供する。
The invention according to claim 4 has a step of preparing a circuit element having a functional portion and an electrode on the lower surface, and a cavity having an electrode pad formed on the bottom surface for accommodating the circuit element. , A package is provided in which an inner side wall of the cavity facing the side surface of the circuit element is provided with a step portion whose gap with the side surface of the circuit element is larger on the bottom side than on the opening side substantially all around. A step, a step of forming a bump on at least one of the electrode of the circuit element and an electrode pad of the package, a step of connecting the electrode of the circuit element and an electrode pad of the package by a bump, the circuit element and the cavity And a step of sealing the resin between the lower surface of the circuit element and the bottom surface of the cavity while leaving a hollow portion between the lower surface of the circuit element and the bottom surface of the cavity. Filling range up parts, to provide a curing method for manufacturing the electronic device, characterized in that it comprises a.

【0008】本発明では、回路素子の側面と対向するキ
ャビティの内側壁に、回路素子の側面との隙間が開口部
側より底部側の方が大きくなる段差部を実質的に全周に
設けてある。キャビティの開口部に流し込まれた樹脂
は、毛細管現象によってキャビティの内側壁と回路素子
の側面との隙間に流入するが、段差部によってキャビテ
ィの内側壁と回路素子の側面との隙間が急拡大するの
で、樹脂と段差部との接触角が減少し、樹脂の流れが止
められる。そのため、樹脂が回路素子の下面側へ流れ込
むのが阻止され、回路素子の下面とキャビティの底面と
の間に中空部を安定して形成することができる。回路素
子の機能部に樹脂が付着しないので、樹脂の誘電率や誘
電損失によって回路素子の電気的特性が影響を受けるの
を防止できる。また、回路素子の側面とキャビティの内
側壁との隙間が4辺でばらついても、段差部で樹脂の流
れが確実に止められるので、樹脂の浸入深さは段差部に
よって規定される。そのため、封止性および固定強度が
回路素子の周囲4辺で一定となり、安定した性能の電子
デバイスが得られる。さらに、樹脂によって封止ができ
るので、パッケージに蓋を接着する必要がなく、工程数
を削減できるとともに、電子デバイスの小型化,低背化
が可能となる。
According to the present invention, the inner wall of the cavity facing the side surface of the circuit element is provided with a step portion whose gap between the side surface of the circuit element and the side surface of the circuit element is larger on the bottom side than on the opening side. is there. The resin that has flowed into the opening of the cavity flows into the gap between the inner wall of the cavity and the side surface of the circuit element due to the capillary phenomenon, but the gap between the inner wall of the cavity and the side surface of the circuit element suddenly expands due to the stepped portion. Therefore, the contact angle between the resin and the step portion is reduced, and the resin flow is stopped. Therefore, the resin is prevented from flowing into the lower surface side of the circuit element, and the hollow portion can be stably formed between the lower surface of the circuit element and the bottom surface of the cavity. Since the resin does not adhere to the functional portion of the circuit element, it is possible to prevent the electrical characteristics of the circuit element from being affected by the dielectric constant and the dielectric loss of the resin. Further, even if the gap between the side surface of the circuit element and the inner wall of the cavity varies on the four sides, the resin flow can be reliably stopped at the step portion, so the resin penetration depth is defined by the step portion. Therefore, the sealing property and the fixing strength are constant on the four sides around the circuit element, and an electronic device with stable performance can be obtained. Further, since it can be sealed with resin, it is not necessary to attach a lid to the package, the number of steps can be reduced, and the electronic device can be downsized and the height can be reduced.

【0009】本発明における段差部とは、樹脂止め部と
して作用するものであり、回路素子の側面と対向するキ
ャビティの内側壁にほぼ全周に設けられ、回路素子の側
面との隙間が開口部側より底部側の方が大きくなる部分
を少なくとも含んでおればよい。したがって、段差の上
部または下部に隣接して凸部や凹部、曲面などを有して
いてもよい。段差部は、キャビティの内側壁の全周に設
けられている必要はなく、樹脂止め部として作用する限
り、部分的に段差部が欠けた部分があってもよい。樹脂
としては、エポキシ系樹脂組成物が好ましいが、これに
限定されるものではない。液状樹脂の粘度は、低ければ
低い程、短時間で充填作業が終了するので好ましい。粘
度が高過ぎると、隙間の狭いところに入らないので、液
状の封止樹脂の粘度を500Pa・s以下とするのがよ
い。樹脂の硬化方法としては、加熱、UV照射、電子線
照射などの樹脂材料に適した方法で行えばよい。
The step portion in the present invention functions as a resin stopper portion, and is provided almost all around the inner wall of the cavity facing the side surface of the circuit element, and the gap with the side surface of the circuit element is the opening. It is sufficient to include at least a portion in which the bottom side is larger than the side side. Therefore, a convex portion, a concave portion, a curved surface, or the like may be provided adjacent to the upper portion or the lower portion of the step. The step portion does not have to be provided on the entire circumference of the inner wall of the cavity, and may have a portion where the step portion is partially cut off as long as it functions as a resin stopper. The resin is preferably an epoxy resin composition, but is not limited to this. The lower the viscosity of the liquid resin, the more preferable the filling operation is completed in a short time. If the viscosity is too high, it will not enter the narrow space, so it is preferable that the viscosity of the liquid sealing resin be 500 Pa · s or less. The resin can be cured by a method suitable for the resin material such as heating, UV irradiation, electron beam irradiation, or the like.

【0010】請求項2のように、回路素子の下面から段
差部までの高さを0.1mm以下とするのがよい。キャ
ビティの内側壁に設けた段差部によって樹脂の素子側へ
の流れ出しは防止されるが、パッケージ側への流れ出し
は、回路素子の下面から段差部までの高さtが大きいと
発生する傾向にある。そこで、回路素子の下面から段差
部までの高さを0.1mm以下にすることで、樹脂のパ
ッケージ側への流れ出しを確実に防止できる。
As described in claim 2, the height from the lower surface of the circuit element to the step portion is preferably 0.1 mm or less. The step provided on the inner wall of the cavity prevents the resin from flowing out to the element side, but the resin flows out to the package side when the height t from the lower surface of the circuit element to the step is large. . Therefore, by setting the height from the lower surface of the circuit element to the step portion to 0.1 mm or less, it is possible to reliably prevent the resin from flowing out to the package side.

【0011】請求項3のように、回路素子の上面を、キ
ャビティの開口部表面より低い位置とし、樹脂を回路素
子の上面および回路素子の側面とキャビティの内側壁と
の間に充填するのがよい。この場合には、回路素子の上
面とキャビティの開口部とで凹部が形成されるので、こ
の凹部に樹脂を流し込むと、樹脂はキャビティの開口部
に拡がるとともに、回路素子の側面とキャビティの内側
壁との間にも流れ込み、1回の充填で回路素子の周囲全
体に均一に樹脂を流し込むことができる。また、樹脂が
回路素子の側面だけでなく上面も覆っているので、回路
素子と外部との絶縁性が向上し、保持強度も高くなる。
According to a third aspect of the present invention, the upper surface of the circuit element is positioned lower than the surface of the opening of the cavity, and resin is filled between the upper surface of the circuit element and the side surface of the circuit element and the inner wall of the cavity. Good. In this case, since the recess is formed by the upper surface of the circuit element and the opening of the cavity, when the resin is poured into this recess, the resin spreads to the opening of the cavity and the side surface of the circuit element and the inner wall of the cavity are formed. The resin can be evenly flowed around the entire circumference of the circuit element by one filling. Further, since the resin covers not only the side surface of the circuit element but also the upper surface, the insulating property between the circuit element and the outside is improved, and the holding strength is also increased.

【0012】[0012]

【発明の実施の形態】図1は本発明にかかる電子デバイ
スの一例を示す。この電子デバイスは、パッケージ1に
回路素子10をフェースダウン実装したものである。パ
ッケージ1は、アルミナなどのセラミック材料、ガラス
エポキシ樹脂などの気密性、電気的絶縁性、耐熱性を有
する材料よりなる。パッケージ1には上方が開口したキ
ャビティ2が形成され、キャビティ2の底面には複数の
電極パッド3が形成されている。これら電極パッド3は
それぞれパッケージ1の外部に導出されている。
1 shows an example of an electronic device according to the present invention. In this electronic device, a circuit element 10 is mounted face down on a package 1. The package 1 is made of a ceramic material such as alumina and a material having airtightness, electrical insulation and heat resistance such as glass epoxy resin. The package 1 is formed with a cavity 2 having an upper opening, and a plurality of electrode pads 3 are formed on the bottom surface of the cavity 2. Each of these electrode pads 3 is led out of the package 1.

【0013】キャビティ2の内側壁には、回路素子10
の側面との隙間が開口部側より底部側の方が大きくなる
段差部4が全周に設けられている。つまり、キャビティ
2の内側壁はオーバーハング状になっている。この段差
部4は、回路素子10を実装した状態で、回路素子10
の側面と対向する高さに形成されている。すなわち、キ
ャビティ2の底面から段差部4までの高さh1 は、キャ
ビティ2の底面から実装状態における回路素子10の上
面までの高さh2 より低く、回路素子10の下面までの
高さh3 より高い。なお、キャビティ2の深さh4 はキ
ャビティ2の底面から回路素子10の上面までの高さh
2 より大きい。
A circuit element 10 is provided on the inner wall of the cavity 2.
A step portion 4 is provided on the entire circumference so that the gap with the side surface of the bottom side is larger than that on the opening side. That is, the inner wall of the cavity 2 has an overhang shape. This step portion 4 has the circuit element 10 mounted thereon.
Is formed at a height facing the side surface of the. That is, the height h 1 from the bottom surface of the cavity 2 to the step portion 4 is lower than the height h 2 from the bottom surface of the cavity 2 to the top surface of the circuit element 10 in the mounted state, and the height h 1 to the bottom surface of the circuit element 10. Higher than 3 . The depth h 4 of the cavity 2 is the height h from the bottom surface of the cavity 2 to the top surface of the circuit element 10.
Greater than 2 .

【0014】上記段差部4を有するパッケージ1の形成
方法は、図2のように種々の方法が考えられる。図2の
(A)は3層のセラミック層1a,1b,1cを積層し
たものであり、第1層1aにはキャビティ2の開口部と
なる穴1a1 が形成され、第2層1bには第1層1aの
穴より大形な穴1b1 が形成されている。第3層1cに
は穴が設けられていない。また、図2の(B)は、内側
面に段差部4を形成した一対のパッケージ部材1dと1
eとを対向して接着したものである。図2の(C)は、
段差部を有しないパッケージ1のキャビティ2の開口部
内面に、枠状部材1fを固定することにより、段差部4
を形成したものである。段差部の形成方法は上記に限る
ものではない。
As a method of forming the package 1 having the step portion 4, various methods can be considered as shown in FIG. FIG. 2A shows a structure in which three ceramic layers 1a, 1b, 1c are laminated, a hole 1a 1 which is an opening of the cavity 2 is formed in the first layer 1a, and a second layer 1b is formed. A hole 1b 1 larger than the hole in the first layer 1a is formed. No holes are provided in the third layer 1c. Further, FIG. 2B shows a pair of package members 1d and 1d having a step portion 4 formed on the inner surface thereof.
e is bonded to face each other. In FIG. 2C,
By fixing the frame-shaped member 1f to the inner surface of the opening of the cavity 2 of the package 1 having no step portion, the step portion 4 is formed.
Is formed. The method of forming the step portion is not limited to the above.

【0015】この実施例の回路素子10は弾性表面波チ
ップであり、図3に示すように、水晶やLiTaO3
LiNbO3 等からなる圧電基板11の主面に、Al等
からなる2組のIDT電極12とTi/Ni/Au等か
らなる4個の入出力電極13とを形成したものである。
機能部であるIDT電極12と入出力電極13とは相互
に接続されている。入出力電極13のそれぞれにはバン
プ15が固定されている。バンプ15としては、Au,
Ag,Pd,Cuを主成分とする金属バンプや、はんだ
バンプなどを用いることができる。バンプ15は、めっ
き法、ワイヤボンディング法などを用いて形成される
が、ここではワイヤボンディング法によりAuバンプを
形成した。回路素子10の外寸は、キャビティ2の開口
部内寸より小さく、各辺の隙間δ(図1参照)は、後述
する液状の封止樹脂20が毛細管現象によって充填され
る隙間とされている。液状の封止樹脂の粘度が500P
a・s以下の場合、隙間δを0.3mm以下とするのが
よい。
The circuit element 10 of this embodiment is a surface acoustic wave chip, and as shown in FIG. 3, crystal, LiTaO 3 ,
Two sets of IDT electrodes 12 made of Al or the like and four input / output electrodes 13 made of Ti / Ni / Au or the like are formed on the main surface of a piezoelectric substrate 11 made of LiNbO 3 or the like.
The IDT electrode 12 and the input / output electrode 13, which are the functional parts, are connected to each other. A bump 15 is fixed to each of the input / output electrodes 13. As the bump 15, Au,
A metal bump containing Ag, Pd, or Cu as a main component, a solder bump, or the like can be used. The bumps 15 are formed by using a plating method, a wire bonding method, or the like. Here, the Au bumps are formed by the wire bonding method. The outer size of the circuit element 10 is smaller than the inner size of the opening of the cavity 2, and the gap δ (see FIG. 1) on each side is a gap in which a liquid sealing resin 20 described later is filled by a capillary phenomenon. The viscosity of the liquid sealing resin is 500P
In the case of a · s or less, the gap δ is preferably 0.3 mm or less.

【0016】上記キャビティ2の開口部には、例えばエ
ポキシ系樹脂などよりなる封止用樹脂20が注入され、
硬化されている。液状の樹脂20の一部は毛細管現象に
より回路素子10の側面とキャビティ2の内側壁との隙
間に流入するが、段差部4によってキャビティ2の内側
壁と回路素子10の側面との隙間が急拡大するので、樹
脂20と段差部4との接触角が減少し、樹脂20の流れ
が止められる。そのため、樹脂20が回路素子10の下
面側へ流れ込むのが防止され、回路素子10の下面(機
能部12を設けた面)とキャビティ4の底面との間に中
空部21を形成することができる。回路素子10の機能
部12に樹脂20が付着しないので、回路素子10の振
動特性に悪影響を及ぼさない。また、樹脂20の誘電率
や誘電損失によって回路素子10の電気的特性が影響を
受けることもない。樹脂20が所定量注入された後、樹
脂20が硬化される。加熱、UV照射、電子線照射など
の公知の方法で行えばよい。
A sealing resin 20 made of, for example, an epoxy resin is injected into the opening of the cavity 2,
It is hardened. A part of the liquid resin 20 flows into the gap between the side surface of the circuit element 10 and the inner side wall of the cavity 2 due to a capillary phenomenon, but the step portion 4 causes a sharp gap between the inner side wall of the cavity 2 and the side surface of the circuit element 10. Since it expands, the contact angle between the resin 20 and the step portion 4 decreases, and the flow of the resin 20 is stopped. Therefore, the resin 20 is prevented from flowing into the lower surface side of the circuit element 10, and the hollow portion 21 can be formed between the lower surface of the circuit element 10 (the surface provided with the functional portion 12) and the bottom surface of the cavity 4. . Since the resin 20 does not adhere to the functional portion 12 of the circuit element 10, the vibration characteristics of the circuit element 10 are not adversely affected. Further, the electric characteristics of the circuit element 10 are not affected by the dielectric constant and the dielectric loss of the resin 20. After the resin 20 is injected in a predetermined amount, the resin 20 is cured. A known method such as heating, UV irradiation, or electron beam irradiation may be used.

【0017】ここで、上記構成よりなる電子デバイスの
製造方法について、図4を参照して説明する。まず図4
の(a)のように、キャビティ2およびその底面に電極
パッド3が形成されたパッケージ1を準備する。キャビ
ティ2の内側壁には、開口部側より底部側が拡張された
段差部4が全周に設けられている。また、下面にIDT
電極12と入出力電極13とが形成され、入出力電極1
3上にバンプ15が形成された回路素子10を準備す
る。そして、回路素子10の上面(IDT電極12を設
けていない面)を熱圧着ツールAで吸着し、パッケージ
1の電極パッド3と回路素子10のバンプ15とが上下
に対応するように位置決めし、バンプ15を電極パッド
3に対して、熱圧着ツールAによって熱と圧力とを加え
て接合する。なお、熱圧着に限らず、超音波によって接
合してもよく、さらには超音波と熱圧着とを併用しても
よい。熱圧着によって、バンプ15の一部が押し潰さ
れ、バンプ15と電極パッド3とが拡散接合される。接
合状態で、キャビティ2と回路素子10との間に所定の
隙間δが形成される。次に、図4の(b)のように、デ
ィスペンサBによって液状の封止樹脂20をキャビティ
2の中、つまり回路素子10の上面に供給すると、樹脂
20は毛細管現象によって、回路素子10の側面とキャ
ビティ2の内側壁との隙間δに流れ込む。段差部4まで
流れ込んだ樹脂20は、段差部4で接触角が減少するた
め、樹脂20の流れが止まる。そのため、回路素子10
の下面とキャビティ2の底面との間に中空部21が形成
され、回路素子10の機能部12に樹脂20が付着する
ことがない。また、樹脂20の浸入深さは段差部4によ
って規定されるので、常に一定深さとなり、封止性およ
び固定強度が安定する。封止樹脂20を塗布した後、パ
ッケージ1を硬化炉に投入して封止樹脂20を硬化させ
れば、図1に示す樹脂封止型の電子デバイスが完成す
る。
Here, a method of manufacturing the electronic device having the above structure will be described with reference to FIG. Figure 4
As shown in (a), the package 1 having the cavity 2 and the electrode pad 3 formed on the bottom surface thereof is prepared. On the inner wall of the cavity 2, a step portion 4 whose bottom side is expanded from the opening side is provided all around. Also, the IDT on the bottom
The electrode 12 and the input / output electrode 13 are formed, and the input / output electrode 1
A circuit element 10 having bumps 15 formed on the surface 3 is prepared. Then, the upper surface of the circuit element 10 (the surface on which the IDT electrode 12 is not provided) is adsorbed by the thermocompression bonding tool A, and the electrode pads 3 of the package 1 and the bumps 15 of the circuit element 10 are positioned so as to correspond to each other vertically. The bumps 15 are bonded to the electrode pads 3 by applying heat and pressure with the thermocompression bonding tool A. Not limited to thermocompression bonding, ultrasonic bonding may be performed, and ultrasonic waves and thermocompression bonding may be used together. By thermocompression bonding, a part of the bump 15 is crushed and the bump 15 and the electrode pad 3 are diffusion-bonded. In the joined state, a predetermined gap δ is formed between the cavity 2 and the circuit element 10. Next, as shown in FIG. 4B, when the liquid sealing resin 20 is supplied to the inside of the cavity 2, that is, the upper surface of the circuit element 10 by the dispenser B, the resin 20 is caused by the capillary phenomenon to the side surface of the circuit element 10. Flows into the gap δ between the inner wall of the cavity 2 and the inner wall of the cavity 2. Since the contact angle of the resin 20 that has flowed to the step portion 4 decreases at the step portion 4, the flow of the resin 20 stops. Therefore, the circuit element 10
The hollow portion 21 is formed between the lower surface of the circuit element 10 and the bottom surface of the cavity 2, so that the resin 20 does not adhere to the functional portion 12 of the circuit element 10. Further, since the penetration depth of the resin 20 is defined by the step portion 4, it is always a constant depth, and the sealing property and the fixing strength are stable. After applying the sealing resin 20, the package 1 is put into a curing furnace to cure the sealing resin 20, and the resin-sealed electronic device shown in FIG. 1 is completed.

【0018】図5は回路素子10の下面から段差部4ま
での高さt(=h1 −h3 )および隙間δと樹脂の流れ
出しとの関係を示したものである。○印は樹脂の流れ出
しがない場合、△印は図6のように樹脂20が段差部4
の下側へ流れた場合を示す。いずれの場合も、樹脂20
が回路素子10の下面側へ流れ出ることはない。図5か
ら明らかなように、段差部4の高さtを0.10mm以
下とした場合には、樹脂20が段差部4の下側へ流れ出
すのを防止できることがわかる。
FIG. 5 shows the relationship between the height t (= h 1 -h 3 ) from the lower surface of the circuit element 10 to the step portion 4 and the gap δ and the resin outflow. The ○ mark indicates that the resin 20 does not flow out, and the Δ mark indicates that the resin 20 indicates the step portion 4 as shown in FIG.
It shows the case of flowing downward. In any case, resin 20
Does not flow out to the lower surface side of the circuit element 10. As is clear from FIG. 5, when the height t of the step portion 4 is 0.10 mm or less, the resin 20 can be prevented from flowing out to the lower side of the step portion 4.

【0019】図7は、パッケージ1の段差部4の形状
と、回路素子10の側面形状との種々の組み合わせを示
す。段差部4の形状は、図1と同一形状のもの(1),
4),7),10))、キャビティ2の内側壁に周溝4aを形
成したもの(2),5),8),11))、キャビティ2の内側
壁に周状突起4bを形成したもの(3),6),9),12))
の3種類が示されている。回路素子10の側面形状は、
図1と同一形状のもの(1),2),3))、側面下端に凹段
部10aを形成したもの(4),5),6))、側面中央部に
突起10bを形成したもの(7),8),9))、側面中央部
に溝10cを形成したもの(10),11),12))の4種類
が示されている。いずれの場合も、段差部4で樹脂20
の流れを止め、中空部を確実に形成することができる。
FIG. 7 shows various combinations of the shape of the step portion 4 of the package 1 and the side surface shape of the circuit element 10. The shape of the step portion 4 is the same as that of FIG. 1 (1),
4), 7), 10)), those in which the circumferential groove 4a is formed on the inner wall of the cavity 2 (2), 5), 8), 11)), and the circumferential projection 4b is formed on the inner wall of the cavity 2. Things (3), 6), 9), 12))
3 types are shown. The side shape of the circuit element 10 is
1 (1), 2), 3)) with the same shape as in FIG. 1, a concave step 10a formed on the lower end of the side surface (4), 5), 6)), and a protrusion 10b formed on the central part of the side surface. (7), 8), 9)) and the one in which the groove 10c is formed in the central portion of the side surface (10), 11), 12)) are shown. In any case, the resin 20 is
The flow can be stopped and the hollow portion can be formed reliably.

【0020】本発明は上記実施例に限定されるものでは
ない。上記実施例では、バンプ15を回路素子10の電
極13に形成したが、バンプ15をパッケージ1の電極
パッド3上に形成してもよい。また、電極13と電極パ
ッド3の両者にバンプを形成し、バンプ同士を突き合わ
せて接合してもよい。上記実施例では、回路素子10の
上面をパッケージ1の上面より低くし、樹脂20が回路
素子10の側面および上面に塗布される例について説明
したが、回路素子10の上面をパッケージ1の上面とほ
ぼ同一高さまたはそれより高くしてもよい。この場合に
は、樹脂20を回路素子10の上面に塗布する必要はな
く、キャビティ2の内側壁と回路素子10の側面との環
状の隙間に塗布すればよい。本発明の回路素子は弾性表
面波素子に限るものではなく、下面に機能部と電極とを
持つ素子であれば、高周波素子や半導体素子など他の回
路素子であってもよいことは勿論である。ただし、弾性
表面波素子のように機能部がアルミニウムなどの腐食し
やすい電極で構成された素子の場合には、本発明の封止
構造が有効である。
The present invention is not limited to the above embodiment. In the above embodiment, the bump 15 is formed on the electrode 13 of the circuit element 10, but the bump 15 may be formed on the electrode pad 3 of the package 1. Alternatively, bumps may be formed on both the electrode 13 and the electrode pad 3, and the bumps may be abutted and joined to each other. In the above embodiment, the example in which the upper surface of the circuit element 10 is lower than the upper surface of the package 1 and the resin 20 is applied to the side surface and the upper surface of the circuit element 10 has been described, but the upper surface of the circuit element 10 is referred to as the upper surface of the package 1. It may be approximately the same height or higher. In this case, the resin 20 does not have to be applied to the upper surface of the circuit element 10, but may be applied to the annular gap between the inner wall of the cavity 2 and the side surface of the circuit element 10. The circuit element of the present invention is not limited to the surface acoustic wave element, and it goes without saying that it may be another circuit element such as a high frequency element or a semiconductor element as long as it is an element having a functional portion and an electrode on the lower surface. . However, the sealing structure of the present invention is effective in the case of an element such as a surface acoustic wave element whose functional portion is composed of an electrode such as aluminum which is easily corroded.

【0021】[0021]

【発明の効果】以上の説明で明らかなように、請求項1
に記載の発明によれば、回路素子の側面と対向するキャ
ビティの内側壁に、回路素子の側面との隙間が開口部側
より底部側の方が大きくなる段差部を実質的に全周に設
けたので、キャビティの開口部に流し込まれた樹脂は、
毛細管現象によってキャビティの内側壁と回路素子の側
面との隙間に流入するが、段差部によってキャビティの
内側壁と回路素子の側面との隙間が急拡大し、樹脂の流
れが止められる。そのため、樹脂が回路素子の下面側へ
流れ込むのが防止され、回路素子の下面とキャビティの
底面との間に安定して中空部を形成することができる。
回路素子の機能部に樹脂が付着しないので、樹脂の誘電
率や誘電損失によって回路素子の電気的特性が影響を受
けるのを防止できる。また、回路素子が振動子の場合で
あっても、特性に悪影響を与えない。また、回路素子の
側面とキャビティの内側壁との隙間が4辺でばらついて
も、段差部で樹脂の流れが確実に止められるので、樹脂
の浸入深さは段差部によって一定に維持される。そのた
め、封止性および固定強度が回路素子の周囲4辺で一定
となり、安定した性能の電子デバイスが得られる。さら
に、樹脂によって封止ができるので、パッケージに蓋を
接着する必要がなく、工程数を削減できるとともに、電
子デバイスの小型化,低背化が可能となる。
As is apparent from the above description, claim 1
According to the invention described in (3), a step portion whose gap between the side surface of the circuit element and the side surface of the circuit element is larger on the bottom side than on the opening side is provided substantially all around the inner side wall of the cavity facing the side surface of the circuit element. Therefore, the resin poured into the opening of the cavity is
Due to the capillary phenomenon, it flows into the gap between the inner wall of the cavity and the side surface of the circuit element, but due to the stepped portion, the gap between the inner wall of the cavity and the side surface of the circuit element expands rapidly, and the flow of resin is stopped. Therefore, the resin is prevented from flowing into the lower surface side of the circuit element, and the hollow portion can be stably formed between the lower surface of the circuit element and the bottom surface of the cavity.
Since the resin does not adhere to the functional portion of the circuit element, it is possible to prevent the electrical characteristics of the circuit element from being affected by the dielectric constant and the dielectric loss of the resin. Further, even when the circuit element is a vibrator, the characteristics are not adversely affected. Further, even if the gap between the side surface of the circuit element and the inner side wall of the cavity varies on the four sides, the resin flow is reliably stopped at the step portion, so that the resin penetration depth is kept constant by the step portion. Therefore, the sealing property and the fixing strength are constant on the four sides around the circuit element, and an electronic device with stable performance can be obtained. Further, since it can be sealed with resin, it is not necessary to attach a lid to the package, the number of steps can be reduced, and the electronic device can be downsized and the height can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明にかかる電子デバイスの一例の断面図で
ある。
FIG. 1 is a sectional view of an example of an electronic device according to the present invention.

【図2】図1に示す電子デバイスに用いられるパッケー
ジのいくつかの製造例の断面図である。
2 is a cross-sectional view of some manufacturing examples of a package used in the electronic device shown in FIG.

【図3】図1に示す電子デバイスに用いられる回路素子
の一例の斜視図である。
FIG. 3 is a perspective view of an example of a circuit element used in the electronic device shown in FIG.

【図4】図1に示す電子デバイスの製造工程図である。FIG. 4 is a manufacturing process diagram of the electronic device shown in FIG. 1.

【図5】段差位置による樹脂の流れ出しを示す分布図で
ある。
FIG. 5 is a distribution diagram showing the outflow of resin depending on the step position.

【図6】樹脂が段差部へ流れ出た状態を示す拡大図であ
る。
FIG. 6 is an enlarged view showing a state where resin flows out to a step portion.

【図7】パッケージの段差部形状と回路素子の側面形状
との種々の組み合わせを示す図である。
FIG. 7 is a diagram showing various combinations of a stepped shape of a package and a side surface shape of a circuit element.

【図8】従来の電子デバイスの断面図である。FIG. 8 is a cross-sectional view of a conventional electronic device.

【符号の説明】[Explanation of symbols]

1 パッケージ 2 キャビティ 3 電極パッド 4 段差部 10 回路素子 12 IDT電極(機能部) 13 入出力電極 15 バンプ 20 封止樹脂 21 中空部 1 package 2 cavities 3 electrode pad 4 step 10 circuit elements 12 IDT electrode (functional part) 13 Input / output electrodes 15 bumps 20 sealing resin 21 hollow

───────────────────────────────────────────────────── フロントページの続き (72)発明者 西川 悦生 京都府長岡京市天神2丁目26番10号 株式 会社村田製作所内   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Nishikawa Etsuo             Stock number 2 26-10 Tenjin, Nagaokakyo-shi, Kyoto             Murata Manufacturing Co., Ltd.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】下面に機能部と電極とを有する回路素子
と、この回路素子を収容し、底面に電極パッドが形成さ
れたキャビティを有するパッケージとを備え、上記回路
素子の電極とパッケージの電極パッドとをバンプにより
接続するとともに、回路素子とキャビティとの間を樹脂
で封止した電子デバイスにおいて、上記回路素子の側面
と対向するキャビティの内側壁に、回路素子の側面との
隙間が開口部側より底部側の方が大きくなる段差部が実
質的に全周に設けられ、上記樹脂は上記キャビティの開
口部から段差部までの範囲に充填・硬化され、上記回路
素子の下面とキャビティの底面との間に中空部が形成さ
れていることを特徴とする電子デバイス。
1. An electrode of the circuit element and an electrode of the package, comprising: a circuit element having a functional part and an electrode on a lower surface; and a package having the cavity for accommodating the circuit element and having an electrode pad formed on a bottom surface thereof. In an electronic device in which a pad is connected with a bump and a space between the circuit element and the cavity is sealed with a resin, a gap between the side surface of the circuit element and an opening is formed in an inner wall of the cavity facing the side surface of the circuit element. The step portion whose bottom side is larger than the bottom side is provided substantially all around, and the resin is filled and hardened in a range from the opening of the cavity to the step portion, and the lower surface of the circuit element and the bottom surface of the cavity. An electronic device characterized in that a hollow portion is formed between and.
【請求項2】上記回路素子の下面から段差部までの高さ
を0.1mm以下としたことを特徴とする請求項1に記
載の電子デバイス。
2. The electronic device according to claim 1, wherein the height from the lower surface of the circuit element to the step portion is 0.1 mm or less.
【請求項3】上記回路素子の上面は、キャビティの開口
部表面より低い位置にあり、上記樹脂は回路素子の上面
および回路素子の側面とキャビティの内側壁との間に充
填されていることを特徴とする請求項1または2に記載
の電子デバイス。
3. The upper surface of the circuit element is lower than the surface of the opening of the cavity, and the resin is filled between the upper surface of the circuit element and the side surface of the circuit element and the inner wall of the cavity. The electronic device according to claim 1 or 2, which is characterized.
【請求項4】下面に機能部と電極とを有する回路素子を
準備する工程と、上記回路素子を収容するため、底面に
電極パッドが形成されたキャビティを有し、上記回路素
子の側面と対向するキャビティの内側壁に、回路素子の
側面との隙間が開口部側より底部側の方が大きくなる段
差部が実質的に全周に設けられたパッケージを準備する
工程と、上記回路素子の電極上およびパッケージの電極
パッド上の少なくとも一方にバンプを形成する工程と、
上記回路素子の電極とパッケージの電極パッドとをバン
プにより接続する工程と、上記回路素子とキャビティと
の間を樹脂で封止する工程であって、上記回路素子の下
面とキャビティの底面との間に中空部を残した状態で、
上記樹脂を上記キャビティの開口部から段差部までの範
囲に充填し、硬化させる工程と、を有することを特徴と
する電子デバイスの製造方法。
4. A step of preparing a circuit element having a functional portion and an electrode on a lower surface, and a cavity having an electrode pad formed on a bottom surface for accommodating the circuit element, and facing a side surface of the circuit element. A step of preparing a package on the inner side wall of the cavity, in which the gap between the side surface of the circuit element is larger on the bottom side than on the opening side is provided on substantially the entire circumference; Forming bumps on at least one of the top and the electrode pads of the package,
A step of connecting the electrode of the circuit element and an electrode pad of the package with a bump, and a step of sealing the space between the circuit element and the cavity with a resin, wherein the lower surface of the circuit element and the bottom surface of the cavity are With the hollow part left in
Filling the range from the opening of the cavity to the stepped portion with the resin, and curing the resin.
JP2002018213A 2002-01-28 2002-01-28 Electronic device and method of manufacturing the same Pending JP2003218251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002018213A JP2003218251A (en) 2002-01-28 2002-01-28 Electronic device and method of manufacturing the same

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG110183A1 (en) * 2003-10-01 2005-04-28 Lintec Corp Process for producing resin-sealed type electronic device
JP2007142210A (en) * 2005-11-18 2007-06-07 Murata Mfg Co Ltd Electronic component
JP2007273585A (en) * 2006-03-30 2007-10-18 Sony Corp Micro device module and method of manufacturing same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG110183A1 (en) * 2003-10-01 2005-04-28 Lintec Corp Process for producing resin-sealed type electronic device
JP2007142210A (en) * 2005-11-18 2007-06-07 Murata Mfg Co Ltd Electronic component
JP2007273585A (en) * 2006-03-30 2007-10-18 Sony Corp Micro device module and method of manufacturing same

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