JP2003216486A - メモリの部分の割り当て管理方法 - Google Patents

メモリの部分の割り当て管理方法

Info

Publication number
JP2003216486A
JP2003216486A JP2002353401A JP2002353401A JP2003216486A JP 2003216486 A JP2003216486 A JP 2003216486A JP 2002353401 A JP2002353401 A JP 2002353401A JP 2002353401 A JP2002353401 A JP 2002353401A JP 2003216486 A JP2003216486 A JP 2003216486A
Authority
JP
Japan
Prior art keywords
memory
bus
address
module
processing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002353401A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003216486A5 (OSRAM
Inventor
Motoo Tanaka
モトオ・タナカ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2003216486A publication Critical patent/JP2003216486A/ja
Publication of JP2003216486A5 publication Critical patent/JP2003216486A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
JP2002353401A 2002-01-03 2002-12-05 メモリの部分の割り当て管理方法 Withdrawn JP2003216486A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/033,778 2002-01-03
US10/033,778 US6832303B2 (en) 2002-01-03 2002-01-03 Method and system for managing an allocation of a portion of a memory

Publications (2)

Publication Number Publication Date
JP2003216486A true JP2003216486A (ja) 2003-07-31
JP2003216486A5 JP2003216486A5 (OSRAM) 2006-01-12

Family

ID=21872383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002353401A Withdrawn JP2003216486A (ja) 2002-01-03 2002-12-05 メモリの部分の割り当て管理方法

Country Status (4)

Country Link
US (1) US6832303B2 (OSRAM)
JP (1) JP2003216486A (OSRAM)
KR (1) KR20030060071A (OSRAM)
SG (1) SG114582A1 (OSRAM)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200014162A (ko) * 2018-07-31 2020-02-10 에스케이하이닉스 주식회사 복수의 메모리 시스템의 연동을 위한 메타 데이터의 관리 방법 및 장치

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7133972B2 (en) 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
US7117316B2 (en) 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US6820181B2 (en) 2002-08-29 2004-11-16 Micron Technology, Inc. Method and system for controlling memory accesses to memory modules having a memory hub architecture
US7120727B2 (en) 2003-06-19 2006-10-10 Micron Technology, Inc. Reconfigurable memory module and method
US7260685B2 (en) * 2003-06-20 2007-08-21 Micron Technology, Inc. Memory hub and access method having internal prefetch buffers
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7330992B2 (en) * 2003-12-29 2008-02-12 Micron Technology, Inc. System and method for read synchronization of memory modules
US8250295B2 (en) 2004-01-05 2012-08-21 Smart Modular Technologies, Inc. Multi-rank memory module that emulates a memory module having a different number of ranks
US7188219B2 (en) * 2004-01-30 2007-03-06 Micron Technology, Inc. Buffer control system and method for a memory system having outstanding read and write request buffers
US7916574B1 (en) 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
US7346401B2 (en) * 2004-05-25 2008-03-18 International Business Machines Corporation Systems and methods for providing constrained optimization using adaptive regulatory control
US7519788B2 (en) 2004-06-04 2009-04-14 Micron Technology, Inc. System and method for an asynchronous data buffer having buffer write and read pointers
US7278006B2 (en) * 2004-12-30 2007-10-02 Intel Corporation Reducing memory fragmentation
US7418568B2 (en) * 2005-01-05 2008-08-26 Sap Ag Memory management technique
US20080270676A1 (en) * 2005-01-31 2008-10-30 Nxp B.V. Data Processing System and Method for Memory Defragmentation
US7516291B2 (en) * 2005-11-21 2009-04-07 Red Hat, Inc. Cooperative mechanism for efficient application memory allocation
US9311227B2 (en) * 2006-10-31 2016-04-12 Hewlett Packard Enterprise Development Lp Memory management
US8516185B2 (en) 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US8154901B1 (en) 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
US8001434B1 (en) 2008-04-14 2011-08-16 Netlist, Inc. Memory board with self-testing capability
US9251149B2 (en) * 2009-02-03 2016-02-02 Bmc Software, Inc. Data set size tracking and management
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
WO2012061633A2 (en) 2010-11-03 2012-05-10 Netlist, Inc. Method and apparatus for optimizing driver load in a memory package
PL3629123T3 (pl) 2013-07-27 2021-08-16 Netlist, Inc. Moduł pamięci z lokalną synchronizacją
US11249919B2 (en) * 2018-07-31 2022-02-15 SK Hynix Inc. Apparatus and method for managing meta data for engagement of plural memory system to store data
US11157207B2 (en) 2018-07-31 2021-10-26 SK Hynix Inc. Apparatus and method for engaging plural memory system with each other to store data
US11442628B2 (en) 2018-07-31 2022-09-13 SK Hynix Inc. Apparatus and method for engaging a plurality of memory systems with each other

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6334175B1 (en) * 1998-07-22 2001-12-25 Ati Technologies, Inc. Switchable memory system and memory allocation method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200014162A (ko) * 2018-07-31 2020-02-10 에스케이하이닉스 주식회사 복수의 메모리 시스템의 연동을 위한 메타 데이터의 관리 방법 및 장치
KR102733337B1 (ko) 2018-07-31 2024-11-25 에스케이하이닉스 주식회사 복수의 메모리 시스템의 연동을 위한 메타 데이터의 관리 방법 및 장치

Also Published As

Publication number Publication date
US20030126393A1 (en) 2003-07-03
US6832303B2 (en) 2004-12-14
KR20030060071A (ko) 2003-07-12
SG114582A1 (en) 2005-09-28

Similar Documents

Publication Publication Date Title
JP2003216486A (ja) メモリの部分の割り当て管理方法
US9223709B1 (en) Thread-aware cache memory management
US8850158B2 (en) Apparatus for processing remote page fault and method thereof
US9038079B2 (en) Reducing cross queue synchronization on systems with low memory latency across distributed processing nodes
US6643746B1 (en) Optimal multi-channel memory controller system
US5987565A (en) Method and apparatus for virtual disk simulation
EP3036642B1 (en) Hardware managed compressed cache
JP2000311156A (ja) 再構成可能並列計算機
US12287968B2 (en) Apparatus and method for sanitizing a shared memory device or a memory expander
US20110161608A1 (en) Method to customize function behavior based on cache and scheduling parameters of a memory argument
CN103577345A (zh) 提高由多个系统共享的存储高速缓存灵活性的方法和结构
CN113628647A (zh) 用于近数据处理的系统、方法和设备
EP2082323A1 (en) Reallocation of memory through global addressing
KR102865735B1 (ko) 시스템-온-칩에서 어드레스 디코딩을 핸들링하기 위한 장치 및 방법
JP2004127291A (ja) 連続したメモリ・アドレスを提供する方法、システムおよびコンピュータ・ソフトウェア
US6092136A (en) Multi-processor central processing unit
CN109542835A (zh) 用于使用多个存储器通道来降低平台中的加速器-存储器访问成本的技术
US6055547A (en) Shared file allocation and release
US7984240B2 (en) Memory compression implementation in a system with directly attached processor memory
JP2005353070A5 (OSRAM)
CN101135995A (zh) 用于从别名地址池中移除别名地址的方法和设备
US6338125B1 (en) Dynamic slot allocation and tracking of multiple memory requests
CN100594481C (zh) 允许运行在逻辑分区上的程序访问资源的方法与系统
US20030229721A1 (en) Address virtualization of a multi-partitionable machine
CN103649931B (zh) 用于支持由多个引擎执行指令序列的互连结构

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051116

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051116

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20080529