JP2003212695A - Method of manufacturing nitride-based compound semiconductor wafer, nitride-based compound semiconductor wafer, and nitride-based semiconductor device - Google Patents

Method of manufacturing nitride-based compound semiconductor wafer, nitride-based compound semiconductor wafer, and nitride-based semiconductor device

Info

Publication number
JP2003212695A
JP2003212695A JP2002008096A JP2002008096A JP2003212695A JP 2003212695 A JP2003212695 A JP 2003212695A JP 2002008096 A JP2002008096 A JP 2002008096A JP 2002008096 A JP2002008096 A JP 2002008096A JP 2003212695 A JP2003212695 A JP 2003212695A
Authority
JP
Japan
Prior art keywords
nitride
compound semiconductor
based compound
substrate
raw material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002008096A
Other languages
Japanese (ja)
Inventor
Tsuneaki Fujikura
序章 藤倉
Takamasa Suzuki
貴征 鈴木
Kazuyuki Iizuka
和幸 飯塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP2002008096A priority Critical patent/JP2003212695A/en
Publication of JP2003212695A publication Critical patent/JP2003212695A/en
Pending legal-status Critical Current

Links

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To grow a nitride-based compound semiconductor layer on a substrate having an uppermost layer of a nitride-based compound semiconductor without interposing an amorphous buffer layer while controlling the characteristics and the flatness of the surface. <P>SOLUTION: When a nitride-based compound semiconductor laminate structure (GaN layer 5) is grown on a substrate 4 having a nitride-based compound semiconductor single crystal layer 3 as the uppermost layer in a vapor phase without interposing a nitride-based compound semiconductor buffer layer grown at a low temperature between the uppermost layer and the nitride-based compound semiconductor laminate structure, the introduction of a group V raw material (ammonia) into a reaction furnace is firstly started and then the introduction of a group III raw material (TMG) is started. Thereby, the flatness and electrical and optical characteristics of the nitride-based compound semiconductor laminate structure are controlled. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、窒化物系化合物半
導体ウェハの製造方法および半導体ウェハならびに半導
体デバイスに関し、特に、GaN単結晶基板を含む最表
面に単結晶窒化物系化合物半導体層を有する基板上への
窒化物系化合物半導体積層構造の特性を制御した成長方
法と、これにより得られる窒化物系半導体ウェハおよび
窒化物系化合物半導体デバイスに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a nitride compound semiconductor wafer, a semiconductor wafer and a semiconductor device, and more particularly to a substrate having a single crystal nitride compound semiconductor layer on the outermost surface including a GaN single crystal substrate. The present invention relates to a growth method in which the characteristics of a nitride-based compound semiconductor laminated structure are controlled, and a nitride-based semiconductor wafer and a nitride-based compound semiconductor device obtained by the growth method.

【0002】[0002]

【従来の技術】GaN、AlGaN、InGaNなどの
窒化物系化合物半導体は、赤色から紫外線の発光が可能
な発光素子材料として注目を集めている。
2. Description of the Related Art Nitride-based compound semiconductors such as GaN, AlGaN, and InGaN have been attracting attention as light-emitting element materials capable of emitting red to ultraviolet light.

【0003】通常、窒化物系化合物半導体の成長はサフ
ァイア基板上へ行われる。この場合、サファイア基板と
窒化物系化合物半導体の間に、600℃以下の低温で成
長された窒化物系化合物半導体バッファ層を挿入するこ
とにより、サファイア基板と窒化物系化合物半導体の間
の格子不整合が緩和され、ある程度特性の良い窒化物系
化合物半導体が得られている。このため、サファイア基
板上への窒化物系化合物半導体の成長に関しては、これ
までに膨大な検討がなされ確立されている。
Usually, the growth of a nitride compound semiconductor is performed on a sapphire substrate. In this case, by inserting a nitride-based compound semiconductor buffer layer grown at a low temperature of 600 ° C. or lower between the sapphire substrate and the nitride-based compound semiconductor, a lattice mismatch between the sapphire substrate and the nitride-based compound semiconductor is obtained. A nitride-based compound semiconductor having relaxed matching and good characteristics to some extent has been obtained. For this reason, enormous studies have been made and established regarding the growth of the nitride compound semiconductor on the sapphire substrate.

【0004】しかしながら、窒化物系化合物半導体上へ
の窒化物系化合物半導体の成長に関しては、次に述べる
ように極めて重要な技術であるにも関わらず、未だ成熟
した技術とはなっていない。
However, the growth of a nitride compound semiconductor on a nitride compound semiconductor is not yet a mature technology, although it is an extremely important technology as described below.

【0005】窒化物系化合物半導体上への窒化物系化合
物半導体の成長の重要性を以下に述べる。
The importance of growing a nitride compound semiconductor on a nitride compound semiconductor will be described below.

【0006】サファイア上へ、低温成長バッファ層を用
いて窒化物系化合物半導体層を成長した場合、成長され
た窒化物系化合物半導体層は1010cm-2程度の欠陥を含
んでおり、この高密度の欠陥が最終的なデバイス特性に
与える悪影響は大きい。このため、近年GaN単結晶基
板が開発されているが、GaN単結晶基板の優れた結晶
性という利点を充分に活かすためには、その上へ高品質
な窒化物系化合物半導体層をエピタキシャル成長する技
術が不可欠である。
When a low temperature growth buffer layer is used to grow a nitride-based compound semiconductor layer on sapphire, the grown nitride-based compound semiconductor layer contains defects of about 10 10 cm -2. Density defects have a large negative effect on the final device characteristics. For this reason, a GaN single crystal substrate has been developed in recent years, but in order to fully utilize the advantage of the excellent crystallinity of the GaN single crystal substrate, a technique for epitaxially growing a high-quality nitride compound semiconductor layer thereon. Is essential.

【0007】また、サファイア基板上に窒化物系化合物
半導体エピタキシャル層を成長した構造を基板として、
その上に再成長する技術も非常に重要である。すなわ
ち、低温バッファ層を用いたサファイア基板上への窒化
物系化合物半導体の成長においては、高品質な窒化物系
化合物半導体層を得るための低温バッファ層部分の成長
条件は非常に微妙であり、わずかなバッファ層成長条件
の変化により、その上に成長する窒化物系化合物半導体
層の特性が大きな影響を受ける。このような不安定性は
窒化物系化合物半導体ウェハおよびデバイス製造におい
て、歩留まりの低下をもたらし、時には生産性を大幅に
低下させる原因となる。この不安定性を回避するために
は、サファイア基板上にあらかじめ低温バッファ層とそ
の上の窒化物系化合物半導体層を成長した構造を基板と
して準備しておき、この基板上に実際の素子構造を成長
する手法が効果的である。この際にも、窒化物系化合物
半導体上への窒化物系化合物半導体の成長が必要であ
る。
Further, a structure in which a nitride-based compound semiconductor epitaxial layer is grown on a sapphire substrate is used as a substrate.
Technology for regrowth on top of that is also very important. That is, in the growth of the nitride compound semiconductor on the sapphire substrate using the low temperature buffer layer, the growth conditions of the low temperature buffer layer portion to obtain a high quality nitride compound semiconductor layer are very delicate, A slight change in the growth conditions of the buffer layer greatly affects the characteristics of the nitride-based compound semiconductor layer grown thereon. Such instability causes a decrease in yield and sometimes a significant decrease in productivity in the production of nitride compound semiconductor wafers and devices. To avoid this instability, prepare a structure in which a low-temperature buffer layer and a nitride-based compound semiconductor layer are grown on a sapphire substrate in advance, and grow the actual device structure on this substrate. The method of doing is effective. Also in this case, it is necessary to grow the nitride compound semiconductor on the nitride compound semiconductor.

【0008】更に、サファイア基板上の窒化物系化合物
半導体の低欠陥化技術として開発されたELO(Epitax
ial Lateral Overgrowth)技術においても、サファイア
基板上のGaN層に開口部を有する絶縁体マスクを施
し、その上に再成長を行っている。
Furthermore, ELO (Epitax) developed as a technology for reducing defects in nitride compound semiconductors on a sapphire substrate
Also in the ial lateral overgrowth technology, an insulator mask having an opening is applied to the GaN layer on the sapphire substrate, and regrowth is performed thereon.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、窒化物
系化合物半導体上への窒化物系化合物半導体の成長技術
は未だ確立されているとは言いがたい。
However, it cannot be said that the technology for growing a nitride compound semiconductor on a nitride compound semiconductor has been established yet.

【0010】単結晶GaN基板上に、GaN非晶質層
(一般に600℃以下で成長される低温成長バッファ層
がこれに対応する)を形成した後にGaNのエピタキシ
ャル層をエピタキシャル成長する手法はすでに提案され
ている(特開2000−340509)。
A method of epitaxially growing an epitaxial layer of GaN after forming a GaN amorphous layer (which corresponds to a low temperature growth buffer layer generally grown at 600 ° C. or lower) on a single crystal GaN substrate has already been proposed. (Japanese Patent Laid-Open No. 2000-340509).

【0011】単結晶窒化物系化合物半導体基板を用いる
最大の利点は、高品質な単結晶基板の有する結晶として
の情報を、エピタキシャル層に引き継ぐことにより高品
質なエピタキシャル層が得られることに有るが、単結晶
基板とエピタキシャル層の間に非晶質層を挿入するこの
ような方法では、その利点が失われてしまう。
The greatest advantage of using a single crystal nitride compound semiconductor substrate lies in that a high quality epitaxial layer can be obtained by inheriting the information as a crystal of a high quality single crystal substrate into the epitaxial layer. In such a method of inserting the amorphous layer between the single crystal substrate and the epitaxial layer, the advantage is lost.

【0012】これに対して、非晶質バッファ層を介在し
ない形で、窒化物系化合物半導体上へ窒化物系化合物半
導体を成長する場合には、高品質な単結晶基板の有する
結晶としての情報を、エピタキシャル層に引き継ぐこと
により高品質なエピタキシャル層が得られるが、この場
合にも後述する実施例で示すように、基板の温度を成長
温度まで昇温する際の手順の違いにより窒化物系化合物
半導体成長層の特性および表面の平坦性が大きく変化す
る。
On the other hand, when a nitride-based compound semiconductor is grown on a nitride-based compound semiconductor without interposing an amorphous buffer layer, information as a crystal contained in a high-quality single crystal substrate is used. , A high-quality epitaxial layer can be obtained by transferring it to the epitaxial layer, and in this case as well, as shown in the examples described later, the nitride-based The characteristics of the compound semiconductor growth layer and the flatness of the surface change significantly.

【0013】そこで、本発明の目的は、上記課題を解決
し、非晶質バッファ層を介在しない形で、窒化物系化合
物半導体を最上層に有する基板上へ、窒化物系化合物半
導体層を、特性を制御しつつ、且つ表面の平坦性を制御
しつつ成長する方法と、これにより得られる半導体ウェ
ハおよび半導体デバイスを提供することにある。
Therefore, an object of the present invention is to solve the above problems and to provide a nitride-based compound semiconductor layer on a substrate having a nitride-based compound semiconductor as an uppermost layer without interposing an amorphous buffer layer, It is an object of the present invention to provide a method of growing while controlling the characteristics and the flatness of the surface, and a semiconductor wafer and a semiconductor device obtained by the method.

【0014】[0014]

【課題を解決するための手段】本発明者は、上記基板の
温度を成長温度まで昇温する際の手順の設計により、窒
化物系化合物半導体を最上層に有する基板上へ、窒化物
系化合物半導体層を、特性を制御しつつ、且つ表面の平
坦性を制御しつつ成長可能であることを見出し、次のよ
うな結論に至った。
The inventors of the present invention designed a procedure for increasing the temperature of the substrate to a growth temperature to design a nitride compound on a substrate having a nitride compound semiconductor as the uppermost layer. It was found that the semiconductor layer can be grown while controlling the characteristics and the flatness of the surface, and came to the following conclusions.

【0015】(1)電子デバイスおよび光デバイスのバ
ッファ層に好適な電気的・光学的特性の悪い(すなわ
ち、高抵抗で発光効率の低い)窒化物系化合物半導体層
を得るためには、III族原料を定常的に成長を行う温度
より1〜30℃低い温度、さらに好ましくは定常的に成
長を行う温度に達した後に反応炉へ導入する必要があ
る。また、定常的に成長を行う温度より300℃以上低
い温度でIII族原料を反応炉へ導入することでも、同様
に電気的・光学的特性の悪い窒化物系化合物半導体層を
得ることができる。
(1) In order to obtain a nitride-based compound semiconductor layer having poor electrical and optical characteristics (that is, high resistance and low emission efficiency) suitable for a buffer layer of an electronic device and an optical device, a group III group is required. It is necessary to introduce the raw material into the reaction furnace after reaching a temperature 1 to 30 ° C. lower than the temperature at which steady growth is carried out, and more preferably a temperature at which steady growth is carried out. Also, by introducing the Group III source material into the reaction furnace at a temperature lower than the temperature at which it grows steadily by 300 ° C. or more, a nitride-based compound semiconductor layer having similarly poor electrical and optical characteristics can be obtained.

【0016】(2)電気的・光学的特性の良い(すなわ
ち、低抵抗で発光効率の高い)窒化物系化合物半導体層
を得るためには、V族原料導入後で、且つ定常的に成長
を行う温度より30〜300℃低い温度、さらに好まし
くは定常的に成長を行う温度から80〜150℃低い温
度に達した後にIII族原料を反応炉へ導入する必要があ
る。
(2) In order to obtain a nitride-based compound semiconductor layer having good electrical and optical characteristics (that is, low resistance and high luminous efficiency), growth is constantly performed after the introduction of the group V raw material. It is necessary to introduce the Group III raw material into the reaction furnace after reaching a temperature 30 to 300 ° C. lower than the temperature to be performed, and more preferably a temperature 80 to 150 ° C. lower than the temperature at which steady growth is performed.

【0017】(3)表面の平坦性の良い窒化物系化合物
半導体層を得るためには、基板温度500℃以下でV族
原料を反応炉へ導入する必要がある。
(3) In order to obtain a nitride-based compound semiconductor layer having a good surface flatness, it is necessary to introduce the group V raw material into the reaction furnace at a substrate temperature of 500 ° C. or lower.

【0018】(4)光取り出し効率が高く表面発光型の
光デバイスに好適な、表面に1〜10nm程度の凸凹を
有する窒化物系化合物半導体層を得るためには、基板温
度500〜800℃でV族原料を反応炉へ導入する必要
がある。
(4) In order to obtain a nitride-based compound semiconductor layer having a surface unevenness of about 1 to 10 nm and having a high light extraction efficiency and suitable for a surface emitting type optical device, a substrate temperature of 500 to 800 ° C. It is necessary to introduce the group V raw material into the reaction furnace.

【0019】本発明において、典型的には、窒化物系化
合物半導体は一般式、BwAlxIn yGazabAsc
(w,x,y,z≧0、w+x+y+z=1、a>0,
b,c≧0、a+b+c=1)であらわされる。いくつ
か例を挙げると、BN、GaN、GaNAs、GaN
P、AlGaN、InGaN、InAlGaNなどであ
る。
In the present invention, a nitride-based material is typically used.
Compound semiconductor is general formula, BwAlxIn yGazNaPbAsc
(W, x, y, z ≧ 0, w + x + y + z = 1, a> 0,
b, c ≧ 0, a + b + c = 1). How many
For example, BN, GaN, GaNAs, GaN
P, AlGaN, InGaN, InAlGaN, etc.
It

【0020】本発明においては、典型的には、有機金属
化学気相成長法(MOVPE法)、あるいは、水素化物
気層成長法(HVPE法)により窒化物系化合物半導体
を気相成長させる。
In the present invention, typically, a nitride compound semiconductor is vapor-grown by a metal organic chemical vapor deposition method (MOVPE method) or a hydride vapor phase epitaxy method (HVPE method).

【0021】上述のように構成された本発明により、非
晶質バッファ層を介在しない形で、窒化物系化合物半導
体を最上層に有する基板上へ、窒化物系化合物半導体層
を特性を制御しつつ、且つ表面の平坦性を制御しつつ成
長する方法と、これにより得られる半導体ウェハおよび
半導体デバイスが提供される。
According to the present invention configured as described above, the characteristics of the nitride compound semiconductor layer are controlled on the substrate having the nitride compound semiconductor as the uppermost layer without interposing the amorphous buffer layer. While providing a method of growing while controlling the surface flatness, a semiconductor wafer and a semiconductor device obtained by the method are provided.

【0022】具体的には、本発明は次のように構成した
ものである。
Specifically, the present invention is configured as follows.

【0023】請求項1の発明に係る窒化物系化合物半導
体ウェハの製造方法は、最上層に窒化物系化合物半導体
単結晶層を有する基板上へ、その上の窒化物系化合物半
導体積層構造との間に600℃以下の温度で成長される
低温成長窒化物系化合物半導体バッファ層を介さずに、
窒化物系化合物半導体積層構造を気相成長するに際し、
先にV族原料の反応炉への導入を開始し、その後にIII
族原料の導入を開始することより、上記窒化物系化合物
半導体積層構造の平坦性・電気的・光学的特性を制御す
ることを特徴とする。
According to a first aspect of the present invention, there is provided a method for manufacturing a nitride-based compound semiconductor wafer comprising: a substrate having a nitride-based compound semiconductor single crystal layer as an uppermost layer; Without interposing a low temperature grown nitride compound semiconductor buffer layer grown at a temperature of 600 ° C. or less,
When vapor-depositing a nitride-based compound semiconductor laminated structure,
The introduction of Group V raw materials into the reactor was started first, and then III
It is characterized in that the flatness / electrical / optical characteristics of the nitride-based compound semiconductor laminated structure are controlled by starting the introduction of the group raw material.

【0024】請求項2の発明は、請求項1記載の窒化物
系化合物半導体ウェハの製造方法において、上記V族原
料の反応炉への導入を基板温度が500〜800℃の段
階で開始し、その後III族原料の供給を開始すること
で、表面に1〜10nm程度の凹凸を有する窒化物系化
合物半導体層を得ることを特徴とする。
According to a second aspect of the present invention, in the method for producing a nitride compound semiconductor wafer according to the first aspect, introduction of the group V raw material into the reaction furnace is started at a substrate temperature of 500 to 800 ° C. After that, the supply of the Group III raw material is started to obtain a nitride-based compound semiconductor layer having irregularities of about 1 to 10 nm on the surface.

【0025】請求項3の発明は、請求項1記載の窒化物
系化合物半導体ウェハの製造方法において、上記V族原
料の反応炉への導入を基板温度が室温〜500℃の段階
で開始し、その後III族原料の供給を開始することで、
表面の平坦性の良い窒化物系化合物半導体層を得ること
を特徴とする。
According to a third aspect of the present invention, in the method for producing a nitride compound semiconductor wafer according to the first aspect, introduction of the group V raw material into the reaction furnace is started at a stage where the substrate temperature is room temperature to 500 ° C., After that, by starting the supply of Group III raw materials,
A feature is that a nitride-based compound semiconductor layer having good surface flatness is obtained.

【0026】請求項4の発明は、請求項2又は3記載の
窒化物系化合物半導体ウェハの製造方法において、上記
III族原料の反応炉への導入をV族原料導入後、且つ基
板温度が上記窒化物系化合物半導体積層構造の実質的な
成長温度より0〜400℃低い段階(上記実質的な成長
温度を1100℃とした場合、1100℃〜700℃)
で開始することにより、上記窒化物系化合物半導体積層
構造の移動度およびホトルミネセンス発光強度を制御す
ることを特徴とする。
According to a fourth aspect of the present invention, in the method for manufacturing a nitride compound semiconductor wafer according to the second or third aspect,
After the introduction of the group III raw material into the reaction furnace and after the introduction of the group V raw material, and the substrate temperature is lower than the substantial growth temperature of the nitride-based compound semiconductor laminated structure by 0 to 400 ° C. (the above-mentioned substantial growth temperature is 1100). (1100 ° C to 700 ° C when measured in ° C)
It is characterized in that the mobility and the photoluminescence emission intensity of the above-mentioned nitride-based compound semiconductor laminated structure are controlled by starting with.

【0027】請求項5の発明は、請求項2又は3記載の
窒化物系化合物半導体ウェハの製造方法において、上記
III族原料の反応炉への導入をV族原料導入後、且つ基
板温度が上記窒化物系化合物半導体積層構造の実質的な
成長温度より30〜300℃低い段階(上記実質的な成
長温度を1100℃とした場合、1070℃〜800
℃)で開始することにより、上記窒化物系化合物半導体
積層構造の移動度およびホトルミネセンス発光強度を制
御することを特徴とする。
According to a fifth aspect of the present invention, in the method for producing a nitride compound semiconductor wafer according to the second or third aspect,
After the introduction of the group III raw material into the reaction furnace and after the introduction of the group V raw material, the substrate temperature is lower than the substantial growth temperature of the nitride-based compound semiconductor laminated structure by 30 to 300 ° C. (the substantial growth temperature is 1100 1070 ° C to 800 ° C
It is characterized in that the mobility and the photoluminescence emission intensity of the nitride-based compound semiconductor laminated structure are controlled by starting at (° C.).

【0028】請求項6の発明は、請求項2又は3記載の
窒化物系化合物半導体ウェハの製造方法において、上記
III族原料の反応炉への導入をV族原料導入後、且つ基
板温度が上記窒化物系化合物半導体積層構造の実質的な
成長温度より80〜150℃低い段階(上記実質的な成
長温度を1100℃とした場合、1020℃〜950
℃)で開始することにより、上記窒化物系化合物半導体
積層構造の移動度およびホトルミネセンス発光強度を制
御することを特徴とする。
According to a sixth aspect of the present invention, in the method of manufacturing a nitride compound semiconductor wafer according to the second or third aspect,
After the introduction of the group III raw material into the reaction furnace and after the introduction of the group V raw material, and the substrate temperature is lower than the substantial growth temperature of the nitride-based compound semiconductor stacked structure by 80 to 150 ° C. (the substantial growth temperature is 1100 ℃ 1020 ℃ -950
It is characterized in that the mobility and the photoluminescence emission intensity of the nitride-based compound semiconductor laminated structure are controlled by starting at (° C.).

【0029】請求項7の発明は、請求項4〜6のいずれ
かに記載の窒化物系化合物半導体ウェハの製造方法にお
いて、上記窒化物系化合物半導体積層構造を構成する窒
化物系化合物半導体が、一般式、BwAlxInyGaz
abAsc(w,x,y,z≧0、w+x+y+z=
1、a>0,b,c≧0、a+b+c=1)で表される
ことを特徴とする。
According to a seventh aspect of the present invention, in the method for manufacturing a nitride compound semiconductor wafer according to any one of the fourth to sixth aspects, the nitride compound semiconductor constituting the nitride compound semiconductor laminated structure is General formula, B w Al x In y Ga z N
a P b As c (w, x, y, z ≧ 0, w + x + y + z =
1, a> 0, b, c ≧ 0, a + b + c = 1).

【0030】請求項8の発明は、請求項4〜7のいずれ
かに記載の窒化物系化合物半導体ウェハの製造方法にお
いて、上記基板の最上層の窒化物系化合物半導体が、一
般式、BwAlxInyGazabAsc(w,x,y,
z≧0、w+x+y+z=1、a>0,b,c≧0、a
+b+c=1)で表されることを特徴とする。
According to an eighth aspect of the present invention, in the method for manufacturing a nitride-based compound semiconductor wafer according to any one of the fourth to seventh aspects, the uppermost nitride-based compound semiconductor of the substrate has a general formula, B w. al x In y Ga z N a P b As c (w, x, y,
z ≧ 0, w + x + y + z = 1, a> 0, b, c ≧ 0, a
+ B + c = 1).

【0031】請求項9の発明は、請求項4〜7のいずれ
かに記載の窒化物系化合物半導体ウェハの製造方法にお
いて、上記基板が一般式、BwAlxInyGazab
c(w,x,y,z≧0、w+x+y+z=1、a>
0,b,c≧0、a+b+c=1)で表される窒化物系
化合物半導体単結晶であることを特徴とする。
The invention of claim 9 is a method of manufacturing a nitride-based compound semiconductor wafer according to any one of claims 4-7, said substrate general formula, B w Al x In y Ga z N a P b A
s c (w, x, y, z ≧ 0, w + x + y + z = 1, a>
0, b, c ≧ 0, a + b + c = 1), which is a nitride-based compound semiconductor single crystal.

【0032】請求項10の発明は、請求項4〜7のいず
れかに記載の窒化物系化合物半導体ウェハの製造方法に
おいて、上記基板がサファイア等の窒化物系化合物半導
体以外の材料からなる基板上へ、一般式、BwAlxIn
yGazabAsc(w,x,y,z≧0、w+x+y
+z=1、a>0,b,c≧0、a+b+c=1)で表
される窒化物系化合物半導体単結晶層を成長したもので
あることを特徴とする。
According to a tenth aspect of the present invention, in the method for manufacturing a nitride compound semiconductor wafer according to any one of the fourth to seventh aspects, the substrate is a substrate made of a material other than a nitride compound semiconductor such as sapphire. To the general formula, B w Al x In
y Ga z N a P b As c (w, x, y, z ≧ 0, w + x + y
+ Z = 1, a> 0, b, c ≧ 0, a + b + c = 1), and a nitride compound semiconductor single crystal layer is grown.

【0033】請求項11の発明に係る窒化物系化合物半
導体ウェハは、上記請求項1〜10のいずれかに記載の
窒化物系化合物半導体ウェハの製造方法を用い、その窒
化物系化合物半導体積層構造が少なくともn形あるいは
p形の内の一種類の伝導形を有する層を含む構造とした
ことを特徴とする。
A nitride-based compound semiconductor wafer according to the invention of claim 11 uses the method for producing a nitride-based compound semiconductor wafer according to any one of the above-mentioned claims 1 to 10, and has a nitride-based compound semiconductor laminated structure. Has a structure including a layer having at least one conductivity type of n-type or p-type.

【0034】請求項12の発明に係る窒化物系化合物半
導体デバイスは、上記請求項11記載の窒化物系化合物
半導体ウェハを用いて製造したことを特徴とする。
A nitride compound semiconductor device according to a twelfth aspect of the present invention is characterized by being manufactured using the nitride compound semiconductor wafer according to the eleventh aspect.

【0035】[0035]

【発明の実施の形態】次に、本発明による窒化物系化合
物半導体ウェハの製造方法と、これにより得られる半導
体ウェハならびに半導体デバイス製造の実施形態につい
て、実施例を中心に説明する。なお、以下の実施例にお
ける成長装置としては、MOVPE(有機金属気相成
長)装置を使用した。
BEST MODE FOR CARRYING OUT THE INVENTION Next, a method for manufacturing a nitride compound semiconductor wafer according to the present invention, and an embodiment of manufacturing a semiconductor wafer and a semiconductor device obtained by the method will be described with a focus on Examples. A MOVPE (metalorganic vapor phase epitaxy) apparatus was used as the growth apparatus in the following examples.

【0036】<実施例1>以下の実施例では、図2に示
すように、c面サファイア基板1上にMOVPE法によ
り低温成長バッファ層2を介して高温で2ミクロンの膜
厚のアンドープGaN層3を成長した構造を基板4とし
て用いた。具体的には、MOVPE装置の反応炉内に
0.25度オフc面サファイア基板1を入れ、1200
℃で熱処理した後に、基板温度を500℃に下げ、In
GaNバッファ層2を20nmの厚さに成長する。次
に、基板温度を1100℃まで上昇した後に、アンドー
プGaN層3を2μm成長する。その後、アンモニア雰
囲気中で、基板温度を室温まで下げ、成長装置より取り
出した。
Example 1 In the following example, as shown in FIG. 2, an undoped GaN layer having a thickness of 2 μm at a high temperature is formed on a c-plane sapphire substrate 1 via a low temperature growth buffer layer 2 by MOVPE method. The structure obtained by growing 3 was used as the substrate 4. Specifically, the 0.25 degree off c-plane sapphire substrate 1 is put in the reaction furnace of the MOVPE apparatus, and 1200
After heat treatment at ℃, lower the substrate temperature to 500 ℃,
The GaN buffer layer 2 is grown to a thickness of 20 nm. Next, after raising the substrate temperature to 1100 ° C., an undoped GaN layer 3 is grown to 2 μm. Then, the substrate temperature was lowered to room temperature in an ammonia atmosphere, and the substrate was taken out from the growth apparatus.

【0037】上記のサファイア基板上のアンドープGa
Nを基板として用い、この上に図1に示す成長手順によ
りアンドープGaN層5の成長を行った。図1では、基
板温度およびV族原料であるアンモニア、III族原料で
あるトリメチルガリウム(TMG)の供給を、時間の関
数として示している。
Undoped Ga on the above sapphire substrate
Using N as a substrate, an undoped GaN layer 5 was grown on the substrate by the growth procedure shown in FIG. In FIG. 1, the substrate temperature and the supply of ammonia as a group V source and trimethylgallium (TMG) as a group III source are shown as a function of time.

【0038】MOVPE装置の反応炉内に「基板4」を
導入し、その直後にV族原料であるアンモニアを導入す
る。次に、先に導入したV族原料であるアンモニア雰囲
気中で、窒化物系化合物半導体積層構造の実質的な成長
温度1100℃まで加熱する。この昇温過程において基
板温度がある温度(Ts=700〜1100℃)に達し
た時点で、つまり実質的な成長温度より0〜400℃低
い段階(1100℃〜700℃)で、III族原料である
トリメチルガリウムTMGの供給を始め、アンドープG
aN層5の成長を開始する。
The "substrate 4" is introduced into the reaction furnace of the MOVPE apparatus, and immediately after that, ammonia which is a group V raw material is introduced. Next, in the atmosphere of the previously introduced group V raw material, ammonia, it is heated to a substantial growth temperature of 1100 ° C. of the nitride-based compound semiconductor laminated structure. In the temperature rising process, when the substrate temperature reaches a certain temperature (Ts = 700 to 1100 ° C.), that is, at a stage (1100 ° C. to 700 ° C.) lower than the substantial growth temperature by 0 to 400 ° C. Starting supply of certain trimethylgallium TMG, undoped G
The growth of the aN layer 5 is started.

【0039】その際の水素流量は10mol/分であ
り、アンモニア流量は0.4mol/分、TMG流量は
180μmol/分とした。この場合のアンドープGa
Nの成長速度は3600nm/時であり、成長時間を3
0分として1800nmのアンドープGaN層5を成長
した。すなわち、成長開始30分後にIII族原料である
トリメチルガリウムTMGの供給を停止し、アンモニア
雰囲気はそのまま維持したまま基板温度を室温まで下げ
た。
At this time, the hydrogen flow rate was 10 mol / min, the ammonia flow rate was 0.4 mol / min, and the TMG flow rate was 180 μmol / min. Undoped Ga in this case
The growth rate of N is 3600 nm / hour, and the growth time is 3
An undoped GaN layer 5 having a thickness of 1800 nm was grown for 0 minutes. That is, 30 minutes after the start of growth, the supply of trimethylgallium TMG, which is a Group III raw material, was stopped, and the substrate temperature was lowered to room temperature while maintaining the ammonia atmosphere as it was.

【0040】上記条件で成長したサンプルはいずれも平
坦性の高い表面を有していた。
The samples grown under the above conditions all had a highly flat surface.

【0041】図3に上記サンプルの室温におけるバンド
端ホトルミネセンス(PL)発光強度を、Tsの関数と
して示す。Ts=950〜1020℃の範囲(基板温度
が上記アンドープGaN層5の実質的な成長温度110
0℃より80〜150℃低い段階)でIII族原料である
トリメチルガリウムTMGの反応炉への導入を開始した
とき、最大のホトルミネセンス(PL)発光強度が得ら
れている。また、Ts=800〜950℃の範囲あるい
はTs=1020〜1070℃の範囲でも、最大値の1
/10程度のPL強度は得られている。Ts<800℃
(1100℃より300℃低い温度値よりも低い温度)
あるいは、Ts>1070℃(1100℃より30℃低
い温度値よりも高い温度)では、PL強度は非常に微弱
であった。
FIG. 3 shows the band edge photoluminescence (PL) emission intensity of the above sample at room temperature as a function of Ts. Ts = 950 to 1020 ° C. (Substrate temperature is substantially the growth temperature 110 of the undoped GaN layer 5)
The maximum photoluminescence (PL) emission intensity is obtained when the introduction of trimethylgallium TMG, which is a group III raw material, into the reaction furnace is started at a temperature lower than 0 ° C. by 80 to 150 ° C.). Further, even in the range of Ts = 800 to 950 ° C. or Ts = 1020 to 1070 ° C., the maximum value of 1
A PL intensity of about / 10 has been obtained. Ts <800 ℃
(Temperature lower than 300 ° C lower than 1100 ° C)
Alternatively, at Ts> 1070 ° C. (higher than the temperature value 30 ° C. lower than 1100 ° C.), the PL intensity was very weak.

【0042】<実施例2>「基板4」上に、実施例1と
同様な条件でシリコンドープGaN層を成長した。この
シリコンドープGaN層のホール測定により求めた電子
移動度をTsの関数として図4に示す。Ts=950〜
1020℃の範囲(実質的な成長温度1100℃より8
0〜150℃低い温度範囲)で最大の電子移動度約60
0cm2/Vsを示している。Ts=800〜950℃の
範囲および1020〜1070℃の範囲では、サンプル
の移動度に若干の減少は見られるが、なお伝導性を有し
ていた。
Example 2 A silicon-doped GaN layer was grown on the “substrate 4” under the same conditions as in Example 1. The electron mobility obtained by hole measurement of this silicon-doped GaN layer is shown in FIG. 4 as a function of Ts. Ts = 950
1020 ℃ range (effective growth temperature from 1100 ℃ to 8
Maximum electron mobility of about 60 in low temperature range of 0-150 ℃
It shows 0 cm 2 / Vs. In the range of Ts = 800 to 950 ° C. and the range of 1020 to 1070 ° C., although there was some decrease in the mobility of the sample, it was still conductive.

【0043】これに対して、Ts<800℃(1100
℃より300℃低い温度値よりも低い温度)あるいは、
Ts>1070℃(1100℃より30℃低い温度値よ
りも高い温度)で成長したサンプルは、高い抵抗を示し
た。Ts=950〜1020℃の範囲(実質的な成長温
度1100℃より80〜150℃低い温度範囲)で成長
したサンプルは、トランジスタ等の活性層として好適で
ある。また、Ts<800℃あるいは、Ts>1070
℃で成長した高抵抗層は、素子間の電気的な分離の目的
に使用可能である。
On the other hand, Ts <800 ° C. (1100
Temperature lower than 300 ° C lower temperature value) or
Samples grown with Ts> 1070 ° C. (higher than 30 ° C. below 1100 ° C.) showed high resistance. The sample grown in the range of Ts = 950 to 1020 ° C. (80 to 150 ° C. lower than the substantial growth temperature 1100 ° C.) is suitable as an active layer of a transistor or the like. Also, Ts <800 ° C. or Ts> 1070
The high resistance layer grown at ℃ can be used for the purpose of electrical isolation between devices.

【0044】<実施例3>図2の成長手順において、II
I族原料であるトリメチルガリウム(TMG)の反応炉
への導入開始温度を1000℃一定とし、V族原料であ
るアンモニアの反応炉への導入温度(Tv)を室温から
1000℃の間で変化させ、それ以外の条件は実施例1
と同じにして、アンドープGaNを成長した。
<Example 3> In the growth procedure of FIG.
The starting temperature for introducing trimethylgallium (TMG), which is a group I raw material, into the reaction furnace is kept constant at 1000 ° C, and the temperature (Tv) for introducing ammonia, which is a group V raw material, is changed from room temperature to 1000 ° C. The other conditions are in Example 1.
In the same manner as above, undoped GaN was grown.

【0045】これらのサンプル表面の粗さのrms値を
原子間力顕微鏡と表面粗さ計を用いて測定した結果を、
アンモニアの導入温度Tvの関数として図5に示す。T
v≦500℃の場合、試料表面の粗さのrms値は0.
5nm程度であり、非常に平坦である。V族原料である
アンモニアの反応炉への導入温度Tvが、Tv=500
〜800℃の間で、表面平坦性は徐々に劣化し、Tv>
800では表面の粗さのrms値が10nm程度になっ
ている。
The rms value of the roughness of these sample surfaces was measured using an atomic force microscope and a surface roughness meter, and
It is shown in FIG. 5 as a function of the introduction temperature Tv of ammonia. T
When v ≦ 500 ° C., the rms value of the roughness of the sample surface is 0.
It is about 5 nm and is very flat. The introduction temperature Tv of the group V raw material ammonia into the reaction furnace is Tv = 500
Surface flatness gradually deteriorates between ~ 800 ° C and Tv>
In 800, the rms value of the surface roughness is about 10 nm.

【0046】即ち本発明において、平坦な窒化物系化合
物半導体表面を得るためには、V族原料の反応炉への導
入温度Tvを、Tv≦500℃とする必要がある。ま
た、V族原料の反応炉への導入温度Tvを500〜80
0℃の間で変化させることにより、表面の粗さのrms
値を1〜10nmの間で制御することができる。
That is, in the present invention, in order to obtain a flat nitride-based compound semiconductor surface, the temperature Tv at which the group V source material is introduced into the reaction furnace must be Tv ≦ 500 ° C. Further, the temperature Tv for introducing the group V raw material into the reaction furnace is set to 500 to 80
Rms of surface roughness by varying between 0 ° C
The value can be controlled between 1 and 10 nm.

【0047】<実施例4>図6は、本発明による半導体
ウェハを用いた発光ダイオード(LED)の構造であ
る。実施例2で述べた「基板4」上に、シリコンをドー
プしたn−GaN層5を1100℃で成長し、その上に
シリコンドープしたn−InGaN層6を低温の800
℃で成長し、その後成長温度を再び1100℃まで上昇
しp−GaN層7を成長した。
<Embodiment 4> FIG. 6 shows the structure of a light emitting diode (LED) using a semiconductor wafer according to the present invention. A silicon-doped n-GaN layer 5 was grown at 1100 ° C. on the “substrate 4” described in Example 2, and a silicon-doped n-InGaN layer 6 was formed at a low temperature of 800 at 800.
The growth temperature was raised again to 1100 ° C. to grow the p-GaN layer 7.

【0048】上記の半導体ウェハ表面をRIE(Reacti
ve Ion Etching)により部分的に除去して、n−GaN
層5の一部を露出させ、露出した部分にTi/Al電極
8を形成する一方、p−GaN層7の表面にNi/Au
電極9を形成した。
RIE (Reacti
ve Ion Etching) to partially remove n-GaN
Part of the layer 5 is exposed and a Ti / Al electrode 8 is formed on the exposed part, while Ni / Au is formed on the surface of the p-GaN layer 7.
The electrode 9 was formed.

【0049】以上の実施例4の「基板4」上への再成長
を含む構成のLEDと、従来通りサファイア基板上への
連続成長により形成した構造を用いたLEDとを対象
に、その発光出力を測定したところ、20mA通電時の
光出力の平均が、実施例4の構成のLEDでは5mWで
あったのに対して、従来の連続成長による半導体ウェハ
を用いたLEDでは3mWであった。
The light emission output of the LED having the structure including the regrowth on the "substrate 4" of the above-mentioned Example 4 and the LED using the structure formed by continuous growth on the sapphire substrate as in the conventional case are targeted. Was measured, the average light output at the time of passing a current of 20 mA was 5 mW in the LED having the configuration of Example 4, whereas it was 3 mW in the LED using the semiconductor wafer by the conventional continuous growth.

【0050】これは、多数のLEDチップの平均である
ためこのような差がついたが、得られた最大の光出力で
比較すると、両者とも同等の7mWであった。本発明に
よる半導体ウェハを用いた実施例4の構成のLEDで
は、従来の連続成長による半導体ウェハを用いたLED
よりも、光出力のばらつきが小さいため、光出力の平均
値にこのような差がついているのである。
Since this is the average of a large number of LED chips, there was such a difference, but when comparing the obtained maximum optical outputs, both were equivalent to 7 mW. In the LED having the structure of Example 4 using the semiconductor wafer according to the present invention, the LED using the semiconductor wafer by the conventional continuous growth is used.
Since the variation of the light output is smaller than that of the above, the average value of the light output has such a difference.

【0051】すなわち、実施例4の構成のLEDでは、
LED特性のばらつきが従来より小さくでき、しかも、
LED特性としては従来形のLEDの最良の特性に近い
ものが得られるということである。
That is, in the LED having the structure of the fourth embodiment,
The variation of LED characteristics can be made smaller than before, and moreover,
The LED characteristics are similar to those of conventional LEDs.

【0052】[0052]

【発明の効果】以上説明したように、この発明による窒
化物系化合物半導体ウェハの製造方法によれば、先にV
族原料の反応炉への導入を開始し、その後にIII族原料
の導入を開始することより、非晶質バッファ層を介在し
ない形で、窒化物系化合物半導体を最上層に有する基板
上へ、高品質な窒化物系化合物半導体層、あるいは、高
抵抗で発光効率の低い窒化物系化合物半導体層を、特性
を制御しつつ、且つ平坦な表面を維持しつつ成長するこ
とができる。
As described above, according to the method for manufacturing a nitride compound semiconductor wafer according to the present invention, V
By starting the introduction of the group raw material into the reaction furnace, and then starting the introduction of the group III raw material, in a form without interposing the amorphous buffer layer, onto the substrate having a nitride-based compound semiconductor in the uppermost layer, A high-quality nitride-based compound semiconductor layer or a high-resistance nitride-based compound semiconductor layer with low luminous efficiency can be grown while controlling the characteristics and maintaining a flat surface.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による窒化物系化合物半導体ウェハの製
造方法による成長手順を示す図である。
FIG. 1 is a diagram showing a growth procedure according to a method for manufacturing a nitride-based compound semiconductor wafer according to the present invention.

【図2】本発明による窒化物系化合物半導体ウェハの製
造方法を説明するための基板及びその上の窒化物系化合
物半導体積層構造の断面図である。
FIG. 2 is a cross-sectional view of a substrate and a nitride-based compound semiconductor laminated structure thereon for explaining a method for manufacturing a nitride-based compound semiconductor wafer according to the present invention.

【図3】本発明の実施例1の基礎となるGaN層のバン
ド端発光強度とIII族原料導入温度Tsの関係を示す図
である。
FIG. 3 is a diagram showing the relationship between the band edge emission intensity of the GaN layer and the group III source material introduction temperature Ts, which is the basis of Example 1 of the present invention.

【図4】本発明の実施例2の基礎となるn−GaN層の
移動度とIII族原料導入温度Tsの関係を示す図であ
る。
FIG. 4 is a diagram showing the relationship between the mobility of an n-GaN layer and the group III source material introduction temperature Ts, which is the basis of Example 2 of the present invention.

【図5】本発明の実施例3の基礎となるGaN層の表面
粗さrms値とV族原料導入温度Tvの関係を示す図で
ある。
FIG. 5 is a diagram showing the relationship between the surface roughness rms value of a GaN layer and the group V source material introduction temperature Tv, which is the basis of Example 3 of the present invention.

【図6】本発明による半導体デバイスの構造を示す断面
図である。
FIG. 6 is a sectional view showing a structure of a semiconductor device according to the present invention.

【符号の説明】[Explanation of symbols]

1 サファイア基板 2 低温成長バッファ層 3 アンドープGaN層 4 基板 5 GaN層 6 InGaN層 7 GaN層 8、9 電極 1 sapphire substrate 2 Low temperature growth buffer layer 3 Undoped GaN layer 4 substrates 5 GaN layer 6 InGaN layer 7 GaN layer 8, 9 electrodes

───────────────────────────────────────────────────── フロントページの続き (72)発明者 飯塚 和幸 東京都千代田区大手町一丁目6番1号 日 立電線株式会社内 Fターム(参考) 4G077 AA03 BE15 DB08 ED06 EE06 EF02 HA02 TA04 TB05 TC11 TK08 5F041 AA40 CA34 CA40 CA46 CA65 5F045 AA04 AB14 AC08 AC12 AD11 AD12 AD13 AD14 AD15 AF04 BB01 BB07 BB16 CA09 DA53 DA57 EE00 EE12 EK26 5F073 CA07 CB05 DA05 DA35 EA29   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kazuyuki Iizuka             1-6-1, Otemachi, Chiyoda-ku, Tokyo             Standing Wire Co., Ltd. F term (reference) 4G077 AA03 BE15 DB08 ED06 EE06                       EF02 HA02 TA04 TB05 TC11                       TK08                 5F041 AA40 CA34 CA40 CA46 CA65                 5F045 AA04 AB14 AC08 AC12 AD11                       AD12 AD13 AD14 AD15 AF04                       BB01 BB07 BB16 CA09 DA53                       DA57 EE00 EE12 EK26                 5F073 CA07 CB05 DA05 DA35 EA29

Claims (12)

【特許請求の範囲】[Claims] 【請求項1】最上層に窒化物系化合物半導体単結晶層を
有する基板上へ、その上の窒化物系化合物半導体積層構
造との間に600℃以下の温度で成長される低温成長窒
化物系化合物半導体バッファ層を介さずに、窒化物系化
合物半導体積層構造を気相成長するに際し、 先にV族原料の反応炉への導入を開始し、その後にIII
族原料の導入を開始することより、上記窒化物系化合物
半導体積層構造の平坦性・電気的・光学的特性を制御す
ることを特徴とする窒化物系化合物半導体ウェハの製造
方法。
1. A low-temperature-grown nitride system grown on a substrate having a nitride-based compound semiconductor single crystal layer as an uppermost layer and at a temperature of 600 ° C. or lower between the substrate and the nitride-based compound semiconductor laminated structure on the substrate. When vapor-depositing a nitride-based compound semiconductor laminated structure without interposing a compound semiconductor buffer layer, introduction of a group V raw material into a reaction furnace is started first, and then III
A method for producing a nitride-based compound semiconductor wafer, comprising controlling the flatness, electrical and optical characteristics of the nitride-based compound semiconductor laminated structure by starting introduction of a group-based material.
【請求項2】上記V族原料の反応炉への導入を基板温度
が500〜800℃の段階で開始し、その後III族原料
の供給を開始することで、表面に1〜10nm程度の凹
凸を有する窒化物系化合物半導体層を得ることを特徴と
する請求項1記載の窒化物系化合物半導体ウェハの製造
方法。
2. The introduction of the group V raw material into the reaction furnace is started at a substrate temperature of 500 to 800 ° C., and then the supply of the group III raw material is started to form irregularities of about 1 to 10 nm on the surface. The method for producing a nitride-based compound semiconductor wafer according to claim 1, wherein the nitride-based compound semiconductor layer is obtained.
【請求項3】上記V族原料の反応炉への導入を基板温度
が室温〜500℃の段階で開始し、その後III族原料の
供給を開始することで、表面の平坦性の良い窒化物系化
合物半導体層を得ることを特徴とする請求項1記載の窒
化物系化合物半導体ウェハの製造方法。
3. A nitride system having good surface flatness by starting the introduction of the group V raw material into the reaction furnace at a stage where the substrate temperature is room temperature to 500 ° C. and then starting the supply of the group III raw material. The method for producing a nitride compound semiconductor wafer according to claim 1, wherein a compound semiconductor layer is obtained.
【請求項4】上記III族原料の反応炉への導入をV族原
料導入後、且つ基板温度が上記窒化物系化合物半導体積
層構造の実質的な成長温度より0〜400℃低い段階で
開始することにより、上記窒化物系化合物半導体積層構
造の移動度およびホトルミネセンス発光強度を制御する
ことを特徴とする請求項2又は3記載の窒化物系化合物
半導体ウェハの製造方法。
4. The introduction of the group III raw material into the reaction furnace is started after the introduction of the group V raw material and at a stage where the substrate temperature is 0 to 400 ° C. lower than the substantial growth temperature of the nitride compound semiconductor laminated structure. The method for producing a nitride compound semiconductor wafer according to claim 2 or 3, wherein the mobility and the photoluminescence emission intensity of the nitride compound semiconductor laminated structure are controlled thereby.
【請求項5】上記III族原料の反応炉への導入をV族原
料導入後、且つ基板温度が上記窒化物系化合物半導体積
層構造の実質的な成長温度より30〜300℃低い段階
で開始することにより、上記窒化物系化合物半導体積層
構造の移動度およびホトルミネセンス発光強度を制御す
ることを特徴とする請求項2又は3記載の窒化物系化合
物半導体ウェハの製造方法。
5. The introduction of the group III raw material into the reaction furnace is started after the introduction of the group V raw material and at a stage where the substrate temperature is lower than the substantial growth temperature of the nitride compound semiconductor laminated structure by 30 to 300 ° C. The method for producing a nitride compound semiconductor wafer according to claim 2 or 3, wherein the mobility and the photoluminescence emission intensity of the nitride compound semiconductor laminated structure are controlled thereby.
【請求項6】上記III族原料の反応炉への導入をV族原
料導入後、且つ基板温度が上記窒化物系化合物半導体積
層構造の実質的な成長温度より80〜150℃低い段階
で開始することにより、上記窒化物系化合物半導体積層
構造の移動度およびホトルミネセンス発光強度を制御す
ることを特徴とする請求項2又は3記載の窒化物系化合
物半導体ウェハの製造方法。
6. The introduction of the group III raw material into the reaction furnace is started after the introduction of the group V raw material and at a stage where the substrate temperature is lower than the substantial growth temperature of the nitride-based compound semiconductor laminated structure by 80 to 150 ° C. The method for producing a nitride compound semiconductor wafer according to claim 2 or 3, wherein the mobility and the photoluminescence emission intensity of the nitride compound semiconductor laminated structure are controlled thereby.
【請求項7】上記窒化物系化合物半導体積層構造を構成
する窒化物系化合物半導体が、一般式、BwAlxIny
GazabAsc(w,x,y,z≧0、w+x+y+
z=1、a>0,b,c≧0、a+b+c=1)で表さ
れることを特徴とする請求項4〜6のいずれかに記載の
窒化物系化合物半導体ウェハの製造方法。
7. The nitride-based compound semiconductor constituting the nitride-based compound semiconductor laminated structure has a general formula of B w AlxIn y.
Ga z N a P b As c (w, x, y, z ≧ 0, w + x + y +
z = 1, a> 0, b, c ≧ 0, a + b + c = 1)), The method for producing a nitride-based compound semiconductor wafer according to claim 4, wherein
【請求項8】上記基板の最上層の窒化物系化合物半導体
が、一般式、BwAlxInyGaz abAsc(w,
x,y,z≧0、w+x+y+z=1、a>0,b,c
≧0、a+b+c=1)で表されることを特徴とする請
求項4〜7のいずれかに記載の窒化物系化合物半導体ウ
ェハの製造方法。
8. A nitride-based compound semiconductor as an uppermost layer of the substrate
Is the general formula, BwAlxInyGazN aPbAsc(W,
x, y, z ≧ 0, w + x + y + z = 1, a> 0, b, c
≧ 0, a + b + c = 1)
8. The nitride-based compound semiconductor device according to any one of claims 4 to 7.
Manufacturing method.
【請求項9】上記基板が一般式、BwAlxInyGaz
abAsc(w,x,y,z≧0、w+x+y+z=
1、a>0,b,c≧0、a+b+c=1)で表される
窒化物系化合物半導体単結晶であることを特徴とする請
求項4〜7のいずれかに記載の窒化物系化合物半導体ウ
ェハの製造方法。
9. The substrate is of the general formula: B w Al x In y Ga z N
a P b As c (w, x, y, z ≧ 0, w + x + y + z =
1, a> 0, b, c ≧ 0, a + b + c = 1), which is a nitride-based compound semiconductor single crystal. 8. The nitride-based compound semiconductor according to claim 4, wherein Wafer manufacturing method.
【請求項10】上記基板がサファイア等の窒化物系化合
物半導体以外の材料からなる基板上へ、一般式、Bw
xInyGazabAsc(w,x,y,z≧0、w+
x+y+z=1、a>0,b,c≧0、a+b+c=
1)で表される窒化物系化合物半導体単結晶層を成長し
たものであることを特徴とする請求項4〜7のいずれか
に記載の窒化物系化合物半導体ウェハの製造方法。
10. A substrate of the general formula, B w A, on which the substrate is made of a material other than a nitride compound semiconductor such as sapphire.
l x In y Ga z N a P b As c (w, x, y, z ≧ 0, w +
x + y + z = 1, a> 0, b, c ≧ 0, a + b + c =
8. The method for manufacturing a nitride compound semiconductor wafer according to claim 4, wherein the nitride compound semiconductor single crystal layer represented by 1) is grown.
【請求項11】上記請求項1〜10のいずれかに記載の
窒化物系化合物半導体ウェハの製造方法を用い、その窒
化物系化合物半導体積層構造が少なくともn形あるいは
p形の内の一種類の伝導形を有する層を含む構造とした
ことを特徴とする窒化物系化合物半導体ウェハ。
11. The method for manufacturing a nitride compound semiconductor wafer according to claim 1, wherein the nitride compound semiconductor laminated structure has at least one of n-type and p-type. A nitride compound semiconductor wafer having a structure including a layer having a conductivity type.
【請求項12】上記請求項11記載の窒化物系化合物半
導体ウェハを用いて製造したことを特徴とする窒化物系
化合物半導体デバイス。
12. A nitride-based compound semiconductor device manufactured by using the nitride-based compound semiconductor wafer according to claim 11.
JP2002008096A 2002-01-17 2002-01-17 Method of manufacturing nitride-based compound semiconductor wafer, nitride-based compound semiconductor wafer, and nitride-based semiconductor device Pending JP2003212695A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002008096A JP2003212695A (en) 2002-01-17 2002-01-17 Method of manufacturing nitride-based compound semiconductor wafer, nitride-based compound semiconductor wafer, and nitride-based semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002008096A JP2003212695A (en) 2002-01-17 2002-01-17 Method of manufacturing nitride-based compound semiconductor wafer, nitride-based compound semiconductor wafer, and nitride-based semiconductor device

Publications (1)

Publication Number Publication Date
JP2003212695A true JP2003212695A (en) 2003-07-30

Family

ID=27646448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002008096A Pending JP2003212695A (en) 2002-01-17 2002-01-17 Method of manufacturing nitride-based compound semiconductor wafer, nitride-based compound semiconductor wafer, and nitride-based semiconductor device

Country Status (1)

Country Link
JP (1) JP2003212695A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010100699A1 (en) * 2009-03-06 2010-09-10 パナソニック株式会社 Crystal growth process for nitride semiconductor, and method for manufacturing semiconductor device
WO2010113423A1 (en) * 2009-04-03 2010-10-07 パナソニック株式会社 Method for growing crystals of nitride semiconductor, and process for manufacture of semiconductor device
JP2012142581A (en) * 2011-01-05 2012-07-26 Samsung Led Co Ltd Manufacturing method of light emitting diode and the light emitting diode manufactured by using the manufacturing method
JP2014183112A (en) * 2013-03-18 2014-09-29 Stanley Electric Co Ltd Method for manufacturing semiconductor light-emitting element
JP2015167201A (en) * 2014-03-04 2015-09-24 ウシオ電機株式会社 Method for manufacturing nitride semiconductor element
JP2016154237A (en) * 2007-11-21 2016-08-25 三菱化学株式会社 Crystal growth method and manufacturing method of light-emitting device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077417A (en) * 1999-08-31 2001-03-23 Sharp Corp Manufacture of nitride compound semiconductor light- emitting element
JP2003059835A (en) * 2001-08-13 2003-02-28 Sony Corp Method for growing nitride semiconductor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077417A (en) * 1999-08-31 2001-03-23 Sharp Corp Manufacture of nitride compound semiconductor light- emitting element
JP2003059835A (en) * 2001-08-13 2003-02-28 Sony Corp Method for growing nitride semiconductor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
A.R.A.ZAUNER ET AL.: "Homo-epitaxial GaN growth on exact and misoriented single crystals:suppression of hillock formation", JOURNAL OF CRYSTAL GROWTH, vol. 210, JPN4006023989, 2000, pages 435 - 443, XP004191355, ISSN: 0000798741, DOI: 10.1016/S0022-0248(99)00886-6 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016154237A (en) * 2007-11-21 2016-08-25 三菱化学株式会社 Crystal growth method and manufacturing method of light-emitting device
WO2010100699A1 (en) * 2009-03-06 2010-09-10 パナソニック株式会社 Crystal growth process for nitride semiconductor, and method for manufacturing semiconductor device
WO2010113423A1 (en) * 2009-04-03 2010-10-07 パナソニック株式会社 Method for growing crystals of nitride semiconductor, and process for manufacture of semiconductor device
CN102369590A (en) * 2009-04-03 2012-03-07 松下电器产业株式会社 Method for growing crystals of nitride semiconductor, and process for manufacture of semiconductor device
JP5641506B2 (en) * 2009-04-03 2014-12-17 パナソニックIpマネジメント株式会社 Nitride semiconductor crystal growth method and semiconductor device manufacturing method
JP2012142581A (en) * 2011-01-05 2012-07-26 Samsung Led Co Ltd Manufacturing method of light emitting diode and the light emitting diode manufactured by using the manufacturing method
JP2014183112A (en) * 2013-03-18 2014-09-29 Stanley Electric Co Ltd Method for manufacturing semiconductor light-emitting element
JP2015167201A (en) * 2014-03-04 2015-09-24 ウシオ電機株式会社 Method for manufacturing nitride semiconductor element

Similar Documents

Publication Publication Date Title
US7871845B2 (en) Nitride-based semiconductor light emitting device and method of manufacturing the same
US7001791B2 (en) GaN growth on Si using ZnO buffer layer
US20090001416A1 (en) Growth of indium gallium nitride (InGaN) on porous gallium nitride (GaN) template by metal-organic chemical vapor deposition (MOCVD)
US20050042789A1 (en) Method for producing nitride semiconductor, semiconductor wafer and semiconductor device
EP3107128B1 (en) Preparation method of a non-polar blue led epitaxial wafer based on lao substrate
CN106098871B (en) Preparation method of light-emitting diode epitaxial wafer
CN1996626A (en) Nitride-based light emitting devices and methods of manufacturing the same
JP2002170991A (en) Epitaxial growth of nitride compound semiconductor
JP4647723B2 (en) Nitride semiconductor crystal growth method and semiconductor device manufacturing method
US7368309B2 (en) Nitride semiconductor and fabrication method thereof
CN117410409A (en) Light-emitting diode
JPH11112030A (en) Production of iii-v compound semiconductor
US8878345B2 (en) Structural body and method for manufacturing semiconductor substrate
JP2003212695A (en) Method of manufacturing nitride-based compound semiconductor wafer, nitride-based compound semiconductor wafer, and nitride-based semiconductor device
JP2999435B2 (en) Semiconductor manufacturing method and semiconductor light emitting device
US9859457B2 (en) Semiconductor and template for growing semiconductors
JP2007103955A (en) Nitride semiconductor and method for growing nitride semiconductor crystal layer
JP2007134463A (en) Nitride semiconductor growth substrate and manufacturing method thereof
JP2007189028A (en) Manufacturing method of both p-type gallium nitride semiconductor and algainn light emitting device
JP2002075880A (en) Method for forming nitride-based semiconductor layer and method for manufacturing nitride-based semiconductor device
KR100822482B1 (en) Growing method for nitride based epitaxial layer and semiconductor device using the same
JP2000012979A (en) Method for manufacturing nitride semiconductor substrate
WO2020250849A1 (en) Semiconductor growth substrate, semiconductor element, semiconductor light-emitting element, and method for manufacturing semiconductor growth substrate
JP2004047762A (en) Method for manufacturing nitride semiconductor, semiconductor wafer, and semiconductor device
KR101282774B1 (en) Nitride based light emitting diode and method of manufacturing the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040220

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20040220

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061219

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070216

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20070216

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070403

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070420

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20070703