JP2003208147A - Character displaying circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To conduct Kanji (Chinese characters) display or graphic display employing an inexpensive and small scale circuit arrangement for a device in which character information is added to video signals and displayed. <P>SOLUTION: Kanji display and graphic display are superposed onto video by using an inexpensive OSC (on screen character display) IC and by providing a FIFO memory for a back stage to store characters (Kanji) and graphics to be displayed without arranging a large scale CRT control circuit. In other words, the character displaying circuit is provided with a synchronization separating circuit which takes out synchronization signals from the video signals, an OSD IC which conducts display control in synchronism with the synchronization signals, a clock signal generating circuit which generates clock signals, a FIFO memory which receives the clock signals and generates character display signals that are in synchronism with the video signals and a superimposing means which superimposed the character display signals onto the video signals, so that the character information is added to the video signals and displayed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to video signal processing for displaying character information on a video signal of a camera or the like.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional example of a character generation circuit for displaying on a CRT screen in addition to video information. In FIG.
Video signal A is input to input terminal 201 and
Given to. The amplifier 203 amplifies the input signal and outputs it as a video signal M to the separation circuit 204 and the video signal superposition circuit 210.

The sync separation circuit 204 converts the sync signal of the input video signal M into Hsync (HD) signal C and Vsync (V
D) CRT for taking out as signal D and controlling display
Output to the controller (CRT CTL) 101. The CRT controller 101 is, for example, HD64 manufactured by Hitachi, Ltd.
45. The CRT controller 101 outputs an address to the SRAM 102 so that the characters are generated in synchronization with the video signal A, and is stored in the character generator ROM 105 containing the character dot pattern and the ROM 106 containing the character border dot pattern. Output raster address.

The ROM 105 outputs the dot information (parallel information U) to the shift register 107, and the ROM 106 outputs
The dot information (parallel information V) for the shift register
Output to 108. The shift register 107 serially converts the dot information of the ROM 105 from the parallel information U and outputs it as the character signal K to the video signal superimposing circuit 210. Similarly, the shift register 108 serially converts the dot information of the ROM 106 from the parallel information V and outputs it as the edging signal L to the video signal superimposing circuit 210.

The video signal superimposing circuit 210 superimposes the character signal K and the edging signal L on the video signal M and outputs it to the amplifier 101 as a video signal N which is obtained by adding character information. Amplifier
101 amplifies the video signal N to a predetermined level and outputs it as a video signal P from an output terminal 202.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
CRT controller that controls large-scale character display 1
SRAM 102 that stores the information of 01 and characters displayed on the screen
And two large-capacity R of character information and edging information of the character
OM (or flash memory, etc.) 105, 106 must be provided, and control and tri-state buffer circuits 103 and 104 for switching these address and data buses in order to rewrite the contents of SRAM 102 are required. It has the disadvantage of large scale and high cost. In addition, it is conceivable to use inexpensive OSD ICs (ICs for on-screen character display) that are used in cameras for home appliances and VTRs in an attempt to reduce the scale of hardware and reduce costs, but these ICs cannot handle kanji. Or, it has the disadvantage that it can handle only very limited kanji. The object of the present invention is to eliminate the above drawbacks, to reduce the scale of hardware, to reduce the cost,
An object of the present invention is to provide a character display circuit with a limited number of characters and the number of characters.

[0007]

In order to achieve the above-mentioned object, the character display circuit of the present invention uses an inexpensive OSD IC to freely display Chinese characters or arbitrary figures while suppressing the hardware scale. It was made possible. That is, the character display circuit of the present invention includes a sync separation circuit that extracts a sync signal from a video signal, an OSD IC that performs display control in synchronization with the sync signal, a clock signal generation circuit that generates a clock signal, A FIFO memory that receives a clock signal to generate a character display signal in synchronization with the video signal, and a superimposing unit that superimposes the character display signal on the video signal are provided, and character information is added to the video signal for display. To do. Further, in the character display circuit of the present invention, the OSD IC has a fixed character type and the number of characters, the FIFO memory is coupled to the latter stage of the OSD IC, and the superimposing means displays the output of the FIFO memory as an image. It is to be superimposed on the signal.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram showing the configuration of a character display circuit according to an embodiment of the present invention. Sync separation circuit for the sync signal of video signal A input from input terminal 201 4
At the OSD as Hsync signal C and Vsync signal D.
It outputs to IC 1 for. For OSD that input this sync signal
The IC 1 controls the display, and receives the clock signal from the clock signal generation circuit 2 and outputs the character display signal J so as to generate the character in synchronization with the video signal A. The OSD IC 1 is, for example, μPD 6461 manufactured by NEC Corporation.

Referring now to FIGS. 1 and 3, the OSD
The operation of the IC for use is explained. FIG. 3 shows an embodiment of the present invention.
It is a figure for explaining operation of IC for OSD. For OSD
As shown in display 301 in Fig. 3, IC 3 is set to select a font in which one character range of 12 × 18 dots is shining and display it on the display.
An example is shown in which one Kanji is displayed using a 4-character range. When the scanning line of the video signal comes to the line in Fig. 3, the character display signal J in Fig. 1 is output and the AND circuit 5
And 6 are enabled and character information is output as K according to the output of FIFO memory 7. Video signal superposition circuit
When the character signal K is input to 10, the characters are superimposed on the video.

Further, referring to FIG. 4, an example in which a kanji character is displayed will be described below. FIFO memory here
The method of storing the character pattern in 7 is, for example, as shown in FIG.
Corresponding to, the character pattern to be displayed should be stored from address 0. Since what can be displayed is determined depending on the pattern stored in the FIFO memory 7, any figure can be displayed.

FIG. 6 is an example of a timing chart in the embodiment of FIGS. 1 and 3 to 5. J indicates the timing of the character display signal, and S indicates A input to the FIFO memory 7.
The output timing of the ND circuit 6 is shown, and K shows the timing of character information. Also, address is the address of FIFO memory 7. Further, in this embodiment, the FIFO memory 7 is 2
It is a bit, and the other bit contains edging information so that characters can be displayed with edging so that it is easy to see. The operation principle is the same as the above-mentioned character information. Furthermore, in the embodiment of FIG. 3 or FIG.
It consists of 4 characters (1 character: 12 x 18 dots), but it may be 1 character, 2 characters, 6 characters, etc.

[0012]

According to the present invention, an inexpensive home television or VTR can be obtained.
And IC for OSD and FIFO used in movie cameras
A kanji display circuit can be configured with memory, and graphic display is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional example.

FIG. 3 is a diagram for explaining the operation of the OSD IC according to the embodiment of the present invention.

FIG. 4 is a diagram showing a display state of characters.

FIG. 5 is a diagram illustrating address correspondence between a display screen and a FIFO memory.

FIG. 6 is a timing chart illustrating an example of the present invention.

[Explanation of symbols]

1: OSD IC, 2: Clock generation circuit, 5: AND circuit,
6: OR circuit, 7: FIFO memory, 8, 9: AND circuit,
10: Video signal superimposing circuit, 101: CRT controller, 1
02: SRAM, 103, 106: buffer, 105, 106: ROM,
107, 108: shift register, 201: input terminal, 20
2: Output terminal, 203, 211: Amplifier, 204: Sync separation circuit, 210: Video signal superimposing circuit, 301: Display.
A: Input video signal, B: Clock signal, C: Hsync signal, D: Vsync signal, E: CPU write signal, F: CPU
Data signal, G: CPU data bus, H: CPU port signal, I: CPU data signal, J: Character display signal output from OSD IC, K: Character signal, L: Border signal, M: Video signal, N: Video signal with characters and the border of characters superimposed, P: Video signal output, W: CPU address bus, X: SRAM address bus, Y: Address bus, T: SRAM data bus (EEPROM Address bus), U: parallel character information, V: parallel character border information.

Claims (2)

[Claims] 1. A sync separation circuit for extracting a sync signal from a video signal, and an OSD for performing display control in synchronization with the sync signal.
IC, a clock signal generation circuit that generates a clock signal, a FIFO memory that receives the clock signal and generates a character display signal in synchronization with the video signal, and a superimposes the character display signal on the video signal Equipped with a superposition means,
A character display circuit, wherein character information is added to the video signal and displayed. 2. The character display circuit according to claim 1, wherein the OSD IC has a fixed character type and the number of characters is fixed, the FIFO memory is coupled to a subsequent stage of the OSD IC, and the superimposing unit is configured to include the FIFO memory. A character display circuit characterized by superimposing the output of a memory on a video signal.