JP2003198298A - Clamp circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clamp circuit, capable of preventing semiconductor chip from becoming large-sized and clamping an input which exceeds the clamp potential by a large amount. <P>SOLUTION: The clamp circuit for clamping the voltage of an input terminal with a first transistor Q11 and a second transistor Q12 has a third transistor Q13, whose emitter is connected to a power source and collector and base are connected to the collector of the transistor Q12, and a fourth transistor Q14 whose emitter is connected to the power source, collector is connected to the collector of the transistor Q11 and the base is commonly connected to the base of the transistor Q13, to form a current mirror circuit. When the transistor Q12 is turned on, the collector current of the transistor Q14 is fed back positively to the base of the transistor Q11 and an emitter current of the transistor Q12 increases, and the input which exceeds the clamp current by a large amount can be clamped. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp circuit, and more particularly to a clamp circuit for clamping a signal voltage at a predetermined potential.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit, a voltage range of an input signal in which a circuit element normally operates is set. Therefore, the external input terminal of the semiconductor integrated circuit is provided with a clamp circuit for clamping the input signal outside the voltage range to the upper limit value or the lower limit value of the voltage range.

FIG. 1 shows a circuit diagram of an example of a conventional clamp circuit. In the figure, an external input terminal 10 is connected to an external signal source 12 via a resistor R1. The external input terminal 10 is connected to the resistor R2 in the semiconductor integrated circuit. The resistor R2 constitutes an input buffer together with the operational amplifier 14 and the resistor R3.

Further, the external input terminal 10 is connected to the emitter of the npn transistor Q2. The collector of the transistor Q2 is connected to the power supply Vcc, and the base of the transistor Q2 is connected to the base and collector of the npn transistor Q1 to form a current mirror configuration. The emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 is connected to the power source Vcc via the constant current source 16.
, And the transistors Q1 and Q2 and the constant current source 16 form a clamp circuit.

Here, when the input voltage of the external input terminal 10 is positive, the transistor Q2 is off, but when the potential of the external input terminal 10 becomes negative, the transistor Q2 is turned on and the emitter current of the transistor Q2 changes. By flowing through the resistor R1, the external input terminal 10 is clamped so as not to drop from the emitter potential of the transistor Q1 of approximately 0V.

[0006]

In the conventional clamp circuit, the emitter area ratio of the transistors Q1 and Q2 is 1: 1.
When the emitter current I1 of the transistor Q1 is 1 μA, the emitter current I1 of 1 μA is applied to the transistor Q1 even when the input voltage applied to the external input terminal 10 is positive.
And the potential of the external input terminal 10 becomes 0 V, the emitter current I2 of the transistor Q2 becomes 1 μA.

However, when a large negative voltage is applied to the external input terminal 10, the emitter current I2 of the transistor Q2 is increased.
2 is 1 μA, the potential of the external input terminal 10 cannot be clamped to 0 V as shown in FIG. 2, which causes a malfunction of the semiconductor integrated circuit.

Therefore, if the emitter currents of the transistors Q1 and Q2 are set to, for example, 100 μA, the potential of the external input terminal 10 can be clamped to 0 V as shown in FIG. 3, but it is constantly consumed by the transistor Q2. There was a problem that the current became large. Note that FIG.
In FIG. 3, the upper line shows the input voltage, the broken line shows the voltage of the external input terminal 10, and the lower line shows the emitter current I2 of the transistor Q2.

If the emitter area of the transistor Q2 is made larger than the emitter area of the transistor Q1, there is a problem that the construction area of the clamp circuit becomes large and the semiconductor chip becomes large.

The present invention has been made in view of the above points, and an object of the present invention is to provide a clamp circuit capable of preventing an increase in the size of a semiconductor chip and clamping an input that greatly exceeds the clamp potential.

[0011]

According to a first aspect of the invention, there is provided a first transistor (Q11, Q21) having a collector and a base connected to a constant current source, and a second transistor having an emitter connected to an input terminal. (Q12, Q22) forms a current mirror circuit, and in the clamp circuit for clamping the voltage of the input terminal, the emitter is connected to the power supply and the collector and the base are connected to the second transistor (Q
12, Q22) and a third transistor (Q13, Q23) connected to the collector, and an emitter connected to the power supply, a collector connected to the collector of the first transistor (Q11, Q21), and a base connected to the third transistor (Q1).
3, Q23) and a fourth transistor (Q14, Q24) commonly connected to form a current mirror circuit, so that when the second transistor (Q12, Q22) turns on, the collector of the fourth transistor (Q14, Q24) The current is positively fed back to the base of the first transistor (Q11, Q21) to increase the emitter current of the second transistor (Q12, Q22), and it becomes possible to clamp an input that greatly exceeds the clamp potential.

According to a second aspect of the present invention, in the clamp circuit according to the first aspect, the first and second transistors (Q11, Q21, Q12, Q22) are npn transistors, and the third and fourth transistors. (Q13, Q
Since 23, Q14, Q24) are pnp transistors, the voltage of the input terminal can be clamped to the ground potential.

According to a third aspect of the present invention, in the clamp circuit according to the first aspect, the first and second transistors (Q11, Q21, Q12, Q22) are pnp transistors, and the third and fourth transistors. (Q13, Q
Since 23, Q14, Q24) are npn transistors, the voltage of the input terminal can be clamped to the potential of the power supply.

It should be noted that the reference numerals in the above parentheses are given for easy understanding and are merely examples, and the present invention is not limited to the illustrated modes.

[0015]

FIG. 4 shows a circuit diagram of an embodiment of the clamp circuit according to the present invention. In the figure, the external input terminal 20 is connected to an external signal source 22 via a resistor R11.
Further, the external input terminal 20 is a resistor R1 in the semiconductor integrated circuit.
Connected to 2. The resistor R12 constitutes an input buffer together with the operational amplifier 24 and the resistor R13.

Further, the external input terminal 20 is connected to the emitter of the npn transistor Q12. The collector of the transistor Q12 is connected to the collector of the pnp transistor Q13, and the base of the transistor Q12 is np.
It is connected to the base and collector of the n-transistor Q11 to form a current mirror circuit. Transistor Q
The emitter of 11 is grounded, and transistor Q11
Is connected to the power supply Vcc via the constant current source 26 and is also connected to the collector of the pnp transistor Q14.

The base and collector of the transistor Q13 are connected to the base of the transistor Q14 to form a current mirror circuit, and the transistors Q13 and Q14 are provided.
Each emitter is connected to the power supply Vcc.

Here, when the input voltage of the external input terminal 20 is positive, the transistors Q12, Q13, Q14 are off, but when the potential of the external input terminal 20 becomes negative, the transistors Q12, Q13, Q14 are on. Then, the emitter current I2 of the transistor Q12 flows through the resistor R11, so that the external input terminal 20 is clamped so as not to drop from the emitter potential of the transistor Q11, which is approximately 0 V (clamp potential).

At this time, since the collector current of the transistor Q14 is positively fed back to the bases of the transistors Q11 and Q12 and amplified by the transistors Q11 and Q12, the emitter current I2 of the transistor Q12 is significantly larger than that in the conventional case (for example, It becomes larger (about 100 times).

Therefore, when the emitter area ratio of the transistors Q11 and Q12 is 1: 1 and the emitter current I1 of the transistor Q11 is 1 μA, when the input voltage applied to the external input terminal 20 is positive, the transistor Q11 has one.
An emitter current I1 of μA flows. That is, the normal current consumption is small.

When a large negative voltage is applied to the external input terminal 20, the emitter current I2 of the transistor Q12 is necessary for clamping the external input terminal 20 to about 0V by positively feeding back the emitter current of the transistor Q14. A current can be passed through the resistor R11 to clamp the potential of the external input terminal 20 to 0V as shown in FIG. This circuit is nothing more than the addition of two transistors to the conventional circuit, and there is almost no increase in the area of the semiconductor chip.

FIG. 6 shows a modification in which an operational amplifier 24 and a non-inverting amplifier are connected to the external input terminal 20 by resistors R11 and R14. The operation of the clamp circuit here is the same as that of FIG. 4, and the description thereof is omitted.

FIG. 7 shows a circuit diagram of another embodiment of the clamp circuit of the present invention. In the figure, the external input terminal 30 is a resistor R21.
Is connected to an external signal source 32 via. The external input terminal 30 is connected to the resistor R22 in the semiconductor integrated circuit. The resistor R22 is the operational amplifier 34 and the resistor R2.
3 together with 3 form an input buffer.

Further, the external input terminal 30 is connected to the emitter of the pnp transistor Q22. The collector of the transistor Q22 is connected to the collector of the npn transistor Q23, and the base of the transistor Q22 is pn.
It is connected to the base and collector of the p-transistor Q21 to form a current mirror circuit. Transistor Q
The emitter of 21 is connected to the power supply Vcc, the collector of the transistor Q21 is grounded via the constant current source 36, and is connected to the collector of the npn transistor Q24.

The base and collector of the transistor Q23 are connected to the base of the transistor Q24 to form a current mirror circuit, and the transistors Q23 and Q24 are provided.
Each emitter is grounded.

Here, when the input voltage of the external input terminal 30 is equal to or lower than the potential of the power source Vcc (referred to as the potential Vcc), the transistors Q22, Q23 and Q24 are off,
When the potential of the external input terminal 30 exceeds the potential Vcc, the transistors Q22, Q23, Q24 are turned on and the emitter current I2 of the transistor Q22 flows through the resistor R21, so that the external input terminal 30 becomes the potential Vcc which is the emitter potential of the transistor Q21. Clamp not to exceed (clamp potential).

At this time, the collector current of the transistor Q24 is positively fed back to the bases of the transistors Q21 and Q22 and amplified by the transistors Q21 and Q22, so that the emitter current of the transistor Q22 becomes significantly larger than that in the conventional case. When the external input terminal 30 greatly exceeds the potential Vcc, the emitter current of the transistor Q24 is positively fed back, so that the emitter current of the transistor Q22 supplies the resistor R21 with the current necessary to clamp the external input terminal 30 to the potential Vcc. Shed.

[0028]

As described above, the invention according to claim 1 is
A third transistor having an emitter connected to the power supply and a collector and a base connected to the collector of the second transistor; and an emitter connected to the power supply, a collector connected to the collector of the first transistor and a base commonly connected to the third transistor. With the fourth transistor forming the current mirror circuit, when the second transistor is turned on, the collector current of the fourth transistor is positively fed back to the base of the first transistor to increase the emitter current of the second transistor, thereby increasing the clamp potential. Clamping is possible for inputs that greatly exceed.

According to a second aspect of the present invention, the first and second transistors are npn transistors and the third and fourth transistors are pnp transistors, so that the voltage at the input terminal can be clamped to the ground potential. it can.

According to a third aspect of the invention, the first and second transistors are pnp transistors, and the third and fourth transistors are npn transistors, so that the voltage of the input terminal is clamped to the potential of the power supply. You can

[Brief description of drawings]

FIG. 1 is a circuit diagram of an example of a conventional clamp circuit.

FIG. 2 is a signal waveform diagram of each part of the circuit of FIG.

FIG. 3 is a signal waveform diagram of each part of the circuit of FIG.

FIG. 4 is a circuit diagram of an embodiment of a clamp circuit according to the present invention.

5 is a signal waveform diagram of each part of the circuit of FIG.

FIG. 6 is a circuit diagram of a modified example of the clamp circuit of the present invention.

FIG. 7 is a circuit diagram of another embodiment of the clamp circuit according to the present invention.

[Explanation of symbols]

20, 30 External input terminal 22,32 signal source 24,34 Operational amplifier 26,36 constant current source R11 to R14, R21 to R23 resistors Q11, Q12, Q23, Q24 npn transistors Q13, Q14, Q21, Q22 pnp transistor

Claims (3)

[Claims] 1. A clamp for forming a current mirror circuit with a first transistor having a collector and a base connected to a constant current source and a second transistor having an emitter connected to an input terminal, and clamping a voltage at the input terminal. A third transistor having an emitter connected to the power supply and a collector and a base connected to the collector of the second transistor; and an emitter connected to the power supply and a collector connected to the collector of the first transistor to a third base Fourth connection with a transistor to form a current mirror circuit
A clamp circuit having a transistor. 2. The clamp circuit according to claim 1, wherein the first and second transistors are npn transistors, and the third and fourth transistors are pnp transistors. 3. The clamp circuit according to claim 1, wherein the first and second transistors are pnp transistors, and the third and fourth transistors are npn transistors.