JP2003196041A - Printer, data transfer device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for transferring data in a bus width in a system even if there is a difference between a bit width of a bus for constituting the system and the bit number of a minimum unit of the data treated by a transmitter. <P>SOLUTION: An FIFO buffer 12C is constituted by using respectively independent four RAM modules 12C1, 12C2, 12C3, and 12C4 of an 8-bit width to a data bus of a 32-bit width, and the bus width is converted via a data bus selector. For example, since access can be simultaneously made to 4 bites (an oblique line part) with a third bit as the forefront from a start of reception, even if the minimum unit of the data treated by the transmitter is 8 bits, the data can be transferred in the 32-bit width of the data bus. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer technique, for example, a technique for efficiently transferring data in a data flow from a printer receiving data from a host computer to printing.

[0002]

2. Description of the Related Art In a data flow in which a printer receives data from a host computer, generates print data, and prints data, the data of the transmission source is transmitted in the process from receiving data to generating print data. Copying may be performed on the receiving side. In such a case, so-called direct memory access (hereinafter referred to as DMA) may be used regardless of the CPU in order to efficiently perform data transfer. In the transfer by DMA, the one-cycle transfer in which the data output to the transfer source is directly taken in by the receiving side is more efficient than the two-cycle transfer in which the data is read from the transfer source and the data is written. For example, when the minimum unit for transmission by the transmission source is 8 bits as in the case of data received from the host computer, generally, transfer is performed by 2-cycle or 1-cycle DMA in 8-bit units. A prominent example of such a transfer occurs when the data received from the host computer is transferred to the storage device of the printer.

[0003]

When the bus width in the system that constitutes the printer is, for example, 32 bits, it is necessary to transfer the data in a 32-bit width in order to efficiently move the data. Since the minimum unit of data handled on one side is 8 bits, even if the transmission source outputs 4 bytes each with a 32-bit width from the start of transmission, for example,
If one byte is not copied and is processed as control data, and it is necessary to copy again from the next byte, there is a discrepancy between 4 bytes from the transmission start of the sending side and 4 bytes from the reception start of the receiving side. Will occur. Therefore, in this case, there is a problem that the transfer with a 32-bit width cannot be performed.

An object of the present invention is to provide a technique for enabling transfer with the bus width in the system even if there is a discrepancy between the bit width of the bus that constitutes the system and the minimum number of bits of data handled by the transmission source. To do.

[0005]

[MEANS FOR SOLVING THE PROBLEMS] A reception data FIFO and a transmission data FIFO are provided in an interface transmission / reception module.
In the case of configuring, the FIFO can be realized by using a flip-flop instead of the RAM module, but since the gate scale becomes large, it is general to use the RAM. In that case, for example, if the bus width of the system is 32 bits, 32
Although it is general to construct a FIFO with a bit width RAM module, in order to solve the above problem, the present invention uses four 8-bit width independent RAM modules to convert the bus width via a bus selector. Was made possible.

When a RAM having a 32-bit width is used, for example, in the case of reception, one read of the RAM module always outputs data of 4 bytes each as 32 bits from the start of reception, so that, for example, 3 bytes from the start of reception. In order to output 4 bytes starting from the eye, that is, 3, 4, 5, and 6 bytes to the 32-bit bus, the interface RAM module must be read twice by changing the address, and the read timing cannot be met.

Similarly to the transmission FIFO, the transmission data is already 1
When writing to the transmission FIFO with a width of 32 bits while existing in the RAM module for byte transmission FIFO When using a 32-bit RAM, it is necessary to write to the RAM module in two steps by changing the address.
This can be solved by using four 8-bit RAMs. The above problem can be solved by providing a data bus selector to this.

According to the first aspect of the present invention, however,
In a printer including an interface unit that receives data in units of a predetermined number of bits (N bits) from a host and a printing unit that performs a predetermined printing process based on the data received from the host, the predetermined unit received from the host First data storage means for storing data in units of the number of bits (N bits) in the interface section, and the data stored in the first data storage means with the predetermined bit width (M bit width). And a second data storage unit for storing the data transferred by the transfer unit with the predetermined bit width (M bit width) in the printing unit, the first data storage unit. A printer is obtained in which the means is configured by using M / N memory modules each having the N-bit width and independent of each other.

Here, the transfer means may include a transfer control means and a bus having the predetermined bit width (M bit width).

The transfer means may be composed of a CPU and / or a DMA controller.

Further, the transfer means further allocates the data stored in the first data storage means to the bus having the predetermined bit width (M bit width) in units of the predetermined number of bits (N bits). And a bus selector for transferring to the second data storage means.

Further, the first data storage means may be composed of a first-in first-out (FIFO) buffer.

The data allocated to the predetermined bit width (M bit width) may be DMA-transferred from the first data storage means to the second data storage means.

On the other hand, according to the second aspect of the present invention, a receiving section for receiving the transferred data of a predetermined number of bits (N bits) and performing a predetermined receiving process, and a predetermined section by the receiving section. A data transfer device for outputting the data subjected to the reception process of 1., the first data storage means for storing the received data of a predetermined bit number (N bits) unit; Transfer means for transferring the data stored in the first data storage means to the output unit with a predetermined bit width (M bit width), and transfer with the predetermined bit width (M bit width) by the transfer means. A second data storage means for storing data, wherein the first data storage means is provided with an independent M / N of the N-bit width.
There is obtained a data transfer device characterized by being configured using a plurality of memory modules.

Here, the transfer means stores the bus having the predetermined bit width (M bit width) and the data stored in the first data storage means in units of the predetermined number of bits (N bits). A bus selector for allocating to a bus having a predetermined bit width (M bit width) and transferring the bus to the second data storage means may be included.

On the other hand, according to the third aspect of the present invention,
The receiving unit that receives the transferred data of a predetermined number of bits (N bits) and performs a predetermined receiving process, and the data that has been subjected to the predetermined receiving process by the receiving unit have a predetermined bit width (M bits). A data transfer method in a system having an output unit for outputting in a width), wherein the received N-bit unit data is stored in M / N memory modules independent of each other with the M-bit width. A data storage step, a transfer step of transferring the data stored in the first data storage step to the output unit via the M-bit width bus, and data transferred in the M-bit width by the transfer step. Is stored in the M bit width, and the data stored in the first data storing step is stored in the M bit unit in the M bit unit. Data transfer method and having a bus selection step for assigning the bus-wide is obtained.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a printer 200 according to the first embodiment of the present invention.

The illustrated printer 200 comprises a printer controller 10 and a print engine 20. The printer controller 10 includes an interface (hereinafter referred to as “host I / F”) 11 that receives print data and the like from the host computer 100, and a printer 20.
An input buffer 12A for temporarily storing print data input to 0, an output (image) buffer 12B for interpreting the print data stored in the input buffer 12A and developing it as image data for printing, various data processing ROM 13 storing routines for CPU and CPU
14 and a semiconductor integrated circuit (Applied) for a specific application including a print control circuit for sending head data and the like to the print head 22 side, various motor drivers, and the like.
Semiconductor integrated
A print control ASIC 15 including a circuit, hereinafter referred to as “ASIC”, and an interface (hereinafter referred to as “mechanical I / F”) 16 for transmitting image data, drive signals, and the like to the print engine 20. Host I / F 11, input buffer 12A, output (image) buffer 12B, ROM 13, CPU 1
4, the print control ASIC 15, the mechanical I / F 16 and the like are connected to each other by a bus 17.

The host I / F 11 includes a FIFO buffer 12C for temporarily storing data for transmission / reception with the host computer 100 and a data bus selector 11a in an interface control unit described later. The host I / F 11 has its FIFO buffer 12C.
A print command or data is received from the host computer 100. The input buffer 12A is a host I /
The print data received by the FIFO buffer 12C in the F11 is temporarily stored. In the output (image) buffer 12B, after analyzing the print command or data,
For example, raster graphics format image data is developed. The ROM 13 stores various control programs executed by the CPU 14 and the like. Also, R
The OM 13 also stores font data and graphic functions (not shown), various procedures, and the like. CPU14
It plays a central role in various controls in the printer 200 of the present embodiment.
The MA controller 14a is provided.

The print engine 20 includes a print head 22.
A carriage mechanism 24 and a paper feed mechanism 26. The paper feed mechanism 26 includes a paper feed motor, a paper feed roller, and the like, and sequentially feeds a print storage medium such as recording paper to perform sub scanning. The carriage mechanism 24 includes a carriage on which the print head 22 is mounted and a carriage motor that runs the carriage via a timing belt or the like, and causes the print head 22 to perform main scanning. The print head 22 has an inkjet nozzle row for each color, which is composed of a large number of 96 nozzles, for example, in the sub-scanning direction, and ejects ink droplets from each nozzle at a predetermined timing.

FIG. 2 shows a general printing system in which the host computer 100 and the printer 200 of this embodiment are connected. The graphics data captured by the host computer 100 via an image scanner (not shown) is transferred to the printer 20 by the printer driver 102 on the host computer 100 as shown in FIG.
Data that can be interpreted as 0 (control command and print data)
Is converted to. The converted data is stored in the operating system (hereinafter, referred to as “O”) on the host computer 100.
Host computer 1 managed by S) 104
00 interface unit (hereinafter referred to as I / F unit) 10
6 to the printer 200 via the connection cable 115.

In the printer 200, first, the data receiving section 222 in the interface control section (hereinafter referred to as the I / F control section) 220 receives the data, the data is stored in the reception buffer memory section 231 of the printing section 230, and then the data is received. The command interpreting unit 233 interprets the control command and the print data, the image data developing unit 235 develops the image data for printing, and the print processing execution unit 237 executes printing. The status of the printer such as the printer status is managed in real time by the status confirmation unit 239 in the printing unit 230, and is transferred to the host computer 100 as a host via the data transmission unit 224 in the I / F control unit 220. Transmitted. The I / F control unit 220 (the data receiving unit 222 and the data transmitting unit 224) mainly uses the F
In addition to the IFO buffer 12C and the data bus selector 11a, the host I / F 11 including a connector and a transceiver (not shown) and the CPU 14 are included. The reception buffer memory unit 231 in the printing unit 230 mainly includes the input buffer 12A and the CPU 14. The command interpreting unit 233 is mainly composed of a CPU.
14 and ROM 13 executed by the CPU 14
It is composed of a command interpreting program stored in. The image data expansion unit 235 is mainly composed of a CPU.
14 and an output (image) buffer 12B. The print processing execution unit 237 mainly includes the CPU 14 and the print control ASIC 15 in the printer controller 10.
And a mechanical I / F 16, a print head 22 in the print engine 20, a carriage mechanism 24, a paper feed mechanism 26, and the like. The state confirmation unit 239 is the CPU 1
4 and a control program executed by the CPU 14 and stored in the ROM 13 for printer status transmission and the like.

FIG. 3 shows the bus 17 in the above embodiment.
Via the I / F control unit 220 via the FIFO buffer 12
FIG. 6 is a diagram for explaining how data is transferred between C and an input buffer 12A. As shown in FIG. 3, the I / F control unit 220 according to the present embodiment uses the data bus 173.
In addition to the FIFO buffer 12C serving as a direct contact point for the data bus selector, the data bus selector 11a is provided. The data bus selector 11a includes an input buffer 12A and a FIF.
FIFO buffer 1 is provided between O buffer 12C and
By performing the first-in first-out control of 2C, for example, 1
It is a functional block that changes the connection destination for each byte.

The bus 17 also includes an address bus 171 and a control bus 172.

FIG. 4 is a diagram for explaining how data is transferred in the printer 200 having the above elements. Figure 4 (a)
When the FIFO buffer 12C ′ is composed of one RAM module having a 32-bit width, FIG. 4B shows that the FIFO buffer 12C has four 8-bit width independent Rs.
AM modules 12C1, 12C2, 12C3, 12C
In the case of the configuration using 4, the following are respectively shown.

An F for data reception is provided in the I / F control unit 220.
When the IFO buffer is configured using a RAM module, for example, if the bus width of the system, here, the bus 17 (data bus 173) in the printer controller 10 (see also FIGS. 1 and 2) is 32 bits wide. For example, conventionally, as shown in FIG. 4A, it is general to configure the FIFO buffer 12C ′ with one RAM module having a 32-bit width, but in the present embodiment, as shown in FIG. As shown, the FIFO buffer 12C is configured by using four RAM modules 12C1, 12C2, 12C3, 12C4 each having an 8-bit width, and the bus width conversion can be realized via the data bus selector 11a shown in FIG. I did it.

That is, as shown in FIG. 4A, if a 32-bit width RAM is used, for example, in the case of reception, the RAM
Since data of 4 bytes each from the start of reception is always output as 32 bits in one read of the module, for example, 4 bytes starting from the 3rd byte from the start of reception, that is, # 3, # 4, To output the # 5 and # 6 bytes to the data bus 173 having a width of 32 bits, refer to FIG.
As shown in (a) and (b), the interface RAM
The module (FIFO buffer 12C ') must be read twice by changing the address, which causes a problem that the read timing cannot be met in time.

On the other hand, in this embodiment, four independent RAM modules 12C1 each having an 8-bit width,
By using 12C2, 12C3, and 12C4 and providing the data bus selector 11a thereto, as shown in FIG. 4B, four bytes starting from the third byte from the start of reception, that is, # 3, # 4. , # 5, # 6 bytes can be accessed at the same time, the interface RAM module (FIFO buffer 12C) only needs to be accessed once, as shown in FIG. Absent.

Although the present invention has been described above with reference to specific embodiments, the present invention is not limited to these, and other embodiments are also applicable within the scope of the invention described in the claims. It

For example, in the above-described embodiment, the FIFO
The data temporarily stored in the buffer 12C is FIF.
Although the DMA transfer is performed from the O buffer 12C to the input buffer 12A, the CPU 14 uses the FIFO buffer 1
It is also possible to read from 2C and write to the input buffer 12A.

In the above embodiment, the case where the interface transmission / reception module is provided with the reception data FIFO has been described. However, the present invention can be similarly applied to the case where the transmission data FIFO is configured in the interface transmission / reception module. In this case, the present invention uses the transmission data FIFO from the main storage device or the like in the printer.
The present invention is applied to the case where data is transferred via, for example, a 32-bit wide data bus.

Further, the present invention is not limited to the above examples, and various printers and hosts (in the sense of a data input device to the printer, not only the host computer but also an image scanner, a digital camera, etc.) can be used. Applicable for data transfer.

[0033]

As is apparent from the above description, according to the present invention, even in a system having a data bus width of 32 bits, even after 8-bit transfer or 16-bit transfer of data or command is performed, Data can be transferred in a 32-bit width at any time.

In addition, in that case, it is possible to directly perform data transfer between the input / output control device of the computer and the internal storage device without processing for aligning the data to 32 bits in the CPU. It has become possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a printer according to an embodiment of the present invention.

FIG. 2 is a functional block diagram showing a flow of data processing including between a host and a printer in the printing system including the printer and the host computer shown in FIG.

FIG. 3 is a block diagram of a bus I according to an embodiment of the present invention.
FIG. 6 is a diagram for explaining how data is transferred between a FIFO buffer 12C and an input buffer 12A in the / F control unit 220.

FIG. 4 is a diagram for explaining how data is transferred in the printer according to the embodiment of the present invention. FIG. 4A shows a FIFO buffer with one 32-bit wide RAM module. If configured, (b)
Shows the case where the FIFO buffer is configured by using four independent RAM modules each having an 8-bit width.

FIG. 5 is a diagram for explaining how 4-byte data is transferred twice from a FIFO buffer to an input buffer in a conventional example. FIG. 5A is a first access to # 3. When the 1-byte data of # 3 is transferred from the FIFO buffer to the input buffer, (b) shows that the 3-byte data of # 4 to # 6 is FIFO by the second access.
The case where data is transferred from the buffer to the input buffer is shown.

FIG. 6 is a diagram for explaining how 4-byte data # 3 to # 6 is transferred from the FIFO buffer to the input buffer at one time in the embodiment of the present invention.

[Explanation of symbols]

10 Printer controller 11 Host I / F 11a Data bus selector 12A input buffer 12B output (image) buffer 12C FIFO buffer 13 ROM 14 CPU 14a DMA controller 15 Print control ASIC 16 Mechanical I / F 17 bus 20 print engine 22 Print head 24 Carriage mechanism 26 Paper feed mechanism 100 host computer 102 printer driver 104 Operating System (OS) 106 I / F section of host computer 100 171 address bus 172 control bus 173 data bus 200 printers 220 I / F control unit 222 Data receiver 224 Data transmission unit 230 Printing Department 231 Receive buffer memory unit 233 Command interpreter 235 Image data development unit 237 Print processing execution unit 239 Status confirmation section

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Claims (9)

[Claims] 1. A printer comprising: an interface unit for receiving data of a predetermined number of bits (N bits) from a host; and a printing unit for performing a predetermined printing process based on the data received from the host, A first data storage unit for storing data in a predetermined number of bits (N bits) unit received from the host in the interface unit; and data stored in the first data storage unit for a predetermined bit width (M bits). Width) to the printing unit, and the predetermined bit width (M bit width) by the transfer unit.
Second data storage means for storing the data transferred in the printing section in the printing section, the first data storage means using M / N memory modules each having the N-bit width and independent of each other. A printer characterized by being configured. 2. The printer according to claim 1, wherein the transfer unit includes a transfer control unit and the predetermined bit width (M
A printer characterized by comprising a bus (bit width). 3. The printer according to claim 2, wherein the transfer means comprises a CPU and / or a DMA controller. 4. The printer according to claim 3, wherein the transfer unit further sets the predetermined bit width (N bits) of the data stored in the first data storage unit to the predetermined bit width (N bits). A printer comprising: a bus selector for allocating to a bus of M bit width and transferring to the second data storage means. 5. The printer according to claim 1, wherein the first data storage means is a first-in first-out (FI).
A printer comprising a FO) buffer. 6. The printer according to claim 4, wherein the data allocated to the predetermined bit width (M bit width) is DMA-transferred from the first data storage means to the second data storage means. A printer characterized in that 7. A receiving unit for receiving the transferred data of a predetermined number of bits (N bits) and performing a predetermined receiving process, and data for which the predetermined receiving process is performed by the receiving unit are output. A data transfer device having an output unit for storing the received data in units of a predetermined number of bits (N bits), and data stored in the first data storage device. And a transfer means for transferring to the output unit with a predetermined bit width (M bit width), and the predetermined bit width (M bit width) by the transfer means.
Second data storage means for storing the data transferred by the above method, wherein the first data storage means is configured by using M / N memory modules each having the N-bit width and independent of each other. Characteristic data transfer device. 8. The transfer means according to claim 7, wherein the transfer means transfers the data stored in the bus of the predetermined bit width (M bit width) and the first data storage means to the predetermined number of bits ( A data transfer device comprising: a bus selector for allocating to the bus of the predetermined bit width (M bit width) in units of N bits and transferring the bus to the second data storage means. 9. A receiving unit that receives transferred data in units of a predetermined number of bits (N bits) and performs a predetermined receiving process, and a data that has been subjected to a predetermined receiving process by the receiving unit are predetermined. A data transfer method in a system having an output unit for outputting a bit width (M bit width), wherein the received N-bit unit data is transferred to the independent M / N memory modules at the M bit width. A first data storage step of storing, a transfer step of transferring the data stored by the first data storage step to the output unit via the M-bit width bus, and the M-bit width by the transfer step. The second data storage step of storing the data transferred by the M-bit width, and the data stored in the first data storage step by the N-bit width. Data transfer method and having a bus selection step for assigning the bus of said M bit wide units.