JP3700410B2 - Printer system and print control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printing system in which a host computer and a printer are connected by a peripheral bus such as a serial bus line. In particular, in a printing system in which a host computer and printer are connected by a peripheral bus such as a serial bus line, a mechanism is provided for transmitting data necessary for printing in real time according to the time interval of the band processed by the printer. The present invention relates to a printer system and a print control method that are capable of printing.
[0002]
[Prior art]
In recent printing systems, particularly color printing systems, the amount of data handled is increasing due to improvements in resolution of 600 dpi × 600 dpi or more. In order to meet the demand for system cost reduction, high-resolution color printers have taken measures to reduce memory by dividing the band and compressing and storing the decompressed data of each band. Also, there is a technology that aims to improve the processing performance at the same time by effectively using the host computer resources by taking over the part of the decomposing process that develops the page description language such as PDF and PostScript on the host computer connected to the printer. ing.
[0003]
However, in such a conventional printer system, since it is necessary to send intermediate data to the printer that is larger than the data size of the print data in the conventional page description language, that is, a part of the decomposing process is completed, the host computer and the printer The load of bus transfer connecting In addition, it is necessary to manage transfer processing for each band, which is a smaller unit than a page.
[0004]
[Problems to be solved by the invention]
Therefore, in a system using the above-described technology, conventionally, when transferring data between a host computer and a printer via a bus interface provided on the host computer, high-speed data at a small time interval as required. There was a problem that transfer performance could not be obtained. This is because communication between a host computer and a peripheral device such as a printer is managed by software called a device driver operating on the host in a bus such as an IEEE 1394 high-speed serial data bus or a USB (Universal Serial Bus) assumed here. This is because that.
[0005]
In addition, the above problem is further serious when the host computer OS is an OS that does not guarantee real-time performance, such as Windows 95 (Microsoft trademark) or Windows NT (Microsoft trademark) operating on an IBM compatible machine. Become.
[0006]
The present invention has been made in consideration of the above-described problems in the prior art. In a printing system in which a host computer and a printer are connected by a peripheral bus such as a serial bus line, the time of a band processed by the printer is obtained. An object of the present invention is to provide a mechanism for transmitting data necessary for printing at high speed in real time according to an interval or the like.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a printer system according to the present invention includes a host computer, a printer controller, a print engine, a parallel connecting the host computer and the printer controller, or a serial bus, and a parallel connecting the printer controller and the print engine. Alternatively, a printer system including a serial bus, a conversion unit that is provided in the host computer and converts print data described in a page description language into intermediate data in units of bands that are band-like areas in print output, and the host computer A DMA transfer circuit for transferring intermediate data in band units from the host computer to the printer control unit via a parallel or serial bus connecting the host computer and the printer control unit; A constant register that is provided inside the host computer and that stores constants based on the time required for the print engine to process an area corresponding to one band, and a storage value that is provided inside the host computer and loads the stored value from the constant register and prints A timer circuit that counts the time required for the engine to process an area corresponding to one band and activates the DMA transfer circuit; An expansion processing circuit that expands intermediate data transferred by the DMA transfer circuit provided in the printer control unit into bitmap data in band units, and bitmap data that is provided in the printer control unit and expanded by the expansion processing circuit in band units The print engine has an output circuit for outputting to the print engine via a parallel or serial bus connecting the printer control unit and the print engine.
[0009]
Further, the timer circuit in the printer system of the present invention is activated by a page synchronization signal input from the print engine.
[0011]
Further, the DMA circuit in the printer system according to the present invention is installed on the system bus of the host computer.
[0012]
Furthermore, the printer system of the present invention is configured such that intermediate data in band units is transferred from the host computer to the printer controller by the bus master transfer circuit via a parallel or serial bus connecting the host computer and the printer controller. ing.
[0013]
The print control method of the present invention further comprises a host computer, a printer control unit, a print engine, a parallel or serial bus connecting the host computer and the printer control unit, and a parallel or serial bus connecting the printer control unit and the print engine. In the print control method in the printer system, a conversion step that is executed inside the host computer and converts print data described in a page description language into intermediate data in units of bands that are band-like areas in print output; This is a step executed inside the host computer, and it is a DMA transfer that transfers intermediate data in band units from the host computer to the printer controller via a parallel or serial bus connecting the host computer and printer controller. And the step, A step that is executed using a timer circuit inside the host computer, and the print engine loads a stored value from a constant register that stores a constant based on the time required for the print engine to process an area corresponding to one band. The timer circuit counts the time required to process the area corresponding to one band, and based on the count, intermediate data is transferred from the host computer to the printer controller via the parallel or serial bus. Determining the timing of a DMA transfer step for performing data transfer; The steps executed in the printer control unit are a development processing step for developing intermediate data transferred by the DMA transfer circuit into bitmap data in band units, and a step executed in the printer control unit. An output step of outputting the bitmap data developed in the step to the print engine in a band unit to the print engine via a parallel or serial bus connecting the printer control unit and the print engine to the print engine.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Details of the printer system and the print control method of the present invention will be described below based on embodiments.
[0016]
[Example 1]
FIG. 1 is a diagram showing main components in an embodiment of a printer system of the present invention. FIG. 1A is a block diagram of the host computer. 1 is a processor, 2 is a cache memory, 3 is a bus control circuit, 4 is a main memory, 5 is a host bus, 6 is a system bus, 7 is a peripheral bus control circuit, 8 is a serial bus output buffer, 9 is a hard disk device, 10 Is an Ethernet I / F connector, 11 is a serial bus connector, 12 is a high-speed transfer control unit, 13 is a transfer control circuit A, 14 is a DMA circuit, and 15 is a timer circuit. FIG. 1B is a block diagram of the color printer. Reference numeral 16 denotes a serial bus connector, 17 denotes a printer control unit, 18 denotes a bus I / F circuit, 19 denotes a transfer control circuit B, 20 denotes a development processing circuit, 21 denotes an output circuit, and 22 denotes a print engine.
[0017]
The host computer in this embodiment is an IBM compatible PC system, and the processor 1 is an Intel Pentium compatible processor. The system bus 6 is a PCI bus. The host computer uses computer resources such as the processor 1, the cache memory 2, the bus control circuit 3, the main memory 4, the host bus 5, the system bus 6, the peripheral bus control circuit 7, the hard disk device 9, and the Ethernet I / F connector 10. Then, the print job sent via the network is spooled and the print job is accepted.
[0018]
Further, the host computer shown in FIG. 1A develops individual pages constituting the received print job into intermediate data to be transmitted to the printer by software processing including a plurality of processes as shown in FIG. And stored in areas on the main memory 4 and the hard disk device 9. Even in this process, the host computer makes effective use of the computer resources listed above.
[0019]
Various processes shown in FIG. 2 will be described. In FIG. 2, 100 is a spool unit, 101 is a language interpretation unit, 102 is a drawing processing unit, 103 is a band dividing unit, and 104 is a transfer processing unit. The spool unit 100 spools the print job and outputs it to the language interpretation unit 101. The language interpretation unit 102 interprets the input page description language and breaks it down into drawing commands corresponding to characters, figures, and images. The drawing processing unit 102 inputs and executes a drawing command, and generates intermediate data to be transmitted to the printer. The band decomposition unit 103 manages the intermediate data for each band by rearranging the order of the intermediate data for each band constituting the page. Here, the band is obtained by dividing a page into a plurality of strip-like regions by a straight line having an angle of 90 degrees with respect to the main scanning direction. The transfer processing unit 104 is responsible for processing to send intermediate data managed for each band to the printer.
[0020]
FIG. 3 is a diagram schematically showing a state in which intermediate data developed on the main memory 4 of the host computer is stored. The intermediate data of band 1 of the page currently being printed is stored in the area from address A to address B of the main memory 4. Similarly, the intermediate data of band 2 is stored in an area from address B to address C of the main memory 4. Thereafter, similarly, the intermediate data of the band is stored in the order of numbers, and finally the intermediate data of the maximum band N is stored in the area from the address Y to the address Z of the main memory 4.
[0021]
Address management of the main memory 4 is performed by the host computer, but the address in FIG. 3 indicates a physical address. The transfer processing unit 104 transfers the intermediate data stored in the main memory 4 shown in FIG. 3 to the printer control unit 17, which will be described below from the hardware configuration and operation. The transfer processing unit 104 operates as software on the processor 1, and data transfer is performed from a memory system including a register on the processor, a primary cache memory, a secondary cache memory 2, a main memory 4, and a hard disk device 9. Intermediate data is transferred to the printer control unit 17 via transfer control means such as a host bus, bus control circuit 3, system bus 6, peripheral bus control circuit 7, serial bus output buffer 8, serial bus connector 11, and high-speed transfer control unit 12. Forward.
[0022]
At this time, the processor 1 DMA-transfers intermediate data on the main memory 4 to the serial bus output buffer 8 using the high-speed transfer control unit 12. The purpose of using the high-speed transfer control unit 12 without the processor 1 relying on software means is that the print control unit 17 performs transfer in units of band processing time on the host computer, and that the bandwidth is reduced by DMA transfer. The guaranteed high-speed transfer is performed and the transfer processing is released from the processor 1 at the same time.
[0023]
Hereinafter, the transfer method using the high-speed transfer control unit 12 will be described in more detail. The transfer control unit 104 transfers the band-divided intermediate data shown in FIG. 3 to the printer control unit 17, which will be described below from the hardware configuration and operation.
[0024]
The transfer control unit 104 operates as software on the processor 1, and data transfer is performed from a memory system including a register on the processor, a primary cache memory, a secondary cache memory 2, a main memory 4, and a hard disk device 9. Intermediate data is transferred to the printer control unit 17 via transfer control means such as the host bus 5, bus control circuit 3, system bus 6, peripheral bus control circuit 7, serial bus output buffer 8, serial bus connector 11, and high-speed transfer control unit 12. Forward. At this time, the processor 1 DMA-transfers intermediate data on the main memory 4 to the serial bus output buffer 8 using the high-speed transfer control unit 12. The purpose of using the high-speed transfer control unit 12 without the processor 1 relying on software means is that the print control unit 17 performs transfer in units of band processing time on the host computer, and that the bandwidth is reduced by DMA transfer. The guaranteed high-speed transfer is performed and the transfer processing is released from the processor 1 at the same time.
[0025]
Hereinafter, the transfer method in the printer system of the present invention using the high-speed transfer control unit 12 will be described in more detail. FIG. 4 is a detailed block diagram of the high-speed transfer control unit 12. In FIG. 4, 131 is a band counter, 141 is a PCI bus I / F circuit, 142 is an address generation circuit, 143 is a FIFO buffer, 151 is a timer counter, and 152 is a constant register.
[0026]
FIG. 5 is an internal block diagram of the address generation circuit 142, where 1421 is an address register, 1422 is an address incrementer, and 1423 is a data counter. Prior to the transfer, the processor 1 initializes a register in the high-speed transfer control unit. Address register 1421 is set with the address of serial bus output buffer 8. The address incrementer 1422 is set with a physical address on the main memory in which intermediate data to be transferred is stored, for example, the address A in FIG. In the data counter 1423, the number of words of intermediate data transferred at a time, for example, the number of words from address A to address B in FIG. In the constant register 152, the time for the print engine 22 to print an area corresponding to one band, in other words, the time corresponding to the time Tb for the printer controller 17 to output dot data in the area corresponding to one band to the print engine 22 is displayed. A constant for counting: C (Tb) is set.
[0027]
If the count frequency of the timer counter is Fco,
Tb = C (Tb) * Fco
The relationship holds.
In the band counter 131, the number of band areas is set.
[0028]
For example, in a configuration in which a plurality of printers having different printing speeds are connected to a host computer and an output printer is selected as necessary and printing is performed, the printer control unit in each printer has an area corresponding to one band. The time Tb for outputting the dot data to the print engine has a different value, and therefore the constant: C (Tb) also differs for each printer. In such a system configuration, the output printer is identified, and the identified printer-specific constant: C (Tb) is set in the constant register 152.
[0029]
Hereinafter, the operation of the high-speed transfer control unit 12 will be described. The high-speed transfer control unit 12 stores the intermediate data on the main memory 4 in the FIFO buffer according to the master transfer mode of the PCI bus, and further transfers the intermediate data from the FIFO buffer to the serial bus output buffer 8 to transfer the intermediate data. Transfer to the printer controller at high speed.
[0030]
The transfer control circuit A13 (see FIG. 1) controls the flow of this transfer process, and performs transfer control according to the flowchart shown in FIG. The transfer control circuit A13 is first activated by the host computer. This is performed via the PCI bus I / F circuit 141. First, when data for the first two bands in step S0 shown in FIG. 6, for example, data is stored in the main memory as shown in FIG. 3, the band 1 intermediate data and the band 2 intermediate data are transferred to the printer control unit. The value of the band counter is decreased by 2. Next, in S1, status information of the printer control unit 17 is checked.
[0031]
In S2, if the printer engine start status is ON, the process proceeds to S3. If not, that is, if the printer engine start status is OFF, the process returns to S1. If the printer engine start status is ON, the value of the constant register 152 is loaded into the timer counter 151 in S3. Next, in S10, the value set in the address incrementer 1422 of the address generation circuit 142 is output to the PCI bus via the PCI bus interface circuit 141, whereby one word of data is transferred from the main memory 4 to the FIFO buffer 143. Forward. At the same time, the value set in the address incrementer 1422 is incremented by one. Next, in S11, the value of the data counter 1423 is decremented by one. In S12, it is checked whether or not the value held by the data counter 1423 is 0. If the value is 0, the process jumps to S14, and if not, the process proceeds to S13. In S13, it is checked whether or not the FIFO buffer 143 is Full. If Full, the process proceeds to S14. If not, the process returns to S10. In S14, data for one word is transferred from the FIFO buffer 143 to the serial bus output buffer 8 this time.
[0032]
Next, in S15, it is checked whether or not the FIFO buffer 143 is Empty. If it is Empty, the process proceeds to S16, and if not, the process returns to S14. In S16, it is checked whether or not the data counter 1423 is 0. If 0, the process proceeds to S17, and if not, the process returns to S10. In S17, since the data transfer for one band is completed, the value of the band counter 131 is decreased by one. In S18, the value of the band counter 131 is checked. If it is 0, the process ends. If not, the process proceeds to S19. In S19, it is checked whether the timer counter 151 is 0. If it is 0, the process returns to S3, and if not, S19 is executed again. The control flow executed by the high-speed transfer control unit 12 has been described above.
[0033]
On the other hand, on the printer control unit 17 side that receives data transfer from the host PC side, the bus I / F circuit 18 monitors the transfer protocol on the serial bus, and sends the sent data to the inside according to a predetermined procedure. Further, the received data is sent to the transfer control circuit 19.
[0034]
The transfer control circuit 19 takes the sent data into the buffer and outputs it to the decompression processing circuit 20, and the decompression processing circuit 20 decompresses the input intermediate data and stores it in the output buffer. The output circuit 21 outputs the data written in the output buffer to the print engine 22. This process will be described in more detail with reference to FIG. In FIG. 7, 190 is a control register and control unit, 191 is an input buffer A, 192 is an input buffer B, 200 is a development processing unit, 201 is an output buffer A, and 202 is an output buffer B.
[0035]
The operation will be described below with reference to detailed configurations of the transfer control circuit B19 and the expansion processing circuit 20. First, the control register and control unit 190 inputs a print start command from the host PC. Next, the input buffer A 191 and the input buffer B 192 sequentially input intermediate data corresponding to the first two bands from the bus I / F circuit. The input buffer A 191 sends intermediate data corresponding to the stored first band to the expansion processing unit 200. In the expansion processing unit 200, the input intermediate data is expanded into bitmap data and stored in the output buffer A201.
[0036]
When the expansion processing unit 200 finishes the expansion processing of the intermediate data in the input buffer A 191, the control register and control unit 190 sends an engine start signal to the print engine 22. Here, the control register and control unit 190 waits for a print operation start signal to be returned from the print engine 22. When the print operation start signal is returned, the transfer control circuit B19 and the expansion processing circuit 20 enter a steady operation mode.
[0037]
In the steady operation mode, the transfer control circuit B19 and the expansion processing circuit 20 repeat the basic operation cycle based on the time Tb allocated for the processing of one band. In the basic cycle, either the input buffer A 191 or the input buffer B 192 inputs and stores intermediate data for one band from the bus I / F circuit 18. Further, since the input buffer to which the intermediate data is not input from the bus I / F circuit 18 has already stored the intermediate data in the previous cycle, the intermediate data stored in the expansion processing unit 200 is already stored. Is output. The expansion processing unit 200 stores the expanded bitmap data in either the output buffer A 201 or the output buffer B 202. The output buffer that does not store the output from the expansion processing unit 200 has finished storing the bitmap data in the previous cycle, and outputs the stored data to the output circuit 21. When one Tb is finished and the next Tb is started, the relationship between the input buffer A / B and the output buffer A / B is reversed to perform the operation opposite to that described above. When such operation is repeated and the last output data is output to the output circuit 18, the control register and control unit 190 inputs an engine print operation end signal from the print engine unit 22.
[0038]
FIG. 8 is a diagram showing the transition of the value of the control bit in the control register and control unit 19. As shown in FIG. 8, the control bit is composed of three bits of Print, Engine Start, and Idle, and each value is 1, indicating printing, print engine operation, and print operation idle. First, in the state of FIG. 8I, the printer is not operating and is in an idle state, only the Idle bit is active, and the other bits are inactive. Here, when a print operation command is input from the host PC, the state transits to the state (II), the Print bit becomes active, and the Idle bit becomes inactive. In this state, the control register and control unit 190 transmits an engine start signal to the print engine 22 and receives an engine operation start signal from the print engine 22. Then, the state transits to the state of (III), and the Engine Start bit indicating that the print engine 22 is operating changes to active. Finally, when the engine print operation end signal is inputted, the state transits to the state (IV), the Print bit and the Engine Start bit become inactive, and the Idle bit changes to active.
[0039]
A timing chart of the above operation is shown in FIG. First, in the initial state, the control bits are (0, 0, 1), which is an idle state. When there is a print start command, the control bits become (1, 0, 0), and two bands of data are sequentially transferred. Thereafter, the development process for each band is executed, the print engine outputs a start signal, and the actual printing operation starts. When the printing operation starts, the control bit becomes (1, 1, 0), and the three processes of the intermediate data input, the input intermediate data expansion process, and the output process after the expansion process are completed as shown in FIG. Executed.
[0040]
In the output process, as described above, the processing time Tb is required for each band. Therefore, it is necessary for all the processes to proceed without causing a delay every time Tb. The transfer process and the expansion process do not need to take the same time as the time Tb, and may be completed within the time Tb. At the end of the output process, as shown in the lower part of FIG. 9, the intermediate data transfer process for the final band to be processed is first completed, and the final band development process is executed in the next Tb cycle. The output process is executed in the Tb cycle, and the entire print process is completed. When the printing process is completed, the control bit is changed to (0, 0, 1).
[0041]
As long as the DMA circuit 14 can control the PCI bus 6 or the system bus in the bus master mode, any of a CPU, a sequencer, and a state machine may be used instead. For example, data transfer between the host computer and the printer control unit may be controlled by a bus master transfer circuit that executes data transfer control by CPU control.
[0042]
In the above description, the timer counter is installed on the host computer, but there is no problem even if it is installed on the printer control unit. In particular, a cycle timer for supporting isochronous data transfer supported in IEEE 1394 may be substituted. Further, the DMA circuit 14 may be a multi-channel type DMA circuit including a plurality of DMA circuits. A plurality of DMA circuits may be connected in a daisy chain.
[0043]
【The invention's effect】
As described above, according to the present invention, in a printer system comprising a host computer, a printer, and a parallel or serial bus connecting the host computer and the printer, data is transferred from the host computer to the printer based on the band information of the printer. By having the DMA transfer circuit or bus master circuit activated as described above, it is possible to transmit data necessary for printing at high speed in real time according to the time interval of the band processed by the printer. is there. Further, since the timer circuit for starting the DMA transfer circuit is included and the timer circuit counts a predetermined band processing time, there is an effect that DMA transfer can be started at every band time interval.
[0044]
Further, since the timer circuit is started by the page synchronization signal input from the print engine, there is an effect that the DMA transfer can be performed accurately in synchronization with the print engine. Further, since the DMA transfer circuit is provided on the system bus of the host computer, the DMA transfer circuit can directly access the main memory of the host computer system.
[0045]
Further, when transfer is performed by connecting a plurality of DMA circuits in a daisy chain and operating, even if a data area to be transferred in the main memory 4 becomes discontinuous, the DMA transfer is not interrupted. There is an effect that DMA transfer can be performed at high speed and at high speed.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a main configuration in an embodiment of a print system according to the present invention.
FIG. 2 is a diagram showing a configuration of decompression software on a host computer of the printing system of the present invention.
FIG. 3 is a diagram showing a band configuration of intermediate data developed in a virtual memory space of the printing system of the present invention.
FIG. 4 is a diagram illustrating an internal configuration of a DMA circuit in the print system of the present invention.
FIG. 5 is a diagram illustrating an internal configuration of a timer circuit in the print system of the present invention.
FIG. 6 is a flowchart illustrating a control flow executed by a transfer control circuit A in the print system of the present invention.
FIG. 7 is a diagram illustrating an internal configuration of a transfer control circuit B and a development processing circuit in the print system of the present invention.
FIG. 8 is a diagram illustrating state transitions of control bits in the print system of the present invention.
FIG. 9 is a timing chart illustrating an operation of a print control unit in the print system of the present invention.
[Explanation of symbols]
1 processor
2 Cache memory
3 Bus control circuit
4 Main memory
5 Host bus
6 PCI bus
7 Peripheral bus control circuit
8 Output buffer
9 Hard disk device
10 Ethernet I / F connector
11 Serial bus connector
12 High-speed transfer controller
13 Transfer control circuit A
14 DMA circuit
15 Timer circuit
16 Serial bus connector
17 Printer control unit
18 Bus I / F circuit
19 Transfer control circuit B
20 Development processing circuit
21 Output circuit
22 Print Engine
100 spool part
101 Language interpretation part
102 Drawing processing unit
103 Band division part
104 Transfer processing unit
105 Intermediate data
131 band counter
141 PCI bus I / F circuit
142 Address generation circuit
143 FIFO buffer
144 Internal bus
151 Timer counter
152 Constant register
190 Control register and control unit
191 Input buffer A
192 Input buffer B
200 Deployment processing unit
201 Output buffer A
202 Output buffer B
1421 Address register
1422 Address incrementer
1423 Data counter

Claims (7)

In a printer system comprising a host computer, a printer control unit, a print engine, a parallel or serial bus connecting the host computer and the printer control unit, and a parallel or serial bus connecting the printer control unit and the print engine,
A conversion unit that converts print data provided in the host computer and described in a page description language into intermediate data in band units that are band-like regions in print output;
DMA transfer provided in the host computer for transferring the intermediate data in units of bands from the host computer to the printer controller via the parallel or serial bus connecting the host computer and the printer controller. Circuit,
A constant register that is provided inside the host computer and stores a constant based on the time required for the print engine to process an area corresponding to one band;
A timer circuit that is provided inside the host computer, loads a stored value from the constant register, counts the time required for the print engine to process an area corresponding to one band, and activates the DMA transfer circuit;
A development processing circuit provided in the printer control unit for developing the intermediate data transferred by the DMA transfer circuit into bitmap data in units of bands;
The bitmap data provided in the printer control unit and developed by the development processing circuit is output to the print engine in units of bands to the print engine via the parallel or serial bus connecting the printer control unit and the print engine. An output circuit to
A printer system comprising: The printer system according to claim 1 , wherein the timer circuit is activated by a page synchronization signal input from the print engine.   The printer system according to claim 1, wherein the DMA transfer circuit is installed on a system bus of the host computer. In a printer system comprising a host computer, a printer control unit, a print engine, a parallel or serial bus connecting the host computer and the printer control unit, and a parallel or serial bus connecting the printer control unit and the print engine,
A conversion unit that converts print data provided in the host computer and described in a page description language into intermediate data in band units that are band-like regions in print output;
Bus master transfer provided in the host computer for transferring the intermediate data in the band unit from the host computer to the printer control unit via the parallel or serial bus connecting the host computer and the printer control unit Circuit,
A constant register that is provided inside the host computer and stores a constant based on the time required for the print engine to process an area corresponding to one band;
A timer circuit that is provided inside the host computer, loads a stored value from the constant register, counts the time required for the print engine to process an area corresponding to one band, and activates the bus master transfer circuit;
A development processing circuit provided in the printer control unit for developing the intermediate data transferred by the bus master transfer circuit into bitmap data in units of bands;
The bitmap data provided in the printer control unit and developed by the development processing circuit is output to the print engine in units of bands to the print engine via the parallel or serial bus connecting the printer control unit and the print engine. An output circuit to
A printer system comprising: The printer system according to claim 4 , wherein the timer circuit is activated by a page synchronization signal input from the print engine. The printer system according to claim 4 , wherein the bus master circuit is installed on a system bus of a host computer. Print control method in printer system comprising host computer, printer control unit, print engine, parallel or serial bus connecting host computer and printer control unit, and parallel or serial bus connecting printer control unit and print engine In
A conversion step that is executed inside the host computer and converts print data described in a page description language into intermediate data in units of bands that are band-like regions in print output;
A step executed in the host computer, wherein the intermediate data in the band unit is transferred from the host computer to the printer controller via the parallel or serial bus connecting the host computer and the printer controller. A DMA transfer step for performing the transfer;
A step executed by using a timer circuit inside the host computer, loading a stored value from a constant register storing a constant based on a time required for the print engine to process an area corresponding to one band; The timer circuit counts the time required for the print engine to process an area corresponding to one band, and based on the count, the intermediate data is transferred from the host computer to the printer controller in units of bands. Determining the timing of a DMA transfer step for transferring data via the parallel or serial bus;
A step of executing in the printer control unit, a step of developing the intermediate data transferred in the DMA transfer step into bitmap data in units of bands;
A step executed in the printer control unit, and the bitmap data developed in the development processing step is connected to the print engine in units of bands via the parallel or serial bus connecting the printer control unit and the print engine. An output step of outputting to the print engine;
A print control method characterized by comprising:

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